fvp_common.c 7.66 KB
Newer Older
1
/*
2
 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
3
 *
dp-arm's avatar
dp-arm committed
4
 * SPDX-License-Identifier: BSD-3-Clause
5
6
 */

7
8
#include <arm_config.h>
#include <arm_def.h>
9
10
#include <assert.h>
#include <cci.h>
11
#include <ccn.h>
12
#include <debug.h>
13
#include <gicv2.h>
14
#include <mmio.h>
15
16
#include <plat_arm.h>
#include <v2m_def.h>
17
#include "../fvp_def.h"
18

19
20
21
22
23
/* Defines for GIC Driver build time selection */
#define FVP_GICV2		1
#define FVP_GICV3		2
#define FVP_GICV3_LEGACY	3

24
/*******************************************************************************
25
26
 * arm_config holds the characteristics of the differences between the three FVP
 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
27
28
29
 * at each boot stage by the primary before enabling the MMU (to allow
 * interconnect configuration) & used thereafter. Each BL will have its own copy
 * to allow independent operation.
30
 ******************************************************************************/
31
arm_config_t arm_config;
32
33
34
35
36
37
38
39
40

#define MAP_DEVICE0	MAP_REGION_FLAT(DEVICE0_BASE,			\
					DEVICE0_SIZE,			\
					MT_DEVICE | MT_RW | MT_SECURE)

#define MAP_DEVICE1	MAP_REGION_FLAT(DEVICE1_BASE,			\
					DEVICE1_SIZE,			\
					MT_DEVICE | MT_RW | MT_SECURE)

41
42
43
44
/*
 * Need to be mapped with write permissions in order to set a new non-volatile
 * counter value.
 */
45
46
#define MAP_DEVICE2	MAP_REGION_FLAT(DEVICE2_BASE,			\
					DEVICE2_SIZE,			\
47
					MT_DEVICE | MT_RW | MT_SECURE)
48
49


50
/*
51
52
53
 * Table of memory regions for various BL stages to map using the MMU.
 * This doesn't include Trusted SRAM as arm_setup_page_tables() already
 * takes care of mapping it.
54
55
56
 *
 * The flash needs to be mapped as writable in order to erase the FIP's Table of
 * Contents in case of unrecoverable error (see plat_error_handler()).
57
 */
58
#ifdef IMAGE_BL1
59
60
const mmap_region_t plat_arm_mmap[] = {
	ARM_MAP_SHARED_RAM,
61
	V2M_MAP_FLASH0_RW,
62
	V2M_MAP_IOFPGA,
63
64
	MAP_DEVICE0,
	MAP_DEVICE1,
65
#if TRUSTED_BOARD_BOOT
66
67
68
	/* To access the Root of Trust Public Key registers. */
	MAP_DEVICE2,
	/* Map DRAM to authenticate NS_BL2U image. */
69
70
	ARM_MAP_NS_DRAM1,
#endif
71
72
73
	{0}
};
#endif
74
#ifdef IMAGE_BL2
75
76
const mmap_region_t plat_arm_mmap[] = {
	ARM_MAP_SHARED_RAM,
77
	V2M_MAP_FLASH0_RW,
78
	V2M_MAP_IOFPGA,
79
80
	MAP_DEVICE0,
	MAP_DEVICE1,
81
	ARM_MAP_NS_DRAM1,
82
#ifdef SPD_tspd
83
	ARM_MAP_TSP_SEC_MEM,
84
#endif
85
86
87
88
#if TRUSTED_BOARD_BOOT
	/* To access the Root of Trust Public Key registers. */
	MAP_DEVICE2,
#endif
David Wang's avatar
David Wang committed
89
90
#if ARM_BL31_IN_DRAM
	ARM_MAP_BL31_SEC_DRAM,
91
92
93
#endif
#ifdef SPD_opteed
	ARM_OPTEE_PAGEABLE_LOAD_MEM,
David Wang's avatar
David Wang committed
94
#endif
95
96
97
	{0}
};
#endif
98
#ifdef IMAGE_BL2U
99
100
101
102
103
104
const mmap_region_t plat_arm_mmap[] = {
	MAP_DEVICE0,
	V2M_MAP_IOFPGA,
	{0}
};
#endif
105
#ifdef IMAGE_BL31
106
107
108
const mmap_region_t plat_arm_mmap[] = {
	ARM_MAP_SHARED_RAM,
	V2M_MAP_IOFPGA,
109
110
111
112
113
	MAP_DEVICE0,
	MAP_DEVICE1,
	{0}
};
#endif
114
#ifdef IMAGE_BL32
115
const mmap_region_t plat_arm_mmap[] = {
116
117
118
#ifdef AARCH32
	ARM_MAP_SHARED_RAM,
#endif
119
	V2M_MAP_IOFPGA,
120
121
	MAP_DEVICE0,
	MAP_DEVICE1,
122
123
	{0}
};
124
#endif
125

126
ARM_CASSERT_MMAP
127

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
#if FVP_INTERCONNECT_DRIVER != FVP_CCN
static const int fvp_cci400_map[] = {
	PLAT_FVP_CCI400_CLUS0_SL_PORT,
	PLAT_FVP_CCI400_CLUS1_SL_PORT,
};

static const int fvp_cci5xx_map[] = {
	PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
	PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
};

static unsigned int get_interconnect_master(void)
{
	unsigned int master;
	u_register_t mpidr;

	mpidr = read_mpidr_el1();
	master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ?
		MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);

	assert(master < FVP_CLUSTER_COUNT);
	return master;
}
#endif
152

153
154
155
156
157
158
159
/*******************************************************************************
 * A single boot loader stack is expected to work on both the Foundation FVP
 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
 * SYS_ID register provides a mechanism for detecting the differences between
 * these platforms. This information is stored in a per-BL array to allow the
 * code to take the correct path.Per BL platform configuration.
 ******************************************************************************/
160
void fvp_config_setup(void)
161
{
162
	unsigned int rev, hbi, bld, arch, sys_id;
163

164
165
166
167
168
	sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
	rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
	hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
	bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
	arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
169

170
171
	if (arch != ARCH_MODEL) {
		ERROR("This firmware is for FVP models\n");
172
		panic();
173
	}
174
175
176
177
178
179
180

	/*
	 * The build field in the SYS_ID tells which variant of the GIC
	 * memory is implemented by the model.
	 */
	switch (bld) {
	case BLD_GIC_VE_MMAP:
181
182
		ERROR("Legacy Versatile Express memory map for GIC peripheral"
				" is not supported\n");
183
		panic();
184
185
186
187
		break;
	case BLD_GIC_A53A57_MMAP:
		break;
	default:
188
189
		ERROR("Unsupported board build %x\n", bld);
		panic();
190
191
192
193
194
195
196
	}

	/*
	 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
	 * for the Foundation FVP.
	 */
	switch (hbi) {
197
198
	case HBI_FOUNDATION_FVP:
		arm_config.flags = 0;
199
200
201
202
203
204

		/*
		 * Check for supported revisions of Foundation FVP
		 * Allow future revisions to run but emit warning diagnostic
		 */
		switch (rev) {
205
206
207
		case REV_FOUNDATION_FVP_V2_0:
		case REV_FOUNDATION_FVP_V2_1:
		case REV_FOUNDATION_FVP_v9_1:
208
		case REV_FOUNDATION_FVP_v9_6:
209
210
211
212
213
			break;
		default:
			WARN("Unrecognized Foundation FVP revision %x\n", rev);
			break;
		}
214
		break;
215
	case HBI_BASE_FVP:
216
		arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
217
218
219
220
221
222

		/*
		 * Check for supported revisions
		 * Allow future revisions to run but emit warning diagnostic
		 */
		switch (rev) {
223
		case REV_BASE_FVP_V0:
224
225
226
			arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
			break;
		case REV_BASE_FVP_REVC:
227
			arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
228
					ARM_CONFIG_FVP_HAS_CCI5XX);
229
230
231
232
233
			break;
		default:
			WARN("Unrecognized Base FVP revision %x\n", rev);
			break;
		}
234
235
		break;
	default:
236
237
		ERROR("Unsupported board HBI number 0x%x\n", hbi);
		panic();
238
	}
239
240
241
242
243
244
245
246

	/*
	 * We assume that the presence of MT bit, and therefore shifted
	 * affinities, is uniform across the platform: either all CPUs, or no
	 * CPUs implement it.
	 */
	if (read_mpidr_el1() & MPIDR_MT_MASK)
		arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
247
}
248

249

250
void fvp_interconnect_init(void)
251
{
252
#if FVP_INTERCONNECT_DRIVER == FVP_CCN
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
	if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
		ERROR("Unrecognized CCN variant detected. Only CCN-502"
				" is supported");
		panic();
	}

	plat_arm_interconnect_init();
#else
	uintptr_t cci_base = 0;
	const int *cci_map = 0;
	unsigned int map_size = 0;

	if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
				ARM_CONFIG_FVP_HAS_CCI5XX))) {
		return;
	}

	/* Initialize the right interconnect */
	if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) {
		cci_base = PLAT_FVP_CCI5XX_BASE;
		cci_map = fvp_cci5xx_map;
		map_size = ARRAY_SIZE(fvp_cci5xx_map);
	} else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) {
		cci_base = PLAT_FVP_CCI400_BASE;
		cci_map = fvp_cci400_map;
		map_size = ARRAY_SIZE(fvp_cci400_map);
279
	}
280
281
282
283
284

	assert(cci_base);
	assert(cci_map);
	cci_init(cci_base, cci_map, map_size);
#endif
285
286
}

287
void fvp_interconnect_enable(void)
288
{
289
290
291
292
293
294
295
296
297
298
299
#if FVP_INTERCONNECT_DRIVER == FVP_CCN
	plat_arm_interconnect_enter_coherency();
#else
	unsigned int master;

	if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
				ARM_CONFIG_FVP_HAS_CCI5XX)) {
		master = get_interconnect_master();
		cci_enable_snoop_dvm_reqs(master);
	}
#endif
300
301
}

302
void fvp_interconnect_disable(void)
303
{
304
305
306
307
308
309
310
311
312
313
314
#if FVP_INTERCONNECT_DRIVER == FVP_CCN
	plat_arm_interconnect_exit_coherency();
#else
	unsigned int master;

	if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
				ARM_CONFIG_FVP_HAS_CCI5XX)) {
		master = get_interconnect_master();
		cci_disable_snoop_dvm_reqs(master);
	}
#endif
315
}