platform_def.h 6.9 KB
Newer Older
1
/*
2
 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
3
 *
dp-arm's avatar
dp-arm committed
4
 * SPDX-License-Identifier: BSD-3-Clause
5
6
7
8
9
 */

#ifndef __PLATFORM_DEF_H__
#define __PLATFORM_DEF_H__

10
11
12
13
14
#include <arm_def.h>
#include <board_arm_def.h>
#include <board_css_def.h>
#include <common_def.h>
#include <css_def.h>
15
16
17
#if TRUSTED_BOARD_BOOT
#include <mbedtls_config.h>
#endif
18
19
20
#include <soc_css_def.h>
#include <tzc400.h>
#include <v2m_def.h>
21
#include "../juno_def.h"
22

23
/* Required platform porting definitions */
24
25
26
/* Juno supports system power domain */
#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL2
#define PLAT_NUM_PWR_DOMAINS		(ARM_SYSTEM_COUNT + \
27
					JUNO_CLUSTER_COUNT + \
28
					PLATFORM_CORE_COUNT)
29
30
31
#define PLATFORM_CORE_COUNT		(JUNO_CLUSTER0_CORE_COUNT + \
					JUNO_CLUSTER1_CORE_COUNT)

32
33
34
/* Cryptocell HW Base address */
#define PLAT_CRYPTOCELL_BASE		0x60050000

35
/*
36
 * Other platform porting definitions are provided by included headers
37
 */
38

39
40
41
/*
 * Required ARM standard platform porting definitions
 */
42
#define PLAT_ARM_CLUSTER_COUNT		JUNO_CLUSTER_COUNT
43

44
45
/* Use the bypass address */
#define PLAT_ARM_TRUSTED_ROM_BASE	V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET
46
47

/*
48
49
50
 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB
 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of
 * flash
51
 */
52
#if TRUSTED_BOARD_BOOT
53
#define PLAT_ARM_TRUSTED_ROM_SIZE	0x00020000
54
#else
55
56
57
#define PLAT_ARM_TRUSTED_ROM_SIZE	0x00010000
#endif /* TRUSTED_BOARD_BOOT */

58
/*
59
 * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values
60
61
 * defined for ARM development platforms.
 */
62
#if ARM_BOARD_OPTIMISE_MEM
63
64
65
66
/*
 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
 * plat_arm_mmap array defined for each BL stage.
 */
67
#ifdef IMAGE_BL1
68
69
70
71
# define PLAT_ARM_MMAP_ENTRIES		7
# define MAX_XLAT_TABLES		4
#endif

72
#ifdef IMAGE_BL2
73
#ifdef SPD_opteed
74
# define PLAT_ARM_MMAP_ENTRIES		11
75
# define MAX_XLAT_TABLES		5
76
#else
77
# define PLAT_ARM_MMAP_ENTRIES		10
78
# define MAX_XLAT_TABLES		4
79
#endif
80
#endif
81

82
#ifdef IMAGE_BL2U
83
84
85
86
# define PLAT_ARM_MMAP_ENTRIES		4
# define MAX_XLAT_TABLES		3
#endif

87
#ifdef IMAGE_BL31
88
#  define PLAT_ARM_MMAP_ENTRIES		7
89
#  define MAX_XLAT_TABLES		3
90
91
#endif

92
#ifdef IMAGE_BL32
93
94
# define PLAT_ARM_MMAP_ENTRIES		5
# define MAX_XLAT_TABLES		4
95
96
#endif

97
98
99
100
101
/*
 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
 * plus a little space for growth.
 */
#if TRUSTED_BOARD_BOOT
102
# define PLAT_ARM_MAX_BL1_RW_SIZE	0xA000
103
104
105
106
107
108
109
110
111
#else
# define PLAT_ARM_MAX_BL1_RW_SIZE	0x6000
#endif

/*
 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
 * little space for growth.
 */
#if TRUSTED_BOARD_BOOT
112
113
114
115
116
#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
# define PLAT_ARM_MAX_BL2_SIZE		0x1E000
#else
# define PLAT_ARM_MAX_BL2_SIZE		0x1A000
#endif
117
118
119
120
121
122
123
#else
# define PLAT_ARM_MAX_BL2_SIZE		0xC000
#endif

/*
 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
 * little space for growth.
124
125
126
127
 * SCP_BL2 image is loaded into the space BL31 -> BL1_RW_BASE.
 * For TBB use case, PLAT_ARM_MAX_BL1_RW_SIZE has been increased and therefore
 * PLAT_ARM_MAX_BL31_SIZE has been increased to ensure SCP_BL2 has the same
 * space available.
128
 */
129
#define PLAT_ARM_MAX_BL31_SIZE		0x1E000
130

131
132
133
134
135
136
137
138
139
#if JUNO_AARCH32_EL3_RUNTIME
/*
 * PLAT_ARM_MAX_BL32_SIZE is calculated for SP_MIN as the AArch32 Secure
 * Payload. We also need to take care of SCP_BL2 size as well, as the SCP_BL2
 * is loaded into the space BL32 -> BL1_RW_BASE
 */
# define PLAT_ARM_MAX_BL32_SIZE		0x1E000
#endif

140
141
142
143
144
145
/*
 * Since free SRAM space is scant, enable the ASSERTION message size
 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40).
 */
#define PLAT_LOG_LEVEL_ASSERT		40

146
#endif /* ARM_BOARD_OPTIMISE_MEM */
147
148
149
150
151
152

/* CCI related constants */
#define PLAT_ARM_CCI_BASE		0x2c090000
#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX	4
#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX	3

153
154
155
/* System timer related constants */
#define PLAT_ARM_NSTIMER_FRAME_ID		1

156
/* TZC related constants */
157
#define PLAT_ARM_TZC_BASE		0x2a4a0000
158
159
160
161
162
163
164
165
166
167
168
#define PLAT_ARM_TZC_NS_DEV_ACCESS	(				\
		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400)	|	\
		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE)	|	\
		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0)	|	\
		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1)	|	\
		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB)	|	\
		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330)	|	\
		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS)	|	\
		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP)		|	\
		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU)	|	\
		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT))
169

170
/*
171
 * Required ARM CSS based platform porting definitions
172
 */
173
174

/* GIC related constants (no GICR in GIC-400) */
175
176
177
178
179
#define PLAT_ARM_GICD_BASE		0x2c010000
#define PLAT_ARM_GICC_BASE		0x2c02f000
#define PLAT_ARM_GICH_BASE		0x2c04f000
#define PLAT_ARM_GICV_BASE		0x2c06f000

180
181
182
/* MHU related constants */
#define PLAT_CSS_MHU_BASE		0x2b1f0000

183
184
185
/*
 * Base address of the first memory region used for communication between AP
 * and SCP. Used by the BOM and SCPI protocols.
Soby Mathew's avatar
Soby Mathew committed
186
187
188
 */
#if !CSS_USE_SCMI_SDS_DRIVER
/*
189
190
191
192
193
194
195
196
197
 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which
 * means the SCP/AP configuration data gets overwritten when the AP initiates
 * communication with the SCP. The configuration data is expected to be a
 * 32-bit word on all CSS platforms. On Juno, part of this configuration is
 * which CPU is the primary, according to the shift and mask definitions below.
 */
#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE	(ARM_TRUSTED_SRAM_BASE + 0x80)
#define PLAT_CSS_PRIMARY_CPU_SHIFT		8
#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH		4
Soby Mathew's avatar
Soby Mathew committed
198
#endif
199

200
201
202
203
/*
 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
 * SCP_BL2 size plus a little space for growth.
 */
204
#define PLAT_CSS_MAX_SCP_BL2_SIZE	0x14000
205

206
207
208
209
/*
 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
 * SCP_BL2U size plus a little space for growth.
 */
210
#define PLAT_CSS_MAX_SCP_BL2U_SIZE	0x14000
211

212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
	CSS_G1S_IRQ_PROPS(grp), \
	ARM_G1S_IRQ_PROPS(grp), \
	INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
		grp, GIC_INTR_CFG_LEVEL), \
	INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
		grp, GIC_INTR_CFG_LEVEL), \
	INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
		grp, GIC_INTR_CFG_LEVEL), \
	INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
		grp, GIC_INTR_CFG_LEVEL), \
	INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
		grp, GIC_INTR_CFG_LEVEL), \
	INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \
		grp, GIC_INTR_CFG_LEVEL), \
	INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \
		grp, GIC_INTR_CFG_LEVEL), \
	INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
		grp, GIC_INTR_CFG_LEVEL)

#define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
233

234
/*
235
 * Required ARM CSS SoC based platform porting definitions
236
 */
237
238
239
240

/* CSS SoC NIC-400 Global Programmers View (GPV) */
#define PLAT_SOC_CSS_NIC400_BASE	0x2a000000

241
#endif /* __PLATFORM_DEF_H__ */