bl2.ld.S 4.05 KB
Newer Older
1
/*
2
 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
3
 *
dp-arm's avatar
dp-arm committed
4
 * SPDX-License-Identifier: BSD-3-Clause
5
6
 */

7
#include <platform_def.h>
8
#include <xlat_tables_defs.h>
9
10
11

OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12
ENTRY(bl2_entrypoint)
13
14

MEMORY {
15
    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
16
17
18
19
20
21
}


SECTIONS
{
    . = BL2_BASE;
22
    ASSERT(. == ALIGN(PAGE_SIZE),
23
           "BL2_BASE address is not aligned on a page boundary.")
24

25
26
27
28
29
30
#if SEPARATE_CODE_AND_RODATA
    .text . : {
        __TEXT_START__ = .;
        *bl2_entrypoint.o(.text*)
        *(.text*)
        *(.vectors)
31
        . = NEXT(PAGE_SIZE);
32
33
34
35
36
37
38
39
40
41
42
43
44
        __TEXT_END__ = .;
     } >RAM

    .rodata . : {
        __RODATA_START__ = .;
        *(.rodata*)

        /* Ensure 8-byte alignment for descriptors and ensure inclusion */
        . = ALIGN(8);
        __PARSER_LIB_DESCS_START__ = .;
        KEEP(*(.img_parser_lib_descs))
        __PARSER_LIB_DESCS_END__ = .;

45
        . = NEXT(PAGE_SIZE);
46
47
48
        __RODATA_END__ = .;
    } >RAM
#else
49
50
    ro . : {
        __RO_START__ = .;
Andrew Thoelke's avatar
Andrew Thoelke committed
51
52
        *bl2_entrypoint.o(.text*)
        *(.text*)
53
        *(.rodata*)
54
55
56
57
58
59
60

        /* Ensure 8-byte alignment for descriptors and ensure inclusion */
        . = ALIGN(8);
        __PARSER_LIB_DESCS_START__ = .;
        KEEP(*(.img_parser_lib_descs))
        __PARSER_LIB_DESCS_END__ = .;

Achin Gupta's avatar
Achin Gupta committed
61
        *(.vectors)
62
63
64
65
66
67
        __RO_END_UNALIGNED__ = .;
        /*
         * Memory page(s) mapped to this section will be marked as
         * read-only, executable.  No RW data from the next section must
         * creep in.  Ensure the rest of the current memory page is unused.
         */
68
        . = NEXT(PAGE_SIZE);
69
        __RO_END__ = .;
70
    } >RAM
71
#endif
72

73
74
75
76
77
78
    /*
     * Define a linker symbol to mark start of the RW memory area for this
     * image.
     */
    __RW_START__ = . ;

79
80
81
82
83
    /*
     * .data must be placed at a lower address than the stacks if the stack
     * protector is enabled. Alternatively, the .data.stack_protector_canary
     * section can be placed independently of the main .data section.
     */
84
85
    .data . : {
        __DATA_START__ = .;
Andrew Thoelke's avatar
Andrew Thoelke committed
86
        *(.data*)
87
        __DATA_END__ = .;
88
89
    } >RAM

90
91
92
93
    stacks (NOLOAD) : {
        __STACKS_START__ = .;
        *(tzfw_normal_stacks)
        __STACKS_END__ = .;
94
95
    } >RAM

96
97
    /*
     * The .bss section gets initialised to 0 at runtime.
98
99
     * Its base address should be 16-byte aligned for better performance of the
     * zero-initialization code.
100
101
102
     */
    .bss : ALIGN(16) {
        __BSS_START__ = .;
Andrew Thoelke's avatar
Andrew Thoelke committed
103
        *(SORT_BY_ALIGNMENT(.bss*))
104
        *(COMMON)
105
        __BSS_END__ = .;
106
107
    } >RAM

108
    /*
109
     * The xlat_table section is for full, aligned page tables (4K).
110
     * Removing them from .bss avoids forcing 4K alignment on
111
112
     * the .bss section. The tables are initialized to zero by the translation
     * tables library.
113
114
115
116
117
     */
    xlat_table (NOLOAD) : {
        *(xlat_table)
    } >RAM

118
#if USE_COHERENT_MEM
119
120
121
122
123
124
    /*
     * The base address of the coherent memory section must be page-aligned (4K)
     * to guarantee that the coherent data are stored on their own pages and
     * are not mixed with normal data.  This is required to set up the correct
     * memory attributes for the coherent data page tables.
     */
125
    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
126
127
128
129
130
131
132
133
        __COHERENT_RAM_START__ = .;
        *(tzfw_coherent_mem)
        __COHERENT_RAM_END_UNALIGNED__ = .;
        /*
         * Memory page(s) mapped to this section will be marked
         * as device memory.  No other unexpected data must creep in.
         * Ensure the rest of the current memory page is unused.
         */
134
        . = NEXT(PAGE_SIZE);
135
        __COHERENT_RAM_END__ = .;
136
    } >RAM
137
#endif
138

139
140
141
142
143
    /*
     * Define a linker symbol to mark end of the RW memory area for this
     * image.
     */
    __RW_END__ = .;
144
    __BL2_END__ = .;
145

146
    __BSS_SIZE__ = SIZEOF(.bss);
147
148

#if USE_COHERENT_MEM
149
150
    __COHERENT_RAM_UNALIGNED_SIZE__ =
        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
151
#endif
152
153

    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
154
}