fvp_pm.c 10.2 KB
Newer Older
1
/*
2
 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3
 *
dp-arm's avatar
dp-arm committed
4
 * SPDX-License-Identifier: BSD-3-Clause
5
6
7
 */

#include <arch_helpers.h>
8
#include <arm_config.h>
9
#include <assert.h>
10
#include <debug.h>
11
#include <errno.h>
12
13
#include <mmio.h>
#include <platform.h>
14
#include <plat_arm.h>
15
#include <psci.h>
16
#include <v2m_def.h>
17
#include "drivers/pwrc/fvp_pwrc.h"
18
19
#include "fvp_def.h"
#include "fvp_private.h"
20

21

22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
#if ARM_RECOM_STATE_ID_ENC
/*
 *  The table storing the valid idle power states. Ensure that the
 *  array entries are populated in ascending order of state-id to
 *  enable us to use binary search during power state validation.
 *  The table must be terminated by a NULL entry.
 */
const unsigned int arm_pm_idle_states[] = {
	/* State-id - 0x01 */
	arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
			ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
	/* State-id - 0x02 */
	arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
			ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
	/* State-id - 0x22 */
	arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
			ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
	0,
};
#endif

43
44
45
46
/*******************************************************************************
 * Function which implements the common FVP specific operations to power down a
 * cluster in response to a CPU_OFF or CPU_SUSPEND request.
 ******************************************************************************/
47
static void fvp_cluster_pwrdwn_common(void)
48
49
50
{
	uint64_t mpidr = read_mpidr_el1();

51
52
53
54
55
56
57
58
#if ENABLE_SPE_FOR_LOWER_ELS
	/*
	 * On power down we need to disable statistical profiling extensions
	 * before exiting coherency.
	 */
	arm_disable_spe();
#endif

59
	/* Disable coherency if this cluster is to be turned off */
60
	fvp_interconnect_disable();
61
62
63
64
65

	/* Program the power controller to turn the cluster off */
	fvp_pwrc_write_pcoffr(mpidr);
}

66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state)
{
	unsigned long mpidr;

	assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
					ARM_LOCAL_STATE_OFF);

	/* Get the mpidr for this cpu */
	mpidr = read_mpidr_el1();

	/* Perform the common cluster specific operations */
	if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
					ARM_LOCAL_STATE_OFF) {
		/*
		 * This CPU might have woken up whilst the cluster was
		 * attempting to power down. In this case the FVP power
		 * controller will have a pending cluster power off request
		 * which needs to be cleared by writing to the PPONR register.
		 * This prevents the power controller from interpreting a
		 * subsequent entry of this cpu into a simple wfi as a power
		 * down request.
		 */
		fvp_pwrc_write_pponr(mpidr);

		/* Enable coherency if this cluster was off */
91
		fvp_interconnect_enable();
92
93
94
95
96
97
98
99
100
101
	}

	/*
	 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
	 * with a cpu power down unless the bit is set again
	 */
	fvp_pwrc_clr_wen(mpidr);
}


102
/*******************************************************************************
103
 * FVP handler called when a CPU is about to enter standby.
104
 ******************************************************************************/
105
void fvp_cpu_standby(plat_local_state_t cpu_state)
106
{
107
108
109

	assert(cpu_state == ARM_LOCAL_STATE_RET);

110
111
112
113
114
	/*
	 * Enter standby state
	 * dsb is good practice before using wfi to enter low power states
	 */
	dsb();
115
116
117
	wfi();
}

118
/*******************************************************************************
119
120
 * FVP handler called when a power domain is about to be turned on. The
 * mpidr determines the CPU to be turned on.
121
 ******************************************************************************/
122
int fvp_pwr_domain_on(u_register_t mpidr)
123
124
125
126
127
{
	int rc = PSCI_E_SUCCESS;
	unsigned int psysr;

	/*
128
129
130
	 * Ensure that we do not cancel an inflight power off request for the
	 * target cpu. That would leave it in a zombie wfi. Wait for it to power
	 * off and then program the power controller to turn that CPU on.
131
132
133
134
135
136
137
138
139
140
	 */
	do {
		psysr = fvp_pwrc_read_psysr(mpidr);
	} while (psysr & PSYSR_AFF_L0);

	fvp_pwrc_write_pponr(mpidr);
	return rc;
}

/*******************************************************************************
141
142
 * FVP handler called when a power domain is about to be turned off. The
 * target_state encodes the power state that each level should transition to.
143
 ******************************************************************************/
144
void fvp_pwr_domain_off(const psci_power_state_t *target_state)
145
{
146
147
	assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
					ARM_LOCAL_STATE_OFF);
148

149
	/*
150
151
152
	 * If execution reaches this stage then this power domain will be
	 * suspended. Perform at least the cpu specific actions followed
	 * by the cluster specific operations if applicable.
153
	 */
154
155
156
157
158
159
160
161
162

	/* Prevent interrupts from spuriously waking up this cpu */
	plat_arm_gic_cpuif_disable();

	/* Turn redistributor off */
	plat_arm_gic_redistif_off();

	/* Program the power controller to power off this cpu. */
	fvp_pwrc_write_ppoffr(read_mpidr_el1());
163

164
165
	if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
					ARM_LOCAL_STATE_OFF)
166
167
		fvp_cluster_pwrdwn_common();

168
169
170
}

/*******************************************************************************
171
172
 * FVP handler called when a power domain is about to be suspended. The
 * target_state encodes the power state that each level should transition to.
173
 ******************************************************************************/
174
void fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
175
{
176
177
	unsigned long mpidr;

178
179
180
181
182
183
	/*
	 * FVP has retention only at cpu level. Just return
	 * as nothing is to be done for retention.
	 */
	if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
					ARM_LOCAL_STATE_RET)
184
		return;
185

186
187
188
	assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
					ARM_LOCAL_STATE_OFF);

189
190
191
	/* Get the mpidr for this cpu */
	mpidr = read_mpidr_el1();

192
193
194
	/* Program the power controller to enable wakeup interrupts. */
	fvp_pwrc_set_wen(mpidr);

195
196
197
198
199
200
201
202
203
204
205
	/* Prevent interrupts from spuriously waking up this cpu */
	plat_arm_gic_cpuif_disable();

	/*
	 * The Redistributor is not powered off as it can potentially prevent
	 * wake up events reaching the CPUIF and/or might lead to losing
	 * register context.
	 */

	/* Program the power controller to power off this cpu. */
	fvp_pwrc_write_ppoffr(read_mpidr_el1());
206
207

	/* Perform the common cluster specific operations */
208
209
	if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
					ARM_LOCAL_STATE_OFF)
210
		fvp_cluster_pwrdwn_common();
211
212
213
}

/*******************************************************************************
214
215
216
 * FVP handler called when a power domain has just been powered on after
 * being turned off earlier. The target_state encodes the low power state that
 * each level has woken up from.
217
 ******************************************************************************/
218
void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
219
{
220
	fvp_power_domain_on_finish_common(target_state);
221

222
	/* Enable the gic cpu interface */
223
224
225
226
	plat_arm_gic_pcpu_init();

	/* Program the gic per-cpu distributor or re-distributor interface */
	plat_arm_gic_cpuif_enable();
227
228
229
}

/*******************************************************************************
230
231
232
 * FVP handler called when a power domain has just been powered on after
 * having been suspended earlier. The target_state encodes the low power state
 * that each level has woken up from.
233
234
235
 * TODO: At the moment we reuse the on finisher and reinitialize the secure
 * context. Need to implement a separate suspend finisher.
 ******************************************************************************/
236
void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
237
{
238
239
240
241
242
243
244
	/*
	 * Nothing to be done on waking up from retention from CPU level.
	 */
	if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
					ARM_LOCAL_STATE_RET)
		return;

245
246
247
	fvp_power_domain_on_finish_common(target_state);

	/* Enable the gic cpu interface */
248
	plat_arm_gic_cpuif_enable();
249
250
}

251
252
253
254
255
256
/*******************************************************************************
 * FVP handlers to shutdown/reboot the system
 ******************************************************************************/
static void __dead2 fvp_system_off(void)
{
	/* Write the System Configuration Control Register */
257
258
259
260
	mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
		V2M_CFGCTRL_START |
		V2M_CFGCTRL_RW |
		V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
261
262
263
264
265
266
267
268
	wfi();
	ERROR("FVP System Off: operation not handled.\n");
	panic();
}

static void __dead2 fvp_system_reset(void)
{
	/* Write the System Configuration Control Register */
269
270
271
272
	mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
		V2M_CFGCTRL_START |
		V2M_CFGCTRL_RW |
		V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
273
274
275
276
	wfi();
	ERROR("FVP System Reset: operation not handled.\n");
	panic();
}
277

278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
static int fvp_node_hw_state(u_register_t target_cpu,
			     unsigned int power_level)
{
	unsigned int psysr;
	int ret;

	/*
	 * The format of 'power_level' is implementation-defined, but 0 must
	 * mean a CPU. We also allow 1 to denote the cluster
	 */
	if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1)
		return PSCI_E_INVALID_PARAMS;

	/*
	 * Read the status of the given MPDIR from FVP power controller. The
	 * power controller only gives us on/off status, so map that to expected
	 * return values of the PSCI call
	 */
	psysr = fvp_pwrc_read_psysr(target_cpu);
	if (psysr == PSYSR_INVALID)
		return PSCI_E_INVALID_PARAMS;

	switch (power_level) {
	case ARM_PWR_LVL0:
		ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF;
		break;
	case ARM_PWR_LVL1:
		ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF;
		break;
	}

	return ret;
}

312
/*******************************************************************************
313
314
 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
 * platform layer will take care of registering the handlers with PSCI.
315
 ******************************************************************************/
316
plat_psci_ops_t plat_arm_psci_pm_ops = {
317
318
319
320
321
322
	.cpu_standby = fvp_cpu_standby,
	.pwr_domain_on = fvp_pwr_domain_on,
	.pwr_domain_off = fvp_pwr_domain_off,
	.pwr_domain_suspend = fvp_pwr_domain_suspend,
	.pwr_domain_on_finish = fvp_pwr_domain_on_finish,
	.pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish,
323
	.system_off = fvp_system_off,
324
	.system_reset = fvp_system_reset,
325
	.validate_power_state = arm_validate_power_state,
326
327
	.validate_ns_entrypoint = arm_validate_ns_entrypoint,
	.get_node_hw_state = fvp_node_hw_state
328
};