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Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1.  The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics.  This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.

SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3