• Jeenu Viswambharan's avatar
    BL31: Program Priority Mask for SMC handling · 3d732e23
    Jeenu Viswambharan authored
    
    
    On GICv3 systems, as a side effect of adding provision to handle EL3
    interrupts (unconditionally routing FIQs to EL3), pending Non-secure
    interrupts (signalled as FIQs) may preempt execution in lower Secure ELs
    [1]. This will inadvertently disrupt the semantics of Fast SMC
    (previously called Atomic SMC) calls.
    
    To retain semantics of Fast SMCs, the GIC PMR must be programmed to
    prevent Non-secure interrupts from preempting Secure execution. To that
    effect, two new functions in the Exception Handling Framework subscribe
    to events introduced in an earlier commit:
    
      - Upon 'cm_exited_normal_world', the Non-secure PMR is stashed, and
        the PMR is programmed to the highest Non-secure interrupt priority.
    
      - Upon 'cm_entering_normal_world', the previously stashed Non-secure
        PMR is restored.
    
    The above sequence however prevents Yielding SMCs from being preempted
    by Non-secure interrupts as intended. To facilitate this, the public API
    exc_allow_ns_preemption() is introduced that programs the PMR to the
    original Non-secure PMR value. Another API
    exc_is_ns_preemption_allowed() is also introduced to check if
    exc_allow_ns_preemption() had been called previously.
    
    API documentation to follow.
    
    [1] On GICv2 systems, this isn't a problem as, unlike GICv3, pending NS
        IRQs during Secure execution are signalled as IRQs, which aren't
        routed to EL3.
    
    Change-Id: Ief96b162b0067179b1012332cd991ee1b3051dd0
    Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
    3d732e23
ehf.c 14.5 KB