• Antonio Nino Diaz's avatar
    Disable processor Cycle Counting in Secure state · ed4fc6f0
    Antonio Nino Diaz authored
    
    
    In a system with ARMv8.5-PMU implemented:
    
    - If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting
      in Secure state in PMCCNTR.
    
    - If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in
      Secure state in PMCCNTR_EL0.
    
    So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64)
    or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure
    as any EL can change that value.
    
    Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f
    Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
    ed4fc6f0
arch.h 21.1 KB