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Neoverse V1 erratum 1940577 is a Cat B erratum, present in some
revisions of the V1 processor core.  The workaround is to insert a
DMB ST before acquire atomic instructions without release semantics.
This issue is present in revisions r0p0 - r1p1  but this workaround
only applies to revisions r1p0 - r1p1, there is no workaround for older
versions.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I210ad7d8f31c81b6ac51b028dfbce75a725c11aa