• Andrew Thoelke's avatar
    Re-design bakery lock memory allocation and algorithm · ee7b35c4
    Andrew Thoelke authored
    This patch unifies the bakery lock api's across coherent and normal
    memory implementation of locks by using same data type `bakery_lock_t`
    and similar arguments to functions.
    
    A separate section `bakery_lock` has been created and used to allocate
    memory for bakery locks using `DEFINE_BAKERY_LOCK`. When locks are
    allocated in normal memory, each lock for a core has to spread
    across multiple cache lines. By using the total size allocated in a
    separate cache line for a single core at compile time, the memory for
    other core locks is allocated at link time by multiplying the single
    core locks size with (PLATFORM_CORE_COUNT - 1). The normal memory lock
    algorithm now uses lock address instead of the `id` in the per_cpu_data.
    For locks allocated in coherent memory, it moves locks from
    tzfw_coherent_memory to bakery_lock section.
    
    The bakery locks are allocated as part of bss or in coherent memory
    depending on usage of coherent memory. Both these regions are
    initialised to zero as part of run_time_init before locks are used.
    Hence, bakery_lock_init() is made an empty function as the lock memory
    is already initialised to zero.
    
    The above design lead to the removal of psci bakery locks from
    non_cpu_power_pd_node to psci_locks.
    
    NOTE: THE BAKERY LOCK API WHEN USE_COHERENT_MEM IS NOT SET HAS CHANGED.
    THIS IS A BREAKING CHANGE FOR ALL PLATFORM PORTS THAT ALLOCATE BAKERY
    LOCKS IN NORMAL MEMORY.
    
    Change-Id: Ic3751c0066b8032dcbf9d88f1d4dc73d15f61d8b
    ee7b35c4
psci_common.c 33.9 KB