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Commit 0258840e authored by Varun Wadekar's avatar Varun Wadekar
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Tegra: drivers: memctrl: move chip specific defines to tegra_def.h 



This patch moves the chip specific memory controller driver defines to
the appropriate tegra_def.h files, for future compatibility.

Change-Id: I3179fb771d8b32e913ca29bd94af95f4b2fc1961
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
parent dec349c8
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Inline Side-by-side
plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
View file @ 0258840e
...@@ -43,7 +43,7 @@ ...@@ -43,7 +43,7 @@
#define GPU_RESET_BIT (1 << 24) #define GPU_RESET_BIT (1 << 24)
/* Video Memory base and size (live values) */ /* Video Memory base and size (live values) */
static uintptr_t video_mem_base; static uint64_t video_mem_base;
static uint64_t video_mem_size; static uint64_t video_mem_size;
/* /*
...@@ -85,7 +85,9 @@ void tegra_memctrl_setup(void) ...@@ -85,7 +85,9 @@ void tegra_memctrl_setup(void)
(void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */
/* video memory carveout */ /* video memory carveout */
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base); tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
(uint32_t)(video_mem_base >> 32));
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)video_mem_base);
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size);
} }
...@@ -208,7 +210,8 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) ...@@ -208,7 +210,8 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
enable_mmu_el3(0); enable_mmu_el3(0);
done: done:
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base); tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32));
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base);
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
/* store new values */ /* store new values */
......
plat/nvidia/tegra/include/drivers/memctrl_v1.h
View file @ 0258840e
...@@ -60,14 +60,6 @@ ...@@ -60,14 +60,6 @@
#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 #define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98
#define MC_SMMU_TRANSLATION_ENABLE (~0) #define MC_SMMU_TRANSLATION_ENABLE (~0)
/* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70
#define MC_SECURITY_CFG1_0 0x74
/* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE 0x648
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
static inline uint32_t tegra_mc_read_32(uint32_t off) static inline uint32_t tegra_mc_read_32(uint32_t off)
{ {
return mmio_read_32(TEGRA_MC_BASE + off); return mmio_read_32(TEGRA_MC_BASE + off);
......
plat/nvidia/tegra/include/drivers/memctrl_v2.h
View file @ 0258840e
...@@ -352,51 +352,6 @@ typedef struct mc_streamid_security_cfg { ...@@ -352,51 +352,6 @@ typedef struct mc_streamid_security_cfg {
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
/*******************************************************************************
* TZDRAM carveout configuration registers
******************************************************************************/
#define MC_SECURITY_CFG0_0 0x70
#define MC_SECURITY_CFG1_0 0x74
#define MC_SECURITY_CFG3_0 0x9BC
/*******************************************************************************
* Video Memory carveout configuration registers
******************************************************************************/
#define MC_VIDEO_PROTECT_BASE_HI 0x978
#define MC_VIDEO_PROTECT_BASE_LO 0x648
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
/*******************************************************************************
* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers
******************************************************************************/
#define MC_TZRAM_BASE_LO 0x2194
#define TZRAM_BASE_LO_SHIFT 12
#define TZRAM_BASE_LO_MASK 0xFFFFF
#define MC_TZRAM_BASE_HI 0x2198
#define TZRAM_BASE_HI_SHIFT 0
#define TZRAM_BASE_HI_MASK 3
#define MC_TZRAM_SIZE 0x219C
#define TZRAM_SIZE_RANGE_4KB_SHIFT 27
#define MC_TZRAM_CARVEOUT_CFG 0x2190
#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1)
#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0)
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4
#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25)
#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7)
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC
/******************************************************************************* /*******************************************************************************
* Memory Controller Reset Control registers * Memory Controller Reset Control registers
******************************************************************************/ ******************************************************************************/
......
plat/nvidia/tegra/include/t132/tegra_def.h
View file @ 0258840e
...@@ -104,6 +104,16 @@ ...@@ -104,6 +104,16 @@
******************************************************************************/ ******************************************************************************/
#define TEGRA_MC_BASE 0x70019000 #define TEGRA_MC_BASE 0x70019000
/* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70
#define MC_SECURITY_CFG1_0 0x74
#define MC_SECURITY_CFG3_0 0x9BC
/* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE_HI 0x978
#define MC_VIDEO_PROTECT_BASE_LO 0x648
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
/******************************************************************************* /*******************************************************************************
* Tegra TZRAM constants * Tegra TZRAM constants
******************************************************************************/ ******************************************************************************/
......
plat/nvidia/tegra/include/t186/tegra_def.h
View file @ 0258840e
...@@ -120,6 +120,45 @@ ...@@ -120,6 +120,45 @@
#define TEGRA_MC_STREAMID_BASE 0x02C00000 #define TEGRA_MC_STREAMID_BASE 0x02C00000
#define TEGRA_MC_BASE 0x02C10000 #define TEGRA_MC_BASE 0x02C10000
/* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70
#define MC_SECURITY_CFG1_0 0x74
#define MC_SECURITY_CFG3_0 0x9BC
/* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE_HI 0x978
#define MC_VIDEO_PROTECT_BASE_LO 0x648
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
#define MC_TZRAM_BASE_LO 0x2194
#define TZRAM_BASE_LO_SHIFT 12
#define TZRAM_BASE_LO_MASK 0xFFFFF
#define MC_TZRAM_BASE_HI 0x2198
#define TZRAM_BASE_HI_SHIFT 0
#define TZRAM_BASE_HI_MASK 3
#define MC_TZRAM_SIZE 0x219C
#define TZRAM_SIZE_RANGE_4KB_SHIFT 27
#define MC_TZRAM_CARVEOUT_CFG 0x2190
#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1)
#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0)
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4
#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25)
#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7)
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8
#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC
/******************************************************************************* /*******************************************************************************
* Tegra UART Controller constants * Tegra UART Controller constants
******************************************************************************/ ******************************************************************************/
......
plat/nvidia/tegra/include/t210/tegra_def.h
View file @ 0258840e
...@@ -129,6 +129,16 @@ ...@@ -129,6 +129,16 @@
******************************************************************************/ ******************************************************************************/
#define TEGRA_MC_BASE 0x70019000 #define TEGRA_MC_BASE 0x70019000
/* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70
#define MC_SECURITY_CFG1_0 0x74
#define MC_SECURITY_CFG3_0 0x9BC
/* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE_HI 0x978
#define MC_VIDEO_PROTECT_BASE_LO 0x648
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
/******************************************************************************* /*******************************************************************************
* Tegra TZRAM constants * Tegra TZRAM constants
******************************************************************************/ ******************************************************************************/
......
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