From 0435ba642de40d50f8d162a8942091d2ff938051 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Wed, 20 Jun 2018 17:03:57 +0530
Subject: [PATCH] plat: xilinx: zynqmp: Get chipid from registers for BL32
This patch reads the chipid registers directly instead of making
pm call when running at BL32. User should ensure that these registers
should always be accessed from APU in their system configuration.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
---
plat/xilinx/zynqmp/aarch64/zynqmp_common.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index b144c84bd..c3612706a 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -205,12 +205,21 @@ static char *zynqmp_get_silicon_idcode_name(void)
{
uint32_t id, ver, chipid[2];
size_t i, j, len;
- enum pm_ret_status ret;
const char *name = "EG/EV";
- ret = pm_get_chipid(chipid);
- if (ret)
+#ifdef IMAGE_BL32
+ /*
+ * For BL32, get the chip id info directly by reading corresponding
+ * registers instead of making pm call. This has limitation
+ * that these registers should be configured to have access
+ * from APU which is default case.
+ */
+ chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
+ chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
+#else
+ if (pm_get_chipid(chipid) != PM_RET_SUCCESS)
return "UNKN";
+#endif
id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
ZYNQMP_CSU_IDCODE_SVD_MASK);
--
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