diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index 91e15247c1e476b5cbf709a7807bf10b504f3129..32e7a532ab4df539c503c2644313e5fc313ca79b 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -7,7 +7,6 @@
#ifndef __MCE_PRIVATE_H__
#define __MCE_PRIVATE_H__
-#include <mmio.h>
#include <tegra_def.h>
/*******************************************************************************
@@ -27,25 +26,11 @@
#define CSTATE_WAKE_MASK_SHIFT 32U
#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU
-/*******************************************************************************
- * Auto-CC3 control macros
- ******************************************************************************/
-#define MCE_AUTO_CC3_FREQ_MASK 0xFFU
-#define MCE_AUTO_CC3_FREQ_SHIFT 0U
-#define MCE_AUTO_CC3_ENABLE_BIT (1U << 31)
-
/*******************************************************************************
* Core ID mask (bits 3:0 in the online request)
******************************************************************************/
#define MCE_CORE_ID_MASK 0xFU
-/*******************************************************************************
- * Cache control macros
- ******************************************************************************/
-#define CACHE_CLEAN_SET (1U << 0)
-#define CACHE_CLEAN_INVAL_SET (1U << 1)
-#define CACHE_CLEAN_INVAL_TR_SET (1U << 2)
-
/*******************************************************************************
* C-state statistics macros
******************************************************************************/
@@ -60,16 +45,11 @@ int32_t nvg_disable_power_saver_modes(void);
void nvg_set_wake_time(uint32_t wake_time);
void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask);
-int32_t nvg_update_crossover_time(uint32_t type, uint32_t time);
int32_t nvg_set_cstate_stat_query_value(uint64_t data);
uint64_t nvg_get_cstate_stat_query_value(void);
int32_t nvg_is_sc7_allowed(void);
int32_t nvg_online_core(uint32_t core);
-int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable);
int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
-int32_t nvg_roc_flush_cache(void);
-int32_t nvg_roc_clean_cache(void);
-int32_t nvg_roc_clean_cache_trbits(void);
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
void nvg_set_request_data(uint64_t req, uint64_t data);
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
index 08f5db82ce10e937f95b433ffd10af4c379310bb..f6edd58adb4293864d3d9882358942dae976aa08 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
@@ -14,7 +14,6 @@
#include <denver.h>
#include <mce.h>
#include <mce_private.h>
-#include <mmio.h>
#include <platform_def.h>
#include <stdbool.h>
#include <string.h>
@@ -41,13 +40,7 @@ static bool mce_firmware_not_supported(void)
int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
uint64_t arg2)
{
- uint64_t ret64 = 0, arg3, arg4, arg5;
int32_t ret = 0;
- cpu_context_t *ctx = cm_get_context(NON_SECURE);
- gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
-
- assert(ctx != NULL);
- assert(gp_regs != NULL);
switch (cmd) {
case (uint64_t)MCE_CMD_ENTER_CSTATE:
@@ -58,65 +51,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
break;
- case (uint64_t)MCE_CMD_UPDATE_CSTATE_INFO:
- /*
- * get the parameters required for the update cstate info
- * command
- */
- arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4);
- arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5);
- arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6);
-
- /* arg0 cluster
- * arg1 ccplex
- * arg2 system
- * arg3 sys_state_force => T19x not support
- * arg4 wake_mask
- * arg5 update_wake_mask
- */
- nvg_update_cstate_info((uint32_t)arg0, (uint32_t)arg1,
- (uint32_t)arg2, (uint32_t)arg4, (uint8_t)arg5);
-
- write_ctx_reg(gp_regs, CTX_GPREG_X4, arg3);
- write_ctx_reg(gp_regs, CTX_GPREG_X5, arg4);
- write_ctx_reg(gp_regs, CTX_GPREG_X6, arg5);
-
- break;
-
- case (uint64_t)MCE_CMD_UPDATE_CROSSOVER_TIME:
- ret = nvg_update_crossover_time((uint32_t)arg0, (uint32_t)arg1);
- if (ret < 0) {
- ERROR("%s: update_crossover_time failed(%d)\n",
- __func__, ret);
- }
-
- break;
-
- case (uint64_t)MCE_CMD_READ_CSTATE_STATS:
- ret64 = nvg_get_cstate_stat_query_value();
-
- /* update context to return cstate stats value */
- write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64);
- write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64);
-
- break;
-
- case (uint64_t)MCE_CMD_WRITE_CSTATE_STATS:
- ret = nvg_set_cstate_stat_query_value(arg0);
-
- break;
-
case (uint64_t)MCE_CMD_IS_SC7_ALLOWED:
ret = nvg_is_sc7_allowed();
if (ret < 0) {
ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret);
- break;
}
- /* update context to return SC7 status value */
- write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)ret);
- write_ctx_reg(gp_regs, CTX_GPREG_X3, (uint64_t)ret);
-
break;
case (uint64_t)MCE_CMD_ONLINE_CORE:
@@ -127,55 +67,9 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
break;
- case (uint64_t)MCE_CMD_CC3_CTRL:
- ret = nvg_cc3_ctrl((uint32_t)arg0, (uint8_t)arg2);
- if (ret < 0) {
- ERROR("%s: cc3_ctrl failed(%d)\n", __func__, ret);
- }
-
- break;
-
- case (uint64_t)MCE_CMD_READ_VERSIONS:
- /* get the MCE firmware version */
- ret64 = nvg_get_version();
-
- /*
- * version = minor(63:32) | major(31:0). Update context
- * to return major and minor version number.
- */
- write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64 & 0xFFFFULL));
- write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64 >> 32U));
-
- break;
-
- case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
- ret = nvg_roc_clean_cache_trbits();
- if (ret < 0) {
- ERROR("%s: flush cache_trbits failed(%d)\n", __func__,
- ret);
- }
-
- break;
-
- case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE:
- ret = nvg_roc_flush_cache();
- if (ret < 0) {
- ERROR("%s: flush cache failed(%d)\n", __func__, ret);
- }
-
- break;
-
- case (uint64_t)MCE_CMD_ROC_CLEAN_CACHE:
- ret = nvg_roc_clean_cache();
- if (ret < 0) {
- ERROR("%s: clean cache failed(%d)\n", __func__, ret);
- }
-
- break;
-
default:
ERROR("unknown MCE command (%llu)\n", cmd);
- ret = EINVAL;
+ ret = -EINVAL;
break;
}
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index d608bfa4dad88f2697921d40046ef085f4be16e1..498415a29e079837a3287c9f7cd89ab6a35b9d01 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -138,82 +138,6 @@ void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
}
-/*
- * Indices gives MTS the crossover point in TSC ticks for when it becomes
- * no longer viable to enter the named state
- *
- * Type 5 : NVGDATA[0:31]: C6 Lower bound
- * Type 6 : NVGDATA[0:31]: CC6 Lower bound
- * Type 8 : NVGDATA[0:31]: CG7 Lower bound
- */
-int32_t nvg_update_crossover_time(uint32_t type, uint32_t time)
-{
- int32_t ret = 0;
-
- switch (type) {
- case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND:
- nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND,
- (uint64_t)time);
- break;
-
- case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND:
- nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND,
- (uint64_t)time);
- break;
-
- case (uint32_t)TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND:
- nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND,
- (uint64_t)time);
- break;
-
- default:
- ERROR("%s: unknown crossover type (%d)\n", __func__, type);
- ret = EINVAL;
- break;
- }
-
- return ret;
-}
-
-/*
- * These NVG calls allow ARM SW to access CSTATE statistical information
- *
- * NVGDATA[0:3]: SW(RW) Core/cluster/cg id
- * NVGDATA[16:31]: SW(RW) Stat id
- */
-int32_t nvg_set_cstate_stat_query_value(uint64_t data)
-{
- int32_t ret = 0;
-
- /* sanity check stat id and core id*/
- if ((data >> MCE_STAT_ID_SHIFT) >
- (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) {
- ERROR("%s: unknown stat id (%d)\n", __func__,
- (uint32_t)(data >> MCE_STAT_ID_SHIFT));
- ret = EINVAL;
- } else if ((data & MCE_CORE_ID_MASK) > (uint64_t)PLATFORM_CORE_COUNT) {
- ERROR("%s: unknown core id (%d)\n", __func__,
- (uint32_t)(data & MCE_CORE_ID_MASK));
- ret = EINVAL;
- } else {
- nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data);
- }
-
- return ret;
-}
-
-/*
- * The read-only value associated with the CSTATE_STAT_QUERY_REQUEST
- *
- * NVGDATA[0:63]: SW(R) Stat count
- */
-uint64_t nvg_get_cstate_stat_query_value(void)
-{
- nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE);
-
- return (uint64_t)nvg_get_result();
-}
-
/*
* Return a non-zero value if the CCPLEX is able to enter SC7
*
@@ -251,35 +175,6 @@ int32_t nvg_online_core(uint32_t core)
return ret;
}
-/*
- * Enables and controls the voltage/frequency hint for CC3. CC3 is disabled
- * by default.
- *
- * NVGDATA[7:0] SW(RW) frequency request
- * NVGDATA[31:31] SW(RW) enable bit
- */
-int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable)
-{
- uint64_t val = 0;
-
- /*
- * If the enable bit is cleared, Auto-CC3 will be disabled by setting
- * the SW visible frequency request registers for all non
- * floorswept cores valid independent of StandbyWFI and disabling
- * the IDLE frequency request register. If set, Auto-CC3
- * will be enabled by setting the ARM SW visible frequency
- * request registers for all non floorswept cores to be enabled by
- * StandbyWFI or the equivalent signal, and always keeping the IDLE
- * frequency request register enabled.
- */
- if (enable != 0U) {
- val = ((uint64_t)freq & MCE_AUTO_CC3_FREQ_MASK) | MCE_AUTO_CC3_ENABLE_BIT;
- }
- nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, val);
-
- return 0;
-}
-
/*
* MC GSC (General Security Carveout) register values are expected to be
* changed by TrustZone ARM code after boot.
diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
index 38802845d2c0bf62454883df1adf88b4c3d5b81c..04602f046a38fcc66e030eca774d679b638d8479 100644
--- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
@@ -20,36 +20,10 @@
extern bool tegra_fake_system_suspend;
-/*******************************************************************************
- * Offset to read the ref_clk counter value
- ******************************************************************************/
-#define REF_CLK_OFFSET 4ULL
-
/*******************************************************************************
* Tegra186 SiP SMCs
******************************************************************************/
-#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01
-#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02
#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03
-#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00
-#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01
-#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02
-#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03
-#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04
-#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05
-#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06
-#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07
-#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08
-#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09
-#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A
-#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B
-#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C
-#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D
-#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E
-#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F
-#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10
-#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11
-#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12
/*******************************************************************************
* This function is responsible for handling all T186 SiP calls
@@ -63,88 +37,26 @@ int32_t plat_sip_handler(uint32_t smc_fid,
void *handle,
uint64_t flags)
{
- int32_t mce_ret, ret = -ENOTSUP;
- uint32_t local_smc_fid = smc_fid;
- uint64_t local_x1 = x1;
+ int32_t ret = -ENOTSUP;
+ (void)x1;
(void)x4;
(void)cookie;
(void)flags;
- /*
- * Convert SMC FID to SMC64 until the linux driver uses
- * SMC64 encoding.
- */
- local_smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
-
- switch (local_smc_fid) {
-
- /*
- * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
- * 0x82FFFFFF SiP SMC space
- */
- case TEGRA_SIP_MCE_CMD_ENTER_CSTATE:
- case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO:
- case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME:
- case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS:
- case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS:
- case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED:
- case TEGRA_SIP_MCE_CMD_CC3_CTRL:
- case TEGRA_SIP_MCE_CMD_ECHO_DATA:
- case TEGRA_SIP_MCE_CMD_READ_VERSIONS:
- case TEGRA_SIP_MCE_CMD_ENUM_FEATURES:
- case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
- case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA:
- case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA:
- case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE:
- case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE:
- case TEGRA_SIP_MCE_CMD_ENABLE_LATIC:
- case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ:
- case TEGRA_SIP_MCE_CMD_MISC_CCPLEX:
-
- /* clean up the high bits */
- local_smc_fid &= MCE_CMD_MASK;
-
- /* execute the command and store the result */
- mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
- write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, (uint64_t)mce_ret);
-
- ret = 0;
- break;
-
- case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE:
-
- /* clean up the high bits */
- local_x1 = (uint32_t)x1;
- (void)local_x1;
-
+ if (smc_fid == TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND) {
/*
- * SC8 is a special Tegra186 system state where the CPUs and
- * DRAM are powered down but the other subsystem is still
- * alive.
- */
-
- ret = 0;
- break;
-
- case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND:
- /*
- * System suspend mode is set if the platform ATF is running is
- * VDK and there is a debug SIP call. This mode ensures that the
- * debug path is excercied, instead of regular code path to suit
- * the pre-silicon platform needs. These include replacing the
- * the call to WFI with calls to system suspend exit procedures.
+ * System suspend mode is set if the platform ATF is
+ * running on VDK and there is a debug SIP call. This mode
+ * ensures that the debug path is exercised, instead of
+ * regular code path to suit the pre-silicon platform needs.
+ * This includes replacing the call to WFI, with calls to
+ * system suspend exit procedures.
*/
if (tegra_platform_is_virt_dev_kit()) {
-
tegra_fake_system_suspend = true;
ret = 0;
}
-
- break;
-
- default:
- break;
}
return ret;