Merge pull request #1914 from marex/arm/master/d3draak-v2.0.1

Arm/master/d3draak v2.0.1

plat/renesas/rcar/bl2_secure_setting.c

@@ -52,7 +52,7 @@ static const struct {
 	    /*        1: Reserved[R-Car E3]                                 */
 	    /* Bit10: SCEG Secure Core slave ports                          */
 	    /*        0: registers accessed from secure resource only       */
-#if RCAR_LSI == RCAR_E3
+#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
 	{
 	SEC_SEL6, 0xFFFFFBFFU},
 #else

plat/renesas/rcar/bl31_plat_setup.c

@@ -85,10 +85,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 	NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
 
+#if RCAR_LSI != RCAR_D3
 	if (RCAR_CLUSTER_A53A57 == rcar_pwrc_get_cluster()) {
 		plat_cci_init();
 		plat_cci_enable();
 	}
+#endif
 }
 
 void bl31_plat_arch_setup(void)

plat/renesas/rcar/include/platform_def.h

@@ -103,14 +103,14 @@
 /* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
  * size plus a little space for growth. */
 #define RCAR_SYSRAM_BASE		U(0xE6300000)
-#if RCAR_LSI == RCAR_E3
+#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
 #define BL2_LIMIT			U(0xE6320000)
 #else
 #define BL2_LIMIT			U(0xE6360000)
 #endif
 
 #define BL2_BASE			U(0xE6304000)
-#if RCAR_LSI == RCAR_E3
+#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
 #define BL2_IMAGE_LIMIT			U(0xE6318000)
 #else
 #define BL2_IMAGE_LIMIT			U(0xE632E800)

plat/renesas/rcar/include/rcar_def.h

@@ -153,6 +153,7 @@
 #define RCAR_PRODUCT_M3			U(0x00005200)
 #define RCAR_PRODUCT_M3N		U(0x00005500)
 #define RCAR_PRODUCT_E3			U(0x00005700)
+#define RCAR_PRODUCT_D3			U(0x00005800)
 #define RCAR_CUT_VER10			U(0x00000000)
 #define RCAR_CUT_VER11			U(0x00000001)	/* H3/M3N/E3 Ver.1.1 */
 #define RCAR_M3_CUT_VER11		U(0x00000010)	/* M3 Ver.1.1/Ver.1.2 */
@@ -205,6 +206,7 @@
 #define	EXTAL_MD14_MD13_TYPE_3		U(16666600)	/* MD14=1 MD13=1 */
 #define	EXTAL_SALVATOR_XS		U(8320000)	/* Salvator-XS */
 #define EXTAL_EBISU			U(24000000)	/* Ebisu */
+#define EXTAL_DRAAK			U(24000000)	/* Draak */
 /* CPG write protect registers 	*/
 #define	CPGWPR_PASSWORD			(0x5A5AFFFFU)
 #define	CPGWPCR_PASSWORD		(0xA5A50000U)

plat/renesas/rcar/plat_pm.c

@@ -92,18 +92,22 @@ static void rcar_pwr_domain_on_finish(const psci_power_state_t *target_state)
 
 static void rcar_pwr_domain_off(const psci_power_state_t *target_state)
 {
+#if RCAR_LSI != RCAR_D3
 	uint32_t cluster_type = rcar_pwrc_get_cluster();
+#endif
 	unsigned long mpidr = read_mpidr_el1();
 
 	gicv2_cpuif_disable();
 	rcar_pwrc_cpuoff(mpidr);
 
+#if RCAR_LSI != RCAR_D3
 	if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
 		if (cluster_type == RCAR_CLUSTER_A53A57)
 			plat_cci_disable();
 
 		rcar_pwrc_clusteroff(mpidr);
 	}
+#endif
 }
 
 static void rcar_pwr_domain_suspend(const psci_power_state_t *target_state)

plat/renesas/rcar/platform.mk

@@ -29,12 +29,14 @@ RCAR_M3:=1
 RCAR_M3N:=2
 RCAR_E3:=3
 RCAR_H3N:=4
+RCAR_D3:=5
 RCAR_AUTO:=99
 $(eval $(call add_define,RCAR_H3))
 $(eval $(call add_define,RCAR_M3))
 $(eval $(call add_define,RCAR_M3N))
 $(eval $(call add_define,RCAR_E3))
 $(eval $(call add_define,RCAR_H3N))
+$(eval $(call add_define,RCAR_D3))
 $(eval $(call add_define,RCAR_AUTO))
 RCAR_CUT_10:=0
 RCAR_CUT_11:=1
@@ -143,6 +145,21 @@ else
       endif
       $(eval $(call add_define,RCAR_LSI_CUT))
     endif
+  else ifeq (${LSI},D3)
+    RCAR_LSI:=${RCAR_D3}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
   else
     $(error "Error: ${LSI} is not supported.")
   endif

tools/renesas/rcar_layout_create/makefile

@@ -55,6 +55,15 @@ endif
 endif
 $(eval $(call add_define,RCAR_SA6_TYPE))
 
+# Handle different VMA adjustment on D3
+ifeq (${RCAR_LSI},${RCAR_D3})
+RCAR_VMA_ADJUST_ADDR := 0xE6320000
+else
+RCAR_VMA_ADJUST_ADDR := 0xE6312000
+endif
+$(eval $(call add_define,RCAR_VMA_ADJUST_ADDR))
+
+
 ###################################################
 
 #c compiler
@@ -88,8 +97,8 @@ $(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
 	-o $(OUTPUT_FILE_SA0)			\
 	-Map $(FILE_NAME_SA0).map 		\
 
-	$(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3  $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
-	$(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3  $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
+	$(objcopy) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3  $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
+	$(objcopy) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3  $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
 
 $(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
 	$(LD) $(OBJ_FILE_SA6)		 	\
@@ -97,8 +106,8 @@ $(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
 	-o $(OUTPUT_FILE_SA6)			\
 	-Map $(FILE_NAME_SA6).map 		\
 
-	$(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3  $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
-	$(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3  $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
+	$(objcopy) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3  $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
+	$(objcopy) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3  $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
 
 ###################################################
 # Compile

tools/renesas/rcar_layout_create/sa0.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#define RCAR_SA0_SIZE_SMALL	(0)	/* for E3 */
+#define RCAR_SA0_SIZE_SMALL	(0)	/* for E3/D3 */
 #define RCAR_SA0_SIZE_NORMAL	(1)	/* for H3/M3/M3N */
 
 #define BL2_ADDRESS	(0xE6304000)	/* BL2 start address */