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adam.huang
Arm Trusted Firmware
Commits
0a4bf763
Unverified
Commit
0a4bf763
authored
Apr 02, 2019
by
Antonio Niño Díaz
Committed by
GitHub
Apr 02, 2019
Browse files
Merge pull request #1914 from marex/arm/master/d3draak-v2.0.1
Arm/master/d3draak v2.0.1
parents
18ff0b61
15652ec3
Changes
28
Expand all
Show whitespace changes
Inline
Side-by-side
drivers/renesas/rcar/board/board.c
View file @
0a4bf763
...
...
@@ -14,7 +14,9 @@
#include "board.h"
#ifndef BOARD_DEFAULT
#if (RCAR_LSI == RCAR_E3)
#if (RCAR_LSI == RCAR_D3)
#define BOARD_DEFAULT (BOARD_DRAAK << BOARD_CODE_SHIFT)
#elif (RCAR_LSI == RCAR_E3)
#define BOARD_DEFAULT (BOARD_EBISU << BOARD_CODE_SHIFT)
#else
#define BOARD_DEFAULT (BOARD_SALVATOR_X << BOARD_CODE_SHIFT)
...
...
@@ -32,6 +34,7 @@
#define SK_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define EB4_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define EB_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define DR_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define KK_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
const
char
*
g_board_tbl
[]
=
{
...
...
@@ -42,6 +45,7 @@ const char *g_board_tbl[] = {
[
BOARD_EBISU_4D
]
=
"Ebisu-4D"
,
[
BOARD_KRIEK
]
=
"Kriek"
,
[
BOARD_EBISU
]
=
"Ebisu"
,
[
BOARD_DRAAK
]
=
"Draak"
,
[
BOARD_UNKNOWN
]
=
"unknown"
};
...
...
@@ -55,6 +59,7 @@ int32_t rcar_get_board_type(uint32_t *type, uint32_t *rev)
[
BOARD_SALVATOR_X
]
=
SX_ID
,
[
BOARD_EBISU_4D
]
=
EB4_ID
,
[
BOARD_EBISU
]
=
EB_ID
,
[
BOARD_DRAAK
]
=
DR_ID
,
[
BOARD_KRIEK
]
=
KK_ID
,
};
static
uint8_t
board_id
=
BOARD_ID_UNKNOWN
;
...
...
drivers/renesas/rcar/board/board.h
View file @
0a4bf763
...
...
@@ -15,7 +15,8 @@
#define BOARD_EBISU (0x08)
#define BOARD_STARTER_KIT_PRE (0x0B)
#define BOARD_EBISU_4D (0x0DU)
#define BOARD_UNKNOWN (BOARD_EBISU_4D + 1U)
#define BOARD_DRAAK (0x0EU)
#define BOARD_UNKNOWN (BOARD_DRAAK + 1U)
#define BOARD_REV_UNKNOWN (0xFF)
...
...
drivers/renesas/rcar/pwrc/pwrc.c
View file @
0a4bf763
...
...
@@ -737,6 +737,12 @@ uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)
return
c
;
}
#if RCAR_LSI == RCAR_D3
uint32_t
rcar_pwrc_get_cpu_num
(
uint32_t
c
)
{
return
1
;
}
#else
uint32_t
rcar_pwrc_get_cpu_num
(
uint32_t
c
)
{
uint32_t
reg
=
mmio_read_32
(
RCAR_PRR
);
...
...
@@ -768,6 +774,7 @@ count_ca57:
done:
return
count
;
}
#endif
int32_t
rcar_pwrc_cpu_on_check
(
uint64_t
mpidr
)
{
...
...
drivers/renesas/rcar/rom/rom_api.c
View file @
0a4bf763
...
...
@@ -19,7 +19,7 @@ typedef uint32_t(*rom_get_lcs_api_f) (uint32_t *lcs);
#define OLD_API_TABLE1 (0U)
/* H3 Ver.1.0/Ver.1.1 */
#define OLD_API_TABLE2 (1U)
/* H3 Ver.2.0 */
#define OLD_API_TABLE3 (2U)
/* M3 Ver.1.0 */
#define NEW_API_TABLE (3U)
/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
#define NEW_API_TABLE (3U)
/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3
, D3
*/
#define API_TABLE_MAX (4U)
/* table max */
/* Later than H3 Ver.2.0 */
...
...
@@ -66,7 +66,7 @@ uint32_t rcar_rom_secure_boot_api(uint32_t *key, uint32_t *cert,
0xEB10DD64U
,
/* H3 Ver.1.0/Ver.1.1 */
0xEB116ED4U
,
/* H3 Ver.2.0 */
0xEB1102FCU
,
/* M3 Ver.1.0 */
0xEB100180U
/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
0xEB100180U
/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3
, D3
*/
};
rom_secure_boot_api_f
secure_boot
;
uint32_t
index
;
...
...
@@ -83,7 +83,7 @@ uint32_t rcar_rom_get_lcs(uint32_t *lcs)
0xEB10DFE0U
,
/* H3 Ver.1.0/Ver.1.1 */
0xEB117150U
,
/* H3 Ver.2.0 */
0xEB110578U
,
/* M3 Ver.1.0 */
0xEB10018CU
/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
0xEB10018CU
/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3
, D3
*/
};
rom_get_lcs_api_f
get_lcs
;
uint32_t
index
;
...
...
drivers/renesas/rcar/scif/scif.S
View file @
0a4bf763
...
...
@@ -17,6 +17,7 @@
#define PRR_CUT_MASK (0x000000FF)
#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
#define PRR_PRODUCT_E3 (0x00005700)
#define PRR_PRODUCT_D3 (0x00005800)
/*
module
stop
*/
#define CPG_BASE (0xE6150000)
...
...
@@ -60,6 +61,7 @@
SCSMR_STOP_1
+
\
SCSMR_CKS_DIV1
)
#define SCBRR_115200BPS (17)
#define SCBRR_115200BPSON (16)
#define SCBRR_115200BPS_E3_SSCG (15)
#define SCBRR_230400BPS (8)
...
...
@@ -192,22 +194,29 @@ func console_core_init
cmp
w1
,
w2
beq
3
f
and
w1
,
w1
,
#
PRR_PRODUCT_MASK
mov
w2
,
#
PRR_PRODUCT_D3
cmp
w1
,
w2
beq
4
f
and
w1
,
w1
,
#
PRR_PRODUCT_MASK
mov
w2
,
#
PRR_PRODUCT_E3
cmp
w1
,
w2
bne
4
f
bne
5
f
ldr
x1
,
=
RST_MODEMR
ldr
w1
,
[
x1
]
and
w1
,
w1
,
#
MODEMR_MD12
mov
w2
,
#
MODEMR_MD12
cmp
w1
,
w2
bne
4
f
bne
5
f
mov
w1
,
#
SCBRR_115200BPS_E3_SSCG
b
2
f
4
:
5
:
mov
w1
,
#
SCBRR_115200BPS
b
2
f
4
:
mov
w1
,
#
SCBRR_115200BPSON
b
2
f
3
:
mov
w1
,
#
SCBRR_230400BPS
2
:
...
...
drivers/renesas/rcar/watchdog/swdt.c
View file @
0a4bf763
...
...
@@ -49,7 +49,11 @@ extern void gicd_set_icenabler(uintptr_t base, unsigned int id);
#define WTCSRA_INIT_DATA (WTCSRA_UPPER_BYTE + 0x0FU)
#define WTCSRB_INIT_DATA (WTCSRB_UPPER_BYTE + 0x21U)
#if RCAR_LSI == RCAR_D3
#define WTCNT_COUNT_8p13k (0x10000U - 40760U)
#else
#define WTCNT_COUNT_8p13k (0x10000U - 40687U)
#endif
#define WTCNT_COUNT_8p13k_H3VER10 (0x10000U - 20343U)
#define WTCNT_COUNT_8p22k (0x10000U - 41115U)
#define WTCNT_COUNT_7p81k (0x10000U - 39062U)
...
...
drivers/staging/renesas/rcar/ddr/ddr.mk
View file @
0a4bf763
...
...
@@ -6,8 +6,10 @@
ifeq
(${RCAR_LSI},${RCAR_E3})
include
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
BL2_SOURCES
+=
drivers/staging/renesas/rcar/ddr/dram_sub_func.c
else
ifeq
(${RCAR_LSI},${RCAR_D3})
include
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
else
include
drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
BL2_SOURCES
+=
drivers/staging/renesas/rcar/ddr/dram_sub_func.c
endif
BL2_SOURCES
+=
drivers/staging/renesas/rcar/ddr/dram_sub_func.c
drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h
0 → 100644
View file @
0a4bf763
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Revision history
*
* rev.0.01 2017/05/22 New
*/
#ifndef BOOT_INIT_DRAM_REGDEF_D3_H_
#define BOOT_INIT_DRAM_REGDEF_D3_H_
#ifdef __cplusplus
extern
"C"
{
#endif
/* __cplusplus */
#define BIT0 0x00000001U
#define BIT30 0x40000000U
/* DBSC registers */
#define DBSC_D3_DBSYSCONF1 0xE6790004U
#define DBSC_D3_DBPHYCONF0 0xE6790010U
#define DBSC_D3_DBKIND 0xE6790020U
#define DBSC_D3_DBMEMCONF00 0xE6790030U
#define DBSC_D3_DBMEMCONF01 0xE6790034U
#define DBSC_D3_DBMEMCONF02 0xE6790038U
#define DBSC_D3_DBMEMCONF03 0xE679003CU
#define DBSC_D3_DBMEMCONF10 0xE6790040U
#define DBSC_D3_DBMEMCONF11 0xE6790044U
#define DBSC_D3_DBMEMCONF12 0xE6790048U
#define DBSC_D3_DBMEMCONF13 0xE679004CU
#define DBSC_D3_DBMEMCONF20 0xE6790050U
#define DBSC_D3_DBMEMCONF21 0xE6790054U
#define DBSC_D3_DBMEMCONF22 0xE6790058U
#define DBSC_D3_DBMEMCONF23 0xE679005CU
#define DBSC_D3_DBMEMCONF30 0xE6790060U
#define DBSC_D3_DBMEMCONF31 0xE6790064U
#define DBSC_D3_DBMEMCONF32 0xE6790068U
#define DBSC_D3_DBMEMCONF33 0xE679006CU
#define DBSC_D3_DBSYSCNT0 0xE6790100U
#define DBSC_D3_DBSVCR1 0xE6790104U
#define DBSC_D3_DBSTATE0 0xE6790108U
#define DBSC_D3_DBSTATE1 0xE679010CU
#define DBSC_D3_DBINTEN 0xE6790180U
#define DBSC_D3_DBINTSTAT0 0xE6790184U
#define DBSC_D3_DBACEN 0xE6790200U
#define DBSC_D3_DBRFEN 0xE6790204U
#define DBSC_D3_DBCMD 0xE6790208U
#define DBSC_D3_DBWAIT 0xE6790210U
#define DBSC_D3_DBSYSCTRL0 0xE6790280U
#define DBSC_D3_DBTR0 0xE6790300U
#define DBSC_D3_DBTR1 0xE6790304U
#define DBSC_D3_DBTR2 0xE6790308U
#define DBSC_D3_DBTR3 0xE679030CU
#define DBSC_D3_DBTR4 0xE6790310U
#define DBSC_D3_DBTR5 0xE6790314U
#define DBSC_D3_DBTR6 0xE6790318U
#define DBSC_D3_DBTR7 0xE679031CU
#define DBSC_D3_DBTR8 0xE6790320U
#define DBSC_D3_DBTR9 0xE6790324U
#define DBSC_D3_DBTR10 0xE6790328U
#define DBSC_D3_DBTR11 0xE679032CU
#define DBSC_D3_DBTR12 0xE6790330U
#define DBSC_D3_DBTR13 0xE6790334U
#define DBSC_D3_DBTR14 0xE6790338U
#define DBSC_D3_DBTR15 0xE679033CU
#define DBSC_D3_DBTR16 0xE6790340U
#define DBSC_D3_DBTR17 0xE6790344U
#define DBSC_D3_DBTR18 0xE6790348U
#define DBSC_D3_DBTR19 0xE679034CU
#define DBSC_D3_DBTR20 0xE6790350U
#define DBSC_D3_DBTR21 0xE6790354U
#define DBSC_D3_DBTR22 0xE6790358U
#define DBSC_D3_DBTR24 0xE6790360U
#define DBSC_D3_DBTR25 0xE6790364U
#define DBSC_D3_DBBL 0xE6790400U
#define DBSC_D3_DBRFCNF1 0xE6790414U
#define DBSC_D3_DBRFCNF2 0xE6790418U
#define DBSC_D3_DBCALCNF 0xE6790424U
#define DBSC_D3_DBRNK2 0xE6790438U
#define DBSC_D3_DBRNK3 0xE679043CU
#define DBSC_D3_DBRNK4 0xE6790440U
#define DBSC_D3_DBRNK5 0xE6790444U
#define DBSC_D3_DBPDNCNF 0xE6790450U
#define DBSC_D3_DBODT0 0xE6790460U
#define DBSC_D3_DBODT1 0xE6790464U
#define DBSC_D3_DBODT2 0xE6790468U
#define DBSC_D3_DBODT3 0xE679046CU
#define DBSC_D3_DBADJ0 0xE6790500U
#define DBSC_D3_DBDBICNT 0xE6790518U
#define DBSC_D3_DBDFICUPDCNF 0xE679052CU
#define DBSC_D3_DBDFICNT0 0xE6790604U
#define DBSC_D3_DBPDLK0 0xE6790620U
#define DBSC_D3_DBPDRGA0 0xE6790624U
#define DBSC_D3_DBPDRGD0 0xE6790628U
#define DBSC_D3_DBPDSTAT00 0xE6790630U
#define DBSC_D3_DBDFISTAT1 0xE6790640U
#define DBSC_D3_DBDFICNT1 0xE6790644U
#define DBSC_D3_DBPDLK1 0xE6790660U
#define DBSC_D3_DBPDRGA1 0xE6790664U
#define DBSC_D3_DBPDRGD1 0xE6790668U
#define DBSC_D3_DBDFICNT2 0xE6790684U
#define DBSC_D3_DBPDLK2 0xE67906A0U
#define DBSC_D3_DBPDRGA2 0xE67906A4U
#define DBSC_D3_DBPDRGD2 0xE67906A8U
#define DBSC_D3_DBPDSTAT20 0xE67906B0U
#define DBSC_D3_DBDFISTAT3 0xE67906C0U
#define DBSC_D3_DBDFICNT3 0xE67906C4U
#define DBSC_D3_DBPDLK3 0xE67906E0U
#define DBSC_D3_DBPDRGA3 0xE67906E4U
#define DBSC_D3_DBPDRGD3 0xE67906E8U
#define DBSC_D3_DBBUS0CNF1 0xE6790804U
#define DBSC_D3_DBCAM0CNF1 0xE6790904U
#define DBSC_D3_DBCAM0CNF2 0xE6790908U
#define DBSC_D3_DBCAM0STAT0 0xE6790980U
#define DBSC_D3_DBCAM1STAT0 0xE6790990U
#define DBSC_D3_DBBCAMDIS 0xE67909FCU
#define DBSC_D3_DBSCHCNT0 0xE6791000U
#define DBSC_D3_DBSCHSZ0 0xE6791010U
#define DBSC_D3_DBSCHRW0 0xE6791020U
#define DBSC_D3_DBSCHRW1 0xE6791024U
#define DBSC_D3_DBSCHQOS00 0xE6791030U
#define DBSC_D3_DBSCHQOS01 0xE6791034U
#define DBSC_D3_DBSCHQOS02 0xE6791038U
#define DBSC_D3_DBSCHQOS03 0xE679103CU
#define DBSC_D3_DBSCHQOS10 0xE6791040U
#define DBSC_D3_DBSCHQOS11 0xE6791044U
#define DBSC_D3_DBSCHQOS12 0xE6791048U
#define DBSC_D3_DBSCHQOS13 0xE679104CU
#define DBSC_D3_DBSCHQOS20 0xE6791050U
#define DBSC_D3_DBSCHQOS21 0xE6791054U
#define DBSC_D3_DBSCHQOS22 0xE6791058U
#define DBSC_D3_DBSCHQOS23 0xE679105CU
#define DBSC_D3_DBSCHQOS30 0xE6791060U
#define DBSC_D3_DBSCHQOS31 0xE6791064U
#define DBSC_D3_DBSCHQOS32 0xE6791068U
#define DBSC_D3_DBSCHQOS33 0xE679106CU
#define DBSC_D3_DBSCHQOS40 0xE6791070U
#define DBSC_D3_DBSCHQOS41 0xE6791074U
#define DBSC_D3_DBSCHQOS42 0xE6791078U
#define DBSC_D3_DBSCHQOS43 0xE679107CU
#define DBSC_D3_DBSCHQOS50 0xE6791080U
#define DBSC_D3_DBSCHQOS51 0xE6791084U
#define DBSC_D3_DBSCHQOS52 0xE6791088U
#define DBSC_D3_DBSCHQOS53 0xE679108CU
#define DBSC_D3_DBSCHQOS60 0xE6791090U
#define DBSC_D3_DBSCHQOS61 0xE6791094U
#define DBSC_D3_DBSCHQOS62 0xE6791098U
#define DBSC_D3_DBSCHQOS63 0xE679109CU
#define DBSC_D3_DBSCHQOS70 0xE67910A0U
#define DBSC_D3_DBSCHQOS71 0xE67910A4U
#define DBSC_D3_DBSCHQOS72 0xE67910A8U
#define DBSC_D3_DBSCHQOS73 0xE67910ACU
#define DBSC_D3_DBSCHQOS80 0xE67910B0U
#define DBSC_D3_DBSCHQOS81 0xE67910B4U
#define DBSC_D3_DBSCHQOS82 0xE67910B8U
#define DBSC_D3_DBSCHQOS83 0xE67910BCU
#define DBSC_D3_DBSCHQOS90 0xE67910C0U
#define DBSC_D3_DBSCHQOS91 0xE67910C4U
#define DBSC_D3_DBSCHQOS92 0xE67910C8U
#define DBSC_D3_DBSCHQOS93 0xE67910CCU
#define DBSC_D3_DBSCHQOS100 0xE67910D0U
#define DBSC_D3_DBSCHQOS101 0xE67910D4U
#define DBSC_D3_DBSCHQOS102 0xE67910D8U
#define DBSC_D3_DBSCHQOS103 0xE67910DCU
#define DBSC_D3_DBSCHQOS110 0xE67910E0U
#define DBSC_D3_DBSCHQOS111 0xE67910E4U
#define DBSC_D3_DBSCHQOS112 0xE67910E8U
#define DBSC_D3_DBSCHQOS113 0xE67910ECU
#define DBSC_D3_DBSCHQOS120 0xE67910F0U
#define DBSC_D3_DBSCHQOS121 0xE67910F4U
#define DBSC_D3_DBSCHQOS122 0xE67910F8U
#define DBSC_D3_DBSCHQOS123 0xE67910FCU
#define DBSC_D3_DBSCHQOS130 0xE6791100U
#define DBSC_D3_DBSCHQOS131 0xE6791104U
#define DBSC_D3_DBSCHQOS132 0xE6791108U
#define DBSC_D3_DBSCHQOS133 0xE679110CU
#define DBSC_D3_DBSCHQOS140 0xE6791110U
#define DBSC_D3_DBSCHQOS141 0xE6791114U
#define DBSC_D3_DBSCHQOS142 0xE6791118U
#define DBSC_D3_DBSCHQOS143 0xE679111CU
#define DBSC_D3_DBSCHQOS150 0xE6791120U
#define DBSC_D3_DBSCHQOS151 0xE6791124U
#define DBSC_D3_DBSCHQOS152 0xE6791128U
#define DBSC_D3_DBSCHQOS153 0xE679112CU
#define DBSC_D3_SCFCTST0 0xE6791700U
#define DBSC_D3_SCFCTST1 0xE6791708U
#define DBSC_D3_SCFCTST2 0xE679170CU
#define DBSC_D3_DBMRRDR0 0xE6791800U
#define DBSC_D3_DBMRRDR1 0xE6791804U
#define DBSC_D3_DBMRRDR2 0xE6791808U
#define DBSC_D3_DBMRRDR3 0xE679180CU
#define DBSC_D3_DBMRRDR4 0xE6791810U
#define DBSC_D3_DBMRRDR5 0xE6791814U
#define DBSC_D3_DBMRRDR6 0xE6791818U
#define DBSC_D3_DBMRRDR7 0xE679181CU
#ifdef __cplusplus
}
#endif
/* __cplusplus */
#endif
/* BOOT_INIT_DRAM_REGDEF_D3_H_*/
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
View file @
0a4bf763
...
...
@@ -4,4 +4,8 @@
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq
(${RCAR_LSI},${RCAR_E3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
else
BL2_SOURCES
+=
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
endif
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
0 → 100644
View file @
0a4bf763
This diff is collapsed.
Click to expand it.
drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
0 → 100644
View file @
0a4bf763
This diff is collapsed.
Click to expand it.
drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.h
0 → 100644
View file @
0a4bf763
/*
* Copyright (c) 2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PFC_INIT_D3_H__
#define PFC_INIT_D3_H__
void
pfc_init_d3
(
void
);
#endif
/* PFC_INIT_D3_H__ */
drivers/staging/renesas/rcar/pfc/pfc.mk
View file @
0a4bf763
...
...
@@ -28,6 +28,9 @@ else ifdef RCAR_LSI_CUT_COMPAT
ifeq
(${RCAR_LSI},${RCAR_E3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
endif
ifeq
(${RCAR_LSI},${RCAR_D3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
endif
else
ifeq
(${RCAR_LSI},${RCAR_H3})
ifeq
(${LSI_CUT},10)
...
...
@@ -51,6 +54,9 @@ else
ifeq
(${RCAR_LSI},${RCAR_E3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
endif
ifeq
(${RCAR_LSI},${RCAR_D3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
endif
endif
BL2_SOURCES
+=
drivers/staging/renesas/rcar/pfc/pfc_init.c
drivers/staging/renesas/rcar/pfc/pfc_init.c
View file @
0a4bf763
...
...
@@ -28,6 +28,9 @@
#endif
#if RCAR_LSI == RCAR_E3
/* E3 */
#include "E3/pfc_init_e3.h"
#endif
#if RCAR_LSI == RCAR_D3
/* D3 */
#include "D3/pfc_init_d3.h"
#endif
/* Product Register */
...
...
@@ -38,6 +41,7 @@
#define PRR_PRODUCT_M3 (0x00005200U)
/* R-Car M3 */
#define PRR_PRODUCT_M3N (0x00005500U)
/* R-Car M3N */
#define PRR_PRODUCT_E3 (0x00005700U)
/* R-Car E3 */
#define PRR_PRODUCT_D3 (0x00005800U)
/* R-Car D3 */
#define PRR_PRODUCT_10 (0x00U)
#define PRR_PRODUCT_11 (0x01U)
#define PRR_PRODUCT_20 (0x10U)
...
...
@@ -122,6 +126,13 @@ void rcar_pfc_init(void)
PRR_PRODUCT_ERR
(
reg
);
#else
pfc_init_e3
();
#endif
break
;
case
PRR_PRODUCT_D3
:
#if RCAR_LSI != RCAR_D3
PRR_PRODUCT_ERR
(
reg
);
#else
pfc_init_d3
();
#endif
break
;
default:
...
...
@@ -167,6 +178,11 @@ void rcar_pfc_init(void)
PRR_PRODUCT_ERR
(
reg
);
}
pfc_init_e3
();
#elif RCAR_LSI == RCAR_D3
/* D3 */
if
((
PRR_PRODUCT_D3
)
!=
(
reg
&
PRR_PRODUCT_MASK
))
{
PRR_PRODUCT_ERR
(
reg
);
}
pfc_init_d3
();
#else
#error "Don't have PFC initialize routine(unknown)."
#endif
...
...
drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c
0 → 100644
View file @
0a4bf763
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <common/debug.h>
#include "qos_init_d3.h"
#define RCAR_QOS_VERSION "rev.0.05"
#define RCAR_QOS_NONE (3U)
#define RCAR_QOS_TYPE_DEFAULT (0U)
#define RCAR_DRAM_SPLIT_LINEAR (0U)
#define RCAR_DRAM_SPLIT_4CH (1U)
#define RCAR_DRAM_SPLIT_2CH (2U)
#define RCAR_DRAM_SPLIT_AUTO (3U)
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
#define DBSC_BASE (0xE6790000U)
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
#define DBSC_AXARB (DBSC_BASE + 0x0800U)
#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
#define AXI_BASE (0xE6784000U)
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
#define MSTAT_BASE (0xE67E0000U)
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
#define RALLOC_BASE (0xE67F0000U)
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
#define RALLOC_FSS (RALLOC_BASE + 0x0048U)
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
#define RALLOC_EARLYR (RALLOC_BASE + 0x0060U)
#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
#define RALLOC_TICKDUPL (RALLOC_BASE + 0x0088U)
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
static
inline
void
io_write_32
(
uintptr_t
addr
,
uint32_t
value
)
{
*
(
volatile
uint32_t
*
)
addr
=
value
;
}
static
inline
void
io_write_64
(
uintptr_t
addr
,
uint64_t
value
)
{
*
(
volatile
uint64_t
*
)
addr
=
value
;
}
typedef
struct
{
uintptr_t
addr
;
uint64_t
value
;
}
mstat_slot_t
;
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
static
const
mstat_slot_t
mstat_fix
[]
=
{
{
0x0000U
,
0x0000000000000000U
},
{
0x0008U
,
0x0000000000000000U
},
{
0x0010U
,
0x0000000000000000U
},
{
0x0018U
,
0x0000000000000000U
},
{
0x0020U
,
0x0000000000000000U
},
{
0x0028U
,
0x0000000000000000U
},
{
0x0030U
,
0x001004340000FFFFU
},
{
0x0038U
,
0x001004140000FFFFU
},
{
0x0040U
,
0x0000000000000000U
},
{
0x0048U
,
0x0000000000000000U
},
{
0x0050U
,
0x0000000000000000U
},
{
0x0058U
,
0x00140B030000FFFFU
},
{
0x0060U
,
0x001408610000FFFFU
},
{
0x0068U
,
0x0000000000000000U
},
{
0x0070U
,
0x0000000000000000U
},
{
0x0078U
,
0x0000000000000000U
},
{
0x0080U
,
0x0000000000000000U
},
{
0x0088U
,
0x001410620000FFFFU
},
{
0x0090U
,
0x0000000000000000U
},
{
0x0098U
,
0x0000000000000000U
},
{
0x00A0U
,
0x000C041C0000FFFFU
},
{
0x00A8U
,
0x000C04090000FFFFU
},
{
0x00B0U
,
0x000C04110000FFFFU
},
{
0x00B8U
,
0x0000000000000000U
},
{
0x00C0U
,
0x000C041C0000FFFFU
},
{
0x00C8U
,
0x000C04090000FFFFU
},
{
0x00D0U
,
0x000C04110000FFFFU
},
{
0x00D8U
,
0x0000000000000000U
},
{
0x00E0U
,
0x0000000000000000U
},
{
0x00E8U
,
0x0000000000000000U
},
{
0x00F0U
,
0x001018570000FFFFU
},
{
0x00F8U
,
0x0000000000000000U
},
{
0x0100U
,
0x0000000000000000U
},
{
0x0108U
,
0x0000000000000000U
},
{
0x0110U
,
0x001008570000FFFFU
},
{
0x0118U
,
0x0000000000000000U
},
{
0x0120U
,
0x0000000000000000U
},
{
0x0128U
,
0x0000000000000000U
},
{
0x0130U
,
0x0000000000000000U
},
{
0x0138U
,
0x0000000000000000U
},
{
0x0140U
,
0x0000000000000000U
},
{
0x0148U
,
0x0000000000000000U
},
{
0x0150U
,
0x001008520000FFFFU
},
{
0x0158U
,
0x0000000000000000U
},
{
0x0160U
,
0x0000000000000000U
},
{
0x0168U
,
0x0000000000000000U
},
{
0x0170U
,
0x0000000000000000U
},
{
0x0178U
,
0x0000000000000000U
},
{
0x0180U
,
0x0000000000000000U
},
{
0x0188U
,
0x0000000000000000U
},
{
0x0190U
,
0x00100CA30000FFFFU
},
{
0x0198U
,
0x0000000000000000U
},
{
0x01A0U
,
0x0000000000000000U
},
{
0x01A8U
,
0x0000000000000000U
},
{
0x01B0U
,
0x0000000000000000U
},
{
0x01B8U
,
0x0000000000000000U
},
{
0x01C0U
,
0x0000000000000000U
},
{
0x01C8U
,
0x0000000000000000U
},
{
0x01D0U
,
0x0000000000000000U
},
{
0x01D8U
,
0x0000000000000000U
},
{
0x01E0U
,
0x0000000000000000U
},
{
0x01E8U
,
0x000C04020000FFFFU
},
{
0x01F0U
,
0x0000000000000000U
},
{
0x01F8U
,
0x0000000000000000U
},
{
0x0200U
,
0x0000000000000000U
},
{
0x0208U
,
0x000C04090000FFFFU
},
{
0x0210U
,
0x0000000000000000U
},
{
0x0218U
,
0x0000000000000000U
},
{
0x0220U
,
0x0000000000000000U
},
{
0x0228U
,
0x0000000000000000U
},
{
0x0230U
,
0x0000000000000000U
},
{
0x0238U
,
0x0000000000000000U
},
{
0x0240U
,
0x0000000000000000U
},
{
0x0248U
,
0x0000000000000000U
},
{
0x0250U
,
0x0000000000000000U
},
{
0x0258U
,
0x0000000000000000U
},
{
0x0260U
,
0x0000000000000000U
},
{
0x0268U
,
0x001410040000FFFFU
},
{
0x0270U
,
0x001404020000FFFFU
},
{
0x0278U
,
0x0000000000000000U
},
{
0x0280U
,
0x0000000000000000U
},
{
0x0288U
,
0x0000000000000000U
},
{
0x0290U
,
0x001410040000FFFFU
},
{
0x0298U
,
0x001404020000FFFFU
},
{
0x02A0U
,
0x000C04050000FFFFU
},
{
0x02A8U
,
0x000C04050000FFFFU
},
{
0x02B0U
,
0x0000000000000000U
},
{
0x02B8U
,
0x0000000000000000U
},
{
0x02C0U
,
0x0000000000000000U
},
{
0x02C8U
,
0x0000000000000000U
},
{
0x02D0U
,
0x000C04050000FFFFU
},
{
0x02D8U
,
0x000C04050000FFFFU
},
{
0x02E0U
,
0x0000000000000000U
},
{
0x02E8U
,
0x0000000000000000U
},
{
0x02F0U
,
0x0000000000000000U
},
{
0x02F8U
,
0x0000000000000000U
},
{
0x0300U
,
0x0000000000000000U
},
{
0x0308U
,
0x0000000000000000U
},
{
0x0310U
,
0x0000000000000000U
},
{
0x0318U
,
0x0000000000000000U
},
{
0x0320U
,
0x0000000000000000U
},
{
0x0328U
,
0x0000000000000000U
},
{
0x0330U
,
0x0000000000000000U
},
{
0x0338U
,
0x0000000000000000U
},
{
0x0340U
,
0x0000000000000000U
},
{
0x0348U
,
0x0000000000000000U
},
{
0x0350U
,
0x0000000000000000U
},
{
0x0358U
,
0x0000000000000000U
},
{
0x0360U
,
0x0000000000000000U
},
{
0x0368U
,
0x0000000000000000U
},
{
0x0370U
,
0x000C04020000FFFFU
},
{
0x0378U
,
0x000C04020000FFFFU
},
{
0x0380U
,
0x000C04090000FFFFU
},
{
0x0388U
,
0x000C04090000FFFFU
},
{
0x0390U
,
0x0000000000000000U
},
};
static
const
mstat_slot_t
mstat_be
[]
=
{
{
0x0000U
,
0x0000000000000000U
},
{
0x0008U
,
0x0000000000000000U
},
{
0x0010U
,
0x0000000000000000U
},
{
0x0018U
,
0x0000000000000000U
},
{
0x0020U
,
0x0000000000000000U
},
{
0x0028U
,
0x0000000000000000U
},
{
0x0030U
,
0x0000000000000000U
},
{
0x0038U
,
0x0000000000000000U
},
{
0x0040U
,
0x0000000000000000U
},
{
0x0048U
,
0x0000000000000000U
},
{
0x0050U
,
0x0000000000000000U
},
{
0x0058U
,
0x0000000000000000U
},
{
0x0060U
,
0x0000000000000000U
},
{
0x0068U
,
0x0000000000000000U
},
{
0x0070U
,
0x0000000000000000U
},
{
0x0078U
,
0x0000000000000000U
},
{
0x0080U
,
0x0000000000000000U
},
{
0x0088U
,
0x0000000000000000U
},
{
0x0090U
,
0x0000000000000000U
},
{
0x0098U
,
0x0000000000000000U
},
{
0x00A0U
,
0x0000000000000000U
},
{
0x00A8U
,
0x0000000000000000U
},
{
0x00B0U
,
0x0000000000000000U
},
{
0x00B8U
,
0x0000000000000000U
},
{
0x00C0U
,
0x0000000000000000U
},
{
0x00C8U
,
0x0000000000000000U
},
{
0x00D0U
,
0x0000000000000000U
},
{
0x00D8U
,
0x0000000000000000U
},
{
0x00E0U
,
0x0000000000000000U
},
{
0x00E8U
,
0x0000000000000000U
},
{
0x00F0U
,
0x0000000000000000U
},
{
0x00F8U
,
0x0000000000000000U
},
{
0x0100U
,
0x0000000000000000U
},
{
0x0108U
,
0x0000000000000000U
},
{
0x0110U
,
0x0000000000000000U
},
{
0x0118U
,
0x0000000000000000U
},
{
0x0120U
,
0x0000000000000000U
},
{
0x0128U
,
0x0000000000000000U
},
{
0x0130U
,
0x0000000000000000U
},
{
0x0138U
,
0x0000000000000000U
},
{
0x0140U
,
0x0000000000000000U
},
{
0x0148U
,
0x0000000000000000U
},
{
0x0150U
,
0x0000000000000000U
},
{
0x0158U
,
0x0000000000000000U
},
{
0x0160U
,
0x0000000000000000U
},
{
0x0168U
,
0x0000000000000000U
},
{
0x0170U
,
0x0000000000000000U
},
{
0x0178U
,
0x0000000000000000U
},
{
0x0180U
,
0x0000000000000000U
},
{
0x0188U
,
0x0000000000000000U
},
{
0x0190U
,
0x0000000000000000U
},
{
0x0198U
,
0x0000000000000000U
},
{
0x01A0U
,
0x0000000000000000U
},
{
0x01A8U
,
0x0000000000000000U
},
{
0x01B0U
,
0x0000000000000000U
},
{
0x01B8U
,
0x0000000000000000U
},
{
0x01C0U
,
0x00110090060FA001U
},
{
0x01C8U
,
0x00110090060FA001U
},
{
0x01D0U
,
0x0000000000000000U
},
{
0x01D8U
,
0x0000000000000000U
},
{
0x01E0U
,
0x0000000000000000U
},
{
0x01E8U
,
0x0000000000000000U
},
{
0x01F0U
,
0x0011001006004401U
},
{
0x01F8U
,
0x0000000000000000U
},
{
0x0200U
,
0x0000000000000000U
},
{
0x0208U
,
0x0000000000000000U
},
{
0x0210U
,
0x0011001006004401U
},
{
0x0218U
,
0x0011001006009801U
},
{
0x0220U
,
0x0011001006009801U
},
{
0x0228U
,
0x0000000000000000U
},
{
0x0230U
,
0x0011001006009801U
},
{
0x0238U
,
0x0011001006009801U
},
{
0x0240U
,
0x0000000000000000U
},
{
0x0248U
,
0x0000000000000000U
},
{
0x0250U
,
0x0000000000000000U
},
{
0x0258U
,
0x0000000000000000U
},
{
0x0260U
,
0x0000000000000000U
},
{
0x0268U
,
0x0000000000000000U
},
{
0x0270U
,
0x0000000000000000U
},
{
0x0278U
,
0x0000000000000000U
},
{
0x0280U
,
0x0000000000000000U
},
{
0x0288U
,
0x0000000000000000U
},
{
0x0290U
,
0x0000000000000000U
},
{
0x0298U
,
0x0000000000000000U
},
{
0x02A0U
,
0x0000000000000000U
},
{
0x02A8U
,
0x0000000000000000U
},
{
0x02B0U
,
0x0000000000000000U
},
{
0x02B8U
,
0x0011001006003401U
},
{
0x02C0U
,
0x0000000000000000U
},
{
0x02C8U
,
0x0000000000000000U
},
{
0x02D0U
,
0x0000000000000000U
},
{
0x02D8U
,
0x0000000000000000U
},
{
0x02E0U
,
0x0000000000000000U
},
{
0x02E8U
,
0x0011001006003401U
},
{
0x02F0U
,
0x00110090060FA001U
},
{
0x02F8U
,
0x00110090060FA001U
},
{
0x0300U
,
0x0000000000000000U
},
{
0x0308U
,
0x0000000000000000U
},
{
0x0310U
,
0x0000000000000000U
},
{
0x0318U
,
0x0012001006003401U
},
{
0x0320U
,
0x0000000000000000U
},
{
0x0328U
,
0x0000000000000000U
},
{
0x0330U
,
0x0000000000000000U
},
{
0x0338U
,
0x0000000000000000U
},
{
0x0340U
,
0x0000000000000000U
},
{
0x0348U
,
0x0000000000000000U
},
{
0x0350U
,
0x0000000000000000U
},
{
0x0358U
,
0x00120090060FA001U
},
{
0x0360U
,
0x00120090060FA001U
},
{
0x0368U
,
0x0012001006003401U
},
{
0x0370U
,
0x0000000000000000U
},
{
0x0378U
,
0x0000000000000000U
},
{
0x0380U
,
0x0000000000000000U
},
{
0x0388U
,
0x0000000000000000U
},
{
0x0390U
,
0x0012001006003401U
},
};
#endif
static
void
dbsc_setting
(
void
)
{
uint32_t
md
=
0
;
/* BUFCAM settings */
//DBSC_DBCAM0CNF0 not set
io_write_32
(
DBSC_DBCAM0CNF1
,
0x00043218
);
//dbcam0cnf1
io_write_32
(
DBSC_DBCAM0CNF2
,
0x000000F4
);
//dbcam0cnf2
io_write_32
(
DBSC_DBSCHCNT0
,
0x000F0037
);
//dbschcnt0
//DBSC_DBSCHCNT1 not set
io_write_32
(
DBSC_DBSCHSZ0
,
0x00000001
);
//dbschsz0
io_write_32
(
DBSC_DBSCHRW0
,
0x22421111
);
//dbschrw0
md
=
(
*
((
volatile
uint32_t
*
)
RST_MODEMR
)
&
0x00080000
)
>>
19
;
switch
(
md
)
{
case
0x0
:
//MD19=0 : DDR3L-1600, 4GByte(1GByte x4)
/* DDR1600 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
default:
//MD19=1 : DDR3L-1856, 4GByte(1GByte x4)
/* DDR1856 */
io_write_32
(
DBSC_SCFCTST2
,
0x012F1123
);
break
;
}
/* QoS Settings */
io_write_32
(
DBSC_DBSCHQOS_0_0
,
0x00000F00
);
io_write_32
(
DBSC_DBSCHQOS_0_1
,
0x00000B00
);
io_write_32
(
DBSC_DBSCHQOS_0_2
,
0x00000000
);
io_write_32
(
DBSC_DBSCHQOS_0_3
,
0x00000000
);
//DBSC_DBSCHQOS_1_0 not set
//DBSC_DBSCHQOS_1_1 not set
//DBSC_DBSCHQOS_1_2 not set
//DBSC_DBSCHQOS_1_3 not set
//DBSC_DBSCHQOS_2_0 not set
//DBSC_DBSCHQOS_2_1 not set
//DBSC_DBSCHQOS_2_2 not set
//DBSC_DBSCHQOS_2_3 not set
//DBSC_DBSCHQOS_3_0 not set
//DBSC_DBSCHQOS_3_1 not set
//DBSC_DBSCHQOS_3_2 not set
//DBSC_DBSCHQOS_3_3 not set
io_write_32
(
DBSC_DBSCHQOS_4_0
,
0x00000300
);
io_write_32
(
DBSC_DBSCHQOS_4_1
,
0x000002F0
);
io_write_32
(
DBSC_DBSCHQOS_4_2
,
0x00000200
);
io_write_32
(
DBSC_DBSCHQOS_4_3
,
0x00000100
);
//DBSC_DBSCHQOS_5_0 not set
//DBSC_DBSCHQOS_5_1 not set
//DBSC_DBSCHQOS_5_2 not set
//DBSC_DBSCHQOS_5_3 not set
//DBSC_DBSCHQOS_6_0 not set
//DBSC_DBSCHQOS_6_1 not set
//DBSC_DBSCHQOS_6_2 not set
//DBSC_DBSCHQOS_6_3 not set
//DBSC_DBSCHQOS_7_0 not set
//DBSC_DBSCHQOS_7_1 not set
//DBSC_DBSCHQOS_7_2 not set
//DBSC_DBSCHQOS_7_3 not set
//DBSC_DBSCHQOS_8_0 not set
//DBSC_DBSCHQOS_8_1 not set
//DBSC_DBSCHQOS_8_2 not set
//DBSC_DBSCHQOS_8_3 not set
io_write_32
(
DBSC_DBSCHQOS_9_0
,
0x00000300
);
io_write_32
(
DBSC_DBSCHQOS_9_1
,
0x000002F0
);
io_write_32
(
DBSC_DBSCHQOS_9_2
,
0x00000200
);
io_write_32
(
DBSC_DBSCHQOS_9_3
,
0x00000100
);
//DBSC_DBSCHQOS_10_0 not set
//DBSC_DBSCHQOS_10_1 not set
//DBSC_DBSCHQOS_10_2 not set
//DBSC_DBSCHQOS_10_3 not set
//DBSC_DBSCHQOS_11_0 not set
//DBSC_DBSCHQOS_11_1 not set
//DBSC_DBSCHQOS_11_2 not set
//DBSC_DBSCHQOS_11_3 not set
//DBSC_DBSCHQOS_12_0 not set
//DBSC_DBSCHQOS_12_1 not set
//DBSC_DBSCHQOS_12_2 not set
//DBSC_DBSCHQOS_12_3 not set
io_write_32
(
DBSC_DBSCHQOS_13_0
,
0x00000100
);
io_write_32
(
DBSC_DBSCHQOS_13_1
,
0x000000F0
);
io_write_32
(
DBSC_DBSCHQOS_13_2
,
0x000000A0
);
io_write_32
(
DBSC_DBSCHQOS_13_3
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS_14_0
,
0x000000C0
);
io_write_32
(
DBSC_DBSCHQOS_14_1
,
0x000000B0
);
io_write_32
(
DBSC_DBSCHQOS_14_2
,
0x00000080
);
io_write_32
(
DBSC_DBSCHQOS_14_3
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS_15_0
,
0x00000040
);
io_write_32
(
DBSC_DBSCHQOS_15_1
,
0x00000030
);
io_write_32
(
DBSC_DBSCHQOS_15_2
,
0x00000020
);
io_write_32
(
DBSC_DBSCHQOS_15_3
,
0x00000010
);
}
void
qos_init_d3
(
void
)
{
io_write_32
(
DBSC_DBSYSCNT0
,
0x00001234
);
dbsc_setting
();
/* DRAM Split Address mapping */
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
ERROR
(
"DRAM Split 4ch not supported.(D3)"
);
panic
();
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
ERROR
(
"DRAM Split 2ch not supported.(D3)"
);
panic
();
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO
ERROR
(
"DRAM Split Auto not supported.(D3)"
);
panic
();
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_LINEAR
/* NOTICE("BL2: DRAM Split is OFF\n"); */
/* Split setting(DDR 1ch) */
io_write_32
(
AXI_ADSPLCR0
,
0x00000000U
);
io_write_32
(
AXI_ADSPLCR3
,
0x00000000U
);
#else
ERROR
(
"DRAM split is an invalid value.(D3)"
);
panic
();
#endif
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
NOTICE
(
"BL2: QoS is default setting(%s)
\n
"
,
RCAR_QOS_VERSION
);
#endif
/* Resource Alloc setting */
io_write_32
(
RALLOC_RAS
,
0x00000020U
);
io_write_32
(
RALLOC_FIXTH
,
0x000F0005U
);
io_write_32
(
RALLOC_RAEN
,
0x00000001U
);
io_write_32
(
RALLOC_REGGD
,
0x00000000U
);
io_write_64
(
RALLOC_DANN
,
0x0404020002020201U
);
io_write_32
(
RALLOC_DANT
,
0x00100804U
);
io_write_32
(
RALLOC_EC
,
0x00000000U
);
io_write_64
(
RALLOC_EMS
,
0x0000000000000000U
);
io_write_32
(
RALLOC_FSS
,
0x0000000AU
);
io_write_32
(
RALLOC_INSFC
,
0xC7840001U
);
io_write_32
(
RALLOC_BERR
,
0x00000000U
);
io_write_32
(
RALLOC_EARLYR
,
0x00000000U
);
io_write_32
(
RALLOC_RACNT0
,
0x00010003U
);
io_write_32
(
RALLOC_TICKDUPL
,
0x00000000U
);
/* GPU setting */
io_write_32
(
0xFD812030U
,
0x00000000U
);
/* MSTAT setting */
io_write_32
(
MSTAT_SL_INIT
,
0x030500ACU
);
io_write_32
(
MSTAT_REF_ARS
,
0x00780000U
);
/* MSTAT SRAM setting */
{
uint32_t
i
;
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_fix
);
i
++
)
{
io_write_64
(
MSTAT_FIX_QOS_BANK0
+
mstat_fix
[
i
].
addr
,
mstat_fix
[
i
].
value
);
io_write_64
(
MSTAT_FIX_QOS_BANK1
+
mstat_fix
[
i
].
addr
,
mstat_fix
[
i
].
value
);
}
for
(
i
=
0U
;
i
<
ARRAY_SIZE
(
mstat_be
);
i
++
)
{
io_write_64
(
MSTAT_BE_QOS_BANK0
+
mstat_be
[
i
].
addr
,
mstat_be
[
i
].
value
);
io_write_64
(
MSTAT_BE_QOS_BANK1
+
mstat_be
[
i
].
addr
,
mstat_be
[
i
].
value
);
}
}
/* 3DG bus Leaf setting */
io_write_32
(
0xFD820808U
,
0x00001234U
);
io_write_32
(
0xFD820800U
,
0x00000000U
);
io_write_32
(
0xFD821800U
,
0x00000000U
);
io_write_32
(
0xFD822800U
,
0x00000000U
);
io_write_32
(
0xFD823800U
,
0x00000000U
);
/* RT bus Leaf setting */
io_write_32
(
0xF1300800U
,
0x00000003U
);
io_write_32
(
0xF1340800U
,
0x00000003U
);
io_write_32
(
0xFFC50800U
,
0x00000000U
);
io_write_32
(
0xFFC51800U
,
0x00000000U
);
/* Resource Alloc start */
io_write_32
(
RALLOC_RAEN
,
0x00000001U
);
/* MSTAT start */
io_write_32
(
MSTAT_STATQC
,
0x00000001U
);
#else
NOTICE
(
"BL2: QoS is None
\n
"
);
/* Resource Alloc setting */
io_write_32
(
RALLOC_EC
,
0x00000000U
);
/* Resource Alloc start */
io_write_32
(
RALLOC_RAEN
,
0x00000001U
);
#endif
/* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
io_write_32
(
DBSC_DBSYSCNT0
,
0x00000000
);
}
drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h
0 → 100644
View file @
0a4bf763
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef QOS_INIT_H_D3__
#define QOS_INIT_H_D3__
void
qos_init_d3
(
void
);
#endif
/* QOS_INIT_H_D3__ */
drivers/staging/renesas/rcar/qos/qos.mk
View file @
0a4bf763
...
...
@@ -35,6 +35,9 @@ else ifdef RCAR_LSI_CUT_COMPAT
ifeq
(${RCAR_LSI},${RCAR_E3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
endif
ifeq
(${RCAR_LSI},${RCAR_D3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c
endif
else
ifeq
(${RCAR_LSI},${RCAR_H3})
ifeq
(${LSI_CUT},10)
...
...
@@ -88,6 +91,9 @@ else
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
endif
endif
ifeq
(${RCAR_LSI},${RCAR_D3})
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/E3/qos_init_d3.c
endif
endif
BL2_SOURCES
+=
drivers/staging/renesas/rcar/qos/qos_init.c
drivers/staging/renesas/rcar/qos/qos_init.c
View file @
0a4bf763
...
...
@@ -40,6 +40,9 @@
#endif
#if RCAR_LSI == RCAR_E3
/* E3 */
#include "E3/qos_init_e3_v10.h"
#endif
#if RCAR_LSI == RCAR_D3
/* D3 */
#include "D3/qos_init_d3.h"
#endif
/* Product Register */
...
...
@@ -50,13 +53,14 @@
#define PRR_PRODUCT_M3 (0x00005200U)
/* R-Car M3 */
#define PRR_PRODUCT_M3N (0x00005500U)
/* R-Car M3N */
#define PRR_PRODUCT_E3 (0x00005700U)
/* R-Car E3 */
#define PRR_PRODUCT_D3 (0x00005800U)
/* R-Car D3 */
#define PRR_PRODUCT_10 (0x00U)
#define PRR_PRODUCT_11 (0x01U)
#define PRR_PRODUCT_20 (0x10U)
#define PRR_PRODUCT_21 (0x11U)
#define PRR_PRODUCT_30 (0x20U)
#if
!
(RCAR_LSI
=
= RCAR_E3)
#if (RCAR_LSI
!
= RCAR_E3)
&& (RCAR_LSI != RCAR_D3)
#define DRAM_CH_CNT 0x04
uint32_t
qos_init_ddr_ch
;
...
...
@@ -81,7 +85,7 @@ uint8_t qos_init_ddr_phyvalid;
void
rcar_qos_init
(
void
)
{
uint32_t
reg
;
#if
!
(RCAR_LSI
=
= RCAR_E3)
#if (RCAR_LSI
!
= RCAR_E3)
&& (RCAR_LSI != RCAR_D3)
uint32_t
i
;
qos_init_ddr_ch
=
0
;
...
...
@@ -164,6 +168,18 @@ void rcar_qos_init(void)
}
#else
PRR_PRODUCT_ERR
(
reg
);
#endif
break
;
case
PRR_PRODUCT_D3
:
#if (RCAR_LSI == RCAR_D3)
switch
(
reg
&
PRR_CUT_MASK
)
{
case
PRR_PRODUCT_10
:
default:
qos_init_d3
();
break
;
}
#else
PRR_PRODUCT_ERR
(
reg
);
#endif
break
;
default:
...
...
@@ -245,6 +261,13 @@ void rcar_qos_init(void)
PRR_PRODUCT_ERR
(
reg
);
}
qos_init_m3n_v10
();
#elif RCAR_LSI == RCAR_D3
/* D3 */
/* D3 Cut 10 or later */
if
((
PRR_PRODUCT_D3
)
!=
(
reg
&
(
PRR_PRODUCT_MASK
)))
{
PRR_PRODUCT_ERR
(
reg
);
}
qos_init_d3
();
#elif RCAR_LSI == RCAR_E3
/* E3 */
/* E3 Cut 10 or later */
if
((
PRR_PRODUCT_E3
)
...
...
@@ -258,7 +281,7 @@ void rcar_qos_init(void)
#endif
}
#if
!
(RCAR_LSI
=
= RCAR_E3)
#if (RCAR_LSI
!
= RCAR_E3)
&& (RCAR_LSI != RCAR_D3)
uint32_t
get_refperiod
(
void
)
{
uint32_t
refperiod
=
QOSWT_WTSET0_CYCLE
;
...
...
plat/renesas/rcar/bl2_cpg_init.c
View file @
0a4bf763
...
...
@@ -33,6 +33,11 @@ static void bl2_realtime_cpg_init_e3(void);
static
void
bl2_system_cpg_init_e3
(
void
);
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
static
void
bl2_realtime_cpg_init_d3
(
void
);
static
void
bl2_system_cpg_init_d3
(
void
);
#endif
typedef
struct
{
uintptr_t
adr
;
uint32_t
val
;
...
...
@@ -41,21 +46,39 @@ typedef struct {
static
void
bl2_secure_cpg_init
(
void
)
{
uint32_t
stop_cr2
,
reset_cr2
;
uint32_t
stop_cr4
,
reset_cr4
;
uint32_t
stop_cr5
,
reset_cr5
;
#if (RCAR_LSI == RCAR_E3)
#if (RCAR_LSI == RCAR_D3)
reset_cr2
=
0x00000000U
;
stop_cr2
=
0xFFFFFFFFU
;
#elif (RCAR_LSI == RCAR_E3)
reset_cr2
=
0x10000000U
;
stop_cr2
=
0xEFFFFFFFU
;
#else
reset_cr2
=
0x14000000U
;
stop_cr2
=
0xEBFFFFFFU
;
#endif
#if (RCAR_LSI == RCAR_D3)
reset_cr4
=
0x00000000U
;
stop_cr4
=
0xFFFFFFFFU
;
reset_cr5
=
0x00000000U
;
stop_cr5
=
0xFFFFFFFFU
;
#else
reset_cr4
=
0x80000003U
;
stop_cr4
=
0x7FFFFFFFU
;
reset_cr5
=
0x40000000U
;
stop_cr5
=
0xBFFFFFFFU
;
#endif
/** Secure Module Stop Control Registers */
cpg_write
(
SCMSTPCR0
,
0xFFFFFFFFU
);
cpg_write
(
SCMSTPCR1
,
0xFFFFFFFFU
);
cpg_write
(
SCMSTPCR2
,
stop_cr2
);
cpg_write
(
SCMSTPCR3
,
0xFFFFFFFFU
);
cpg_write
(
SCMSTPCR4
,
0x7FFFFFFFU
);
cpg_write
(
SCMSTPCR5
,
0xBFFFFFFFU
);
cpg_write
(
SCMSTPCR4
,
stop_cr4
);
cpg_write
(
SCMSTPCR5
,
stop_cr5
);
cpg_write
(
SCMSTPCR6
,
0xFFFFFFFFU
);
cpg_write
(
SCMSTPCR7
,
0xFFFFFFFFU
);
cpg_write
(
SCMSTPCR8
,
0xFFFFFFFFU
);
...
...
@@ -68,8 +91,8 @@ static void bl2_secure_cpg_init(void)
cpg_write
(
SCSRSTECR1
,
0x00000000U
);
cpg_write
(
SCSRSTECR2
,
reset_cr2
);
cpg_write
(
SCSRSTECR3
,
0x00000000U
);
cpg_write
(
SCSRSTECR4
,
0x80000003U
);
cpg_write
(
SCSRSTECR5
,
0x40000000U
);
cpg_write
(
SCSRSTECR4
,
reset_cr4
);
cpg_write
(
SCSRSTECR5
,
reset_cr5
);
cpg_write
(
SCSRSTECR6
,
0x00000000U
);
cpg_write
(
SCSRSTECR7
,
0x00000000U
);
cpg_write
(
SCSRSTECR8
,
0x00000000U
);
...
...
@@ -229,6 +252,42 @@ static void bl2_system_cpg_init_e3(void)
}
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
static
void
bl2_realtime_cpg_init_d3
(
void
)
{
/* Realtime Module Stop Control Registers */
cpg_write
(
RMSTPCR0
,
0x00010000U
);
cpg_write
(
RMSTPCR1
,
0xFFFFFFFFU
);
cpg_write
(
RMSTPCR2
,
0x00060FDCU
);
cpg_write
(
RMSTPCR3
,
0xFFFFFFDFU
);
cpg_write
(
RMSTPCR4
,
0x80000184U
);
cpg_write
(
RMSTPCR5
,
0x83FFFFFFU
);
cpg_write
(
RMSTPCR6
,
0xFFFFFFFFU
);
cpg_write
(
RMSTPCR7
,
0xFFFFFFFFU
);
cpg_write
(
RMSTPCR8
,
0x00F1FFF7U
);
cpg_write
(
RMSTPCR9
,
0xF3F5E016U
);
cpg_write
(
RMSTPCR10
,
0xFFFEFFE0U
);
cpg_write
(
RMSTPCR11
,
0x000000B7U
);
}
static
void
bl2_system_cpg_init_d3
(
void
)
{
/* System Module Stop Control Registers */
cpg_write
(
SMSTPCR0
,
0x00010000U
);
cpg_write
(
SMSTPCR1
,
0xFFFFFFFFU
);
cpg_write
(
SMSTPCR2
,
0x00060FDCU
);
cpg_write
(
SMSTPCR3
,
0xFFFFFBDFU
);
cpg_write
(
SMSTPCR4
,
0x00000084U
);
cpg_write
(
SMSTPCR5
,
0x83FFFFFFU
);
cpg_write
(
SMSTPCR6
,
0xFFFFFFFFU
);
cpg_write
(
SMSTPCR7
,
0xFFFFFFFFU
);
cpg_write
(
SMSTPCR8
,
0x00F1FFF7U
);
cpg_write
(
SMSTPCR9
,
0xF3F5E016U
);
cpg_write
(
SMSTPCR10
,
0xFFFEFFE0U
);
cpg_write
(
SMSTPCR11
,
0x000000B7U
);
}
#endif
void
bl2_cpg_init
(
void
)
{
uint32_t
boot_cpu
=
mmio_read_32
(
RCAR_MODEMR
)
&
MODEMR_BOOT_CPU_MASK
;
...
...
@@ -254,6 +313,9 @@ void bl2_cpg_init(void)
case
RCAR_PRODUCT_E3
:
bl2_realtime_cpg_init_e3
();
break
;
case
RCAR_PRODUCT_D3
:
bl2_realtime_cpg_init_d3
();
break
;
default:
panic
();
break
;
...
...
@@ -266,6 +328,8 @@ void bl2_cpg_init(void)
bl2_realtime_cpg_init_m3n
();
#elif RCAR_LSI == RCAR_E3
bl2_realtime_cpg_init_e3
();
#elif RCAR_LSI == RCAR_D3
bl2_realtime_cpg_init_d3
();
#else
#error "Don't have CPG initialize routine(unknown)."
#endif
...
...
@@ -290,6 +354,9 @@ void bl2_system_cpg_init(void)
case
RCAR_PRODUCT_E3
:
bl2_system_cpg_init_e3
();
break
;
case
RCAR_PRODUCT_D3
:
bl2_system_cpg_init_d3
();
break
;
default:
panic
();
break
;
...
...
@@ -302,6 +369,8 @@ void bl2_system_cpg_init(void)
bl2_system_cpg_init_m3n
();
#elif RCAR_LSI == RCAR_E3
bl2_system_cpg_init_e3
();
#elif RCAR_LSI == RCAR_D3
bl2_system_cpg_init_d3
();
#else
#error "Don't have CPG initialize routine(unknown)."
#endif
...
...
plat/renesas/rcar/bl2_plat_setup.c
View file @
0a4bf763
...
...
@@ -76,6 +76,9 @@ static void bl2_init_generic_timer(void);
#elif RCAR_LSI == RCAR_E3
#define TARGET_PRODUCT RCAR_PRODUCT_E3
#define TARGET_NAME "R-Car E3"
#elif RCAR_LSI == RCAR_D3
#define TARGET_PRODUCT RCAR_PRODUCT_D3
#define TARGET_NAME "R-Car D3"
#elif RCAR_LSI == RCAR_AUTO
#define TARGET_NAME "R-Car H3/M3/M3N"
#endif
...
...
@@ -242,6 +245,9 @@ void bl2_plat_flush_bl31_params(void)
if
(
product
==
RCAR_PRODUCT_H3
&&
RCAR_CUT_VER20
>
cut
)
goto
tlb
;
if
(
product
==
RCAR_PRODUCT_D3
)
goto
tlb
;
/* Disable MFIS write protection */
mmio_write_32
(
MFISWPCNTR
,
MFISWPCNTR_PASSWORD
|
1
);
...
...
@@ -430,6 +436,10 @@ static void bl2_populate_compatible_string(void *fdt)
ret
=
fdt_setprop_string
(
fdt
,
0
,
"compatible"
,
"renesas,ebisu"
);
break
;
case
BOARD_DRAAK
:
ret
=
fdt_setprop_string
(
fdt
,
0
,
"compatible"
,
"renesas,draak"
);
break
;
default:
NOTICE
(
"BL2: Cannot set compatible string, board unsupported
\n
"
);
panic
();
...
...
@@ -458,6 +468,10 @@ static void bl2_populate_compatible_string(void *fdt)
ret
=
fdt_appendprop_string
(
fdt
,
0
,
"compatible"
,
"renesas,r8a77990"
);
break
;
case
RCAR_PRODUCT_D3
:
ret
=
fdt_appendprop_string
(
fdt
,
0
,
"compatible"
,
"renesas,r8a77995"
);
break
;
default:
NOTICE
(
"BL2: Cannot set compatible string, SoC unsupported
\n
"
);
panic
();
...
...
@@ -482,8 +496,10 @@ static void bl2_advertise_dram_entries(uint64_t dram_config[8])
if
(
!
size
)
continue
;
NOTICE
(
"BL2: CH%d: %llx - %llx, %lld GiB
\n
"
,
chan
,
start
,
start
+
size
-
1
,
size
>>
30
);
NOTICE
(
"BL2: CH%d: %llx - %llx, %lld %siB
\n
"
,
chan
,
start
,
start
+
size
-
1
,
(
size
>>
30
)
?
:
size
>>
20
,
(
size
>>
30
)
?
"G"
:
"M"
);
}
/*
...
...
@@ -596,6 +612,11 @@ static void bl2_advertise_dram_size(uint32_t product)
dram_config
[
1
]
=
0x100000000ULL
;
#endif
/* RCAR_DRAM_DDR3L_MEMCONF == 0 */
break
;
case
RCAR_PRODUCT_D3
:
/* 512MB */
dram_config
[
1
]
=
0x20000000ULL
;
break
;
}
bl2_advertise_dram_entries
(
dram_config
);
...
...
@@ -615,6 +636,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
const
char
*
product_h3
=
"H3"
;
const
char
*
product_m3
=
"M3"
;
const
char
*
product_e3
=
"E3"
;
const
char
*
product_d3
=
"D3"
;
const
char
*
lcs_secure
=
"SE"
;
const
char
*
lcs_cm
=
"CM"
;
const
char
*
lcs_dm
=
"DM"
;
...
...
@@ -627,7 +649,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
const
char
*
boot_qspi80
=
"QSPI Flash(80MHz)"
;
const
char
*
boot_emmc25x1
=
"eMMC(25MHz x1)"
;
const
char
*
boot_emmc50x8
=
"eMMC(50MHz x8)"
;
#if RCAR_LSI == RCAR_E3
#if
(
RCAR_LSI == RCAR_E3
) || (RCAR_LSI == RCAR_D3)
const
char
*
boot_hyper160
=
"HyperFlash(150MHz)"
;
#else
const
char
*
boot_hyper160
=
"HyperFlash(160MHz)"
;
...
...
@@ -694,6 +716,9 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
case
RCAR_PRODUCT_E3
:
str
=
product_e3
;
break
;
case
RCAR_PRODUCT_D3
:
str
=
product_d3
;
break
;
default:
str
=
unknown
;
break
;
...
...
@@ -734,6 +759,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
case
BOARD_EBISU
:
case
BOARD_STARTER_KIT_PRE
:
case
BOARD_EBISU_4D
:
case
BOARD_DRAAK
:
break
;
default:
type
=
BOARD_UNKNOWN
;
...
...
@@ -772,9 +798,17 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
str
=
boot_qspi80
;
break
;
case
MODEMR_BOOT_DEV_EMMC_25X1
:
#if RCAR_LSI == RCAR_D3
ERROR
(
"BL2: Failed to Initialize. eMMC is not supported.
\n
"
);
panic
();
#endif
str
=
boot_emmc25x1
;
break
;
case
MODEMR_BOOT_DEV_EMMC_50X8
:
#if RCAR_LSI == RCAR_D3
ERROR
(
"BL2: Failed to Initialize. eMMC is not supported.
\n
"
);
panic
();
#endif
str
=
boot_emmc50x8
;
break
;
default:
...
...
@@ -938,7 +972,9 @@ void bl2_platform_setup(void)
static
void
bl2_init_generic_timer
(
void
)
{
#if RCAR_LSI == RCAR_E3
#if RCAR_LSI == RCAR_D3
uint32_t
reg_cntfid
=
EXTAL_DRAAK
;
#elif RCAR_LSI == RCAR_E3
uint32_t
reg_cntfid
=
EXTAL_EBISU
;
#else
/* RCAR_LSI == RCAR_E3 */
uint32_t
reg
;
...
...
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