diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index 53bce7d5a04c19a279bd72b4d6f829235b0b39e5..797d8d7c13fa2c8e11493c57e65519645c4fa8e2 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -36,7 +36,7 @@ ENTRY(tsp_entrypoint) MEMORY { - RAM (rwx): ORIGIN = TZDRAM_BASE, LENGTH = TZDRAM_SIZE + RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE } @@ -119,5 +119,5 @@ SECTIONS __COHERENT_RAM_UNALIGNED_SIZE__ = __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; - ASSERT(. <= TZDRAM_BASE + (1 << 21), "BL32 image does not fit in the first 2MB of Trusted DRAM.") + ASSERT(. <= BL32_LIMIT, "BL3-2 image does not fit.") } diff --git a/docs/porting-guide.md b/docs/porting-guide.md index 721ba1b6359bd7a44d1acd7c7c9d97263f1342c7..c66279ca60b052557dee1c385f9bd33c37e7b4e7 100644 --- a/docs/porting-guide.md +++ b/docs/porting-guide.md @@ -191,9 +191,36 @@ constants defined. In the ARM FVP port, this file is found in image. Must be aligned on a page-size boundary. * **#define : NS_IMAGE_OFFSET** + Defines the base address in non-secure DRAM where BL2 loads the BL3-3 binary image. Must be aligned on a page-size boundary. +If the BL3-2 image is supported by the platform, the following constants must +be defined as well: + +* **#define : TSP_SEC_MEM_BASE** + + Defines the base address of the secure memory used by the BL3-2 image on the + platform. + +* **#define : TSP_SEC_MEM_SIZE** + + Defines the size of the secure memory used by the BL3-2 image on the + platform. + +* **#define : BL32_BASE** + + Defines the base address in secure memory where BL2 loads the BL3-2 binary + image. Must be inside the secure memory identified by `TSP_SEC_MEM_BASE` and + `TSP_SEC_MEM_SIZE` constants. Must also be aligned on a page-size boundary. + +* **#define : BL32_LIMIT** + + Defines the maximum address that the BL3-2 image can occupy. Must be inside + the secure memory identified by `TSP_SEC_MEM_BASE` and `TSP_SEC_MEM_SIZE` + constants. + + ### File : platform_macros.S [mandatory] Each platform must export a file of this name with the following diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c index 38525eac5d7c834a1e1b34b60662e6ad616cac72..11d300a09b8572c545901d2ff2401ccb135a3ce8 100644 --- a/plat/fvp/bl2_plat_setup.c +++ b/plat/fvp/bl2_plat_setup.c @@ -267,9 +267,9 @@ extern void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) bl32_meminfo->total_base = BL32_BASE; bl32_meminfo->free_base = BL32_BASE; bl32_meminfo->total_size = - (TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE; + (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; bl32_meminfo->free_size = - (TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE; + (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; bl32_meminfo->attr = BOT_LOAD; bl32_meminfo->next = 0; } diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h index 4c8d6064a1b6be5a2731a5e52e7de8ceb84b484a..e6d120d7546a9544444271929abf739cac2202bf 100644 --- a/plat/fvp/platform.h +++ b/plat/fvp/platform.h @@ -248,7 +248,10 @@ /******************************************************************************* * BL32 specific defines. ******************************************************************************/ +#define TSP_SEC_MEM_BASE TZDRAM_BASE +#define TSP_SEC_MEM_SIZE TZDRAM_SIZE #define BL32_BASE (TZDRAM_BASE + 0x2000) +#define BL32_LIMIT (TZDRAM_BASE + (1 << 21)) /******************************************************************************* * Platform specific page table and MMU setup constants