From 0d15a2290f666127e2d29503b4924349bebc92c5 Mon Sep 17 00:00:00 2001
From: Sandrine Bailleux <sandrine.bailleux@arm.com>
Date: Tue, 20 May 2014 17:22:24 +0100
Subject: [PATCH] TSP: Let the platform decide which secure memory to use
The TSP's linker script used to assume that the TSP would
execute from secure DRAM. Although it is currently the case
on FVPs, platforms are free to use any secure memory they wish.
This patch introduces the flexibility to load the TSP into any
secure memory. The platform code gets to specify the extents of
this memory in the platform header file, as well as the BL3-2 image
limit address. The latter definition allows to check in a generic way
that the BL3-2 image fits in its bounds.
Change-Id: I9450f2d8b32d74bd00b6ce57a0a1542716ab449c
---
bl32/tsp/tsp.ld.S | 4 ++--
docs/porting-guide.md | 27 +++++++++++++++++++++++++++
plat/fvp/bl2_plat_setup.c | 4 ++--
plat/fvp/platform.h | 3 +++
4 files changed, 34 insertions(+), 4 deletions(-)
diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S
index 53bce7d5a..797d8d7c1 100644
--- a/bl32/tsp/tsp.ld.S
+++ b/bl32/tsp/tsp.ld.S
@@ -36,7 +36,7 @@ ENTRY(tsp_entrypoint)
MEMORY {
- RAM (rwx): ORIGIN = TZDRAM_BASE, LENGTH = TZDRAM_SIZE
+ RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
}
@@ -119,5 +119,5 @@ SECTIONS
__COHERENT_RAM_UNALIGNED_SIZE__ =
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
- ASSERT(. <= TZDRAM_BASE + (1 << 21), "BL32 image does not fit in the first 2MB of Trusted DRAM.")
+ ASSERT(. <= BL32_LIMIT, "BL3-2 image does not fit.")
}
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 721ba1b63..c66279ca6 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -191,9 +191,36 @@ constants defined. In the ARM FVP port, this file is found in
image. Must be aligned on a page-size boundary.
* **#define : NS_IMAGE_OFFSET**
+
Defines the base address in non-secure DRAM where BL2 loads the BL3-3 binary
image. Must be aligned on a page-size boundary.
+If the BL3-2 image is supported by the platform, the following constants must
+be defined as well:
+
+* **#define : TSP_SEC_MEM_BASE**
+
+ Defines the base address of the secure memory used by the BL3-2 image on the
+ platform.
+
+* **#define : TSP_SEC_MEM_SIZE**
+
+ Defines the size of the secure memory used by the BL3-2 image on the
+ platform.
+
+* **#define : BL32_BASE**
+
+ Defines the base address in secure memory where BL2 loads the BL3-2 binary
+ image. Must be inside the secure memory identified by `TSP_SEC_MEM_BASE` and
+ `TSP_SEC_MEM_SIZE` constants. Must also be aligned on a page-size boundary.
+
+* **#define : BL32_LIMIT**
+
+ Defines the maximum address that the BL3-2 image can occupy. Must be inside
+ the secure memory identified by `TSP_SEC_MEM_BASE` and `TSP_SEC_MEM_SIZE`
+ constants.
+
+
### File : platform_macros.S [mandatory]
Each platform must export a file of this name with the following
diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c
index 38525eac5..11d300a09 100644
--- a/plat/fvp/bl2_plat_setup.c
+++ b/plat/fvp/bl2_plat_setup.c
@@ -267,9 +267,9 @@ extern void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
bl32_meminfo->total_base = BL32_BASE;
bl32_meminfo->free_base = BL32_BASE;
bl32_meminfo->total_size =
- (TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
+ (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
bl32_meminfo->free_size =
- (TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
+ (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
bl32_meminfo->attr = BOT_LOAD;
bl32_meminfo->next = 0;
}
diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h
index 4c8d6064a..e6d120d75 100644
--- a/plat/fvp/platform.h
+++ b/plat/fvp/platform.h
@@ -248,7 +248,10 @@
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
+#define TSP_SEC_MEM_BASE TZDRAM_BASE
+#define TSP_SEC_MEM_SIZE TZDRAM_SIZE
#define BL32_BASE (TZDRAM_BASE + 0x2000)
+#define BL32_LIMIT (TZDRAM_BASE + (1 << 21))
/*******************************************************************************
* Platform specific page table and MMU setup constants
--
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