From 121f2ae7ce54560ed3af4ee6f5abd328ce2088a3 Mon Sep 17 00:00:00 2001
From: Sandrine Bailleux <sandrine.bailleux@arm.com>
Date: Wed, 28 Jan 2015 10:11:48 +0000
Subject: [PATCH] Miscellaneous doc fixes for v1.1
Change-Id: Iaf9d6305edc478d39cf1b37c8a70ccdf723e8ef9
---
docs/cpu-specific-build-macros.md | 2 +-
docs/firmware-design.md | 6 +++---
docs/porting-guide.md | 7 ++++---
docs/user-guide.md | 6 +-----
4 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md
index b913f5ff1..2368fd221 100644
--- a/docs/cpu-specific-build-macros.md
+++ b/docs/cpu-specific-build-macros.md
@@ -21,7 +21,7 @@ for a specific CPU on a platform.
ARM Trusted Firmware exports a series of build flags which control the
errata workarounds that are applied to each CPU by the reset handler. The
-errata details can be found in the CPU specifc errata documents published
+errata details can be found in the CPU specific errata documents published
by ARM. The errata workarounds are implemented for a particular revision
or a set of processor revisions. This is checked by reset handler at runtime.
Each errata workaround is identified by its `ID` as specified in the processor's
diff --git a/docs/firmware-design.md b/docs/firmware-design.md
index acfef4e26..f0c2f629b 100644
--- a/docs/firmware-design.md
+++ b/docs/firmware-design.md
@@ -425,7 +425,7 @@ EL3, little-endian data access, and all interrupt sources masked:
PSTATE.EL = 3
PSTATE.RW = 1
PSTATE.DAIF = 0xf
- CTLR_EL3.EE = 0
+ SCTLR_EL3.EE = 0
X0 and X1 can be used to pass information from the Trusted Boot Firmware to the
platform code in BL3-1:
@@ -1060,9 +1060,9 @@ of any coherency domain.
The BL entrypoint code first invokes the `plat_reset_handler()` to allow
the platform to perform any system initialization required and any system
-errata wrokarounds that needs to be applied. The `get_cpu_ops_ptr()` reads
+errata workarounds that needs to be applied. The `get_cpu_ops_ptr()` reads
the current CPU midr, finds the matching `cpu_ops` entry in the `cpu_ops`
-array and returns it. Note that only the part number and implementator fields
+array and returns it. Note that only the part number and implementer fields
in midr are used to find the matching `cpu_ops` entry. The `reset_func()` in
the returned `cpu_ops` is then invoked which executes the required reset
handling for that CPU and also any errata workarounds enabled by the platform.
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 09cd7d5ed..5a04c54c6 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -1445,9 +1445,10 @@ function uses the storage layer to access non-volatile platform storage.
It is mandatory to implement at least one storage driver. For the FVP the
Firmware Image Package(FIP) driver is provided as the default means to load data
from storage (see the "Firmware Image Package" section in the [User Guide]).
-The storage layer is described in the header file `include/io_storage.h`. The
-implementation of the common library is in `lib/io_storage.c` and the driver
-files are located in `drivers/io/`.
+The storage layer is described in the header file
+`include/drivers/io/io_storage.h`. The implementation of the common library
+is in `drivers/io/io_storage.c` and the driver files are located in
+`drivers/io/`.
Each IO driver must provide `io_dev_*` structures, as described in
`drivers/io/io_driver.h`. These are returned via a mandatory registration
diff --git a/docs/user-guide.md b/docs/user-guide.md
index 4209be7ec..e8a3794ec 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -511,7 +511,7 @@ Preparing a Linux kernel for use on the FVPs can be done as follows
git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Not all required features are available in the kernel mainline yet. These
- can be obtained from the ARM-software EDK2 repository instead:
+ can be obtained from the ARM-software Linux repository instead:
cd linux
git remote add -f --tags arm-software https://github.com/ARM-software/linux.git
@@ -790,7 +790,6 @@ with 8 CPUs using the ARM Trusted Firmware.
-C cluster0.NUM_CORES=4 \
-C cluster1.NUM_CORES=4 \
-C cache_state_modelled=1 \
- -C bp.pl011_uart0.untimed_fifos=1 \
-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
@@ -808,7 +807,6 @@ boot Linux with 8 CPUs using the ARM Trusted Firmware.
-C bp.secure_memory=1 \
-C bp.tzc_400.diagnostics=1 \
-C cache_state_modelled=1 \
- -C bp.pl011_uart0.untimed_fifos=1 \
-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
@@ -828,7 +826,6 @@ with 8 CPUs using the ARM Trusted Firmware.
-C cluster0.NUM_CORES=4 \
-C cluster1.NUM_CORES=4 \
-C cache_state_modelled=1 \
- -C bp.pl011_uart0.untimed_fifos=1 \
-C cluster0.cpu0.RVBAR=0x04023000 \
-C cluster0.cpu1.RVBAR=0x04023000 \
-C cluster0.cpu2.RVBAR=0x04023000 \
@@ -855,7 +852,6 @@ boot Linux with 8 CPUs using the ARM Trusted Firmware.
-C bp.secure_memory=1 \
-C bp.tzc_400.diagnostics=1 \
-C cache_state_modelled=1 \
- -C bp.pl011_uart0.untimed_fifos=1 \
-C cluster0.cpu0.RVBARADDR=0x04023000 \
-C cluster0.cpu1.RVBARADDR=0x04023000 \
-C cluster0.cpu2.RVBARADDR=0x04023000 \
--
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