From 14105374e5afa1af6e94396bc337ade0b926afe8 Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Mon, 23 Jan 2017 16:15:44 -0800 Subject: [PATCH] Tegra194: Support for cpu suspend This patch adds support for cpu suspend in T19x soc. Change-Id: I8ef1d3e03ee9c528dec34eaff6dcbbfa43941484 Signed-off-by: Krishna Sitaraman --- plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index e53d5946e..59131b3d2 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -39,7 +39,7 @@ extern uint32_t __tegra186_cpu_reset_handler_data, #define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 #define TEGRA186_WAKE_TIME_SHIFT 4 /* default core wake mask for CPU_SUSPEND */ -#define TEGRA186_CORE_WAKE_MASK 0x180c +#define TEGRA194_CORE_WAKE_MASK 0x180c /* context size to save during system suspend */ #define TEGRA186_SE_CONTEXT_SIZE 3 @@ -97,6 +97,7 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) #endif uint32_t val; mce_cstate_info_t cstate_info = { 0 }; + int cpu = plat_my_core_pos(); /* get the state ID */ pwr_domain_state = target_state->pwr_domain_state; @@ -109,6 +110,10 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { /* Enter CPU idle/powerdown */ + val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? + TEGRA_NVG_CORE_C6 : TEGRA_NVG_CORE_C7; + (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val, + percpu_data[cpu].wake_time, 0); } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { @@ -173,6 +178,7 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, plat_local_state_t target = *states; int cluster_powerdn = 1; int core_pos = read_mpidr() & MPIDR_CPU_MASK; + mce_cstate_info_t cstate_info = { 0 }; /* get the current core's power state */ target = *(states + core_pos); @@ -181,8 +187,9 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) { /* Program default wake mask */ - - /* Check if CCx state is allowed. */ + cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; + cstate_info.update_wake_mask = 1; + mce_update_cstate_info(&cstate_info); } /* CPU off */ -- GitLab