From 175476f9e561704ab309c60cba531d95b1c0aa6b Mon Sep 17 00:00:00 2001 From: Xing Zheng <zhengxing@rock-chips.com> Date: Tue, 20 Dec 2016 20:44:41 +0800 Subject: [PATCH] FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init We found that the DUT will be hanged if we don't set the bit_1 of the PMUCRU_GATEDIS_CON0. But, from the TRM, there is weird that the bit_1 is set the clk_center1_gating_dis, not clk_pmum0_gating_dis. Is the TRM incorrect? We need to check it with the IC team and re-clean the commit message and explain it tomorrow. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> --- plat/rockchip/rk3399/drivers/pmu/m0_ctl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c index 11bc0eaef..66f3a19c8 100644 --- a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c +++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c @@ -53,7 +53,8 @@ void m0_init(void) 0xf, 0)); /* gating disable for M0 */ - mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, BIT_WITH_WMSK(0)); + mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, + BITS_WITH_WMASK(0x3, 0x3, 0)); /* * To switch the parent to xin24M and div == 1, -- GitLab