diff --git a/bl32/tsp/tsp-fvp.mk b/bl32/tsp/tsp-fvp.mk
index b1d0afef1beb96116b4e4ca9ab3b9fa0de21b653..21864d68da930da20b31d9eb967c842e3dc8cf6f 100644
--- a/bl32/tsp/tsp-fvp.mk
+++ b/bl32/tsp/tsp-fvp.mk
@@ -31,7 +31,7 @@
# TSP source files specific to FVP platform
BL32_SOURCES += drivers/arm/gic/gic_v2.c \
plat/common/aarch64/platform_mp_stack.S \
- plat/fvp/aarch64/plat_common.c \
- plat/fvp/aarch64/plat_helpers.S \
- plat/fvp/bl32_plat_setup.c \
- plat/fvp/plat_gic.c
+ plat/fvp/aarch64/fvp_common.c \
+ plat/fvp/aarch64/fvp_helpers.S \
+ plat/fvp/bl32_fvp_setup.c \
+ plat/fvp/fvp_gic.c
diff --git a/plat/fvp/aarch64/plat_common.c b/plat/fvp/aarch64/fvp_common.c
similarity index 89%
rename from plat/fvp/aarch64/plat_common.c
rename to plat/fvp/aarch64/fvp_common.c
index f0a06d83e430c9b2fcecf63206b3aa2cb61b61b2..acfb75287ee89238031067894790da0c5c8640be 100644
--- a/plat/fvp/aarch64/plat_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -46,7 +46,7 @@
* configuration) & used thereafter. Each BL will have its own copy to allow
* independent operation.
******************************************************************************/
-static unsigned long platform_config[CONFIG_LIMIT];
+static unsigned long fvp_config[CONFIG_LIMIT];
/*******************************************************************************
* Macro generating the code for the function enabling the MMU in the given
@@ -132,7 +132,7 @@ const mmap_region_t fvp_mmap[] = {
* the platform memory map & initialize the mmu, for the given exception level
******************************************************************************/
#define DEFINE_CONFIGURE_MMU_EL(_el) \
- void configure_mmu_el##_el(unsigned long total_base, \
+ void fvp_configure_mmu_el##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit, \
@@ -157,10 +157,10 @@ DEFINE_CONFIGURE_MMU_EL(1)
DEFINE_CONFIGURE_MMU_EL(3)
/* Simple routine which returns a configuration variable value */
-unsigned long platform_get_cfgvar(unsigned int var_id)
+unsigned long fvp_get_cfgvar(unsigned int var_id)
{
assert(var_id < CONFIG_LIMIT);
- return platform_config[var_id];
+ return fvp_config[var_id];
}
/*******************************************************************************
@@ -170,7 +170,7 @@ unsigned long platform_get_cfgvar(unsigned int var_id)
* these platforms. This information is stored in a per-BL array to allow the
* code to take the correct path.Per BL platform configuration.
******************************************************************************/
-int platform_config_setup(void)
+int fvp_config_setup(void)
{
unsigned int rev, hbi, bld, arch, sys_id, midr_pn;
@@ -189,16 +189,16 @@ int platform_config_setup(void)
*/
switch (bld) {
case BLD_GIC_VE_MMAP:
- platform_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
- platform_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
- platform_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
- platform_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
+ fvp_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
+ fvp_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
+ fvp_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
+ fvp_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
break;
case BLD_GIC_A53A57_MMAP:
- platform_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
- platform_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
- platform_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
- platform_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
+ fvp_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
+ fvp_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
+ fvp_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
+ fvp_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
break;
default:
assert(0);
@@ -210,25 +210,25 @@ int platform_config_setup(void)
*/
switch (hbi) {
case HBI_FOUNDATION:
- platform_config[CONFIG_MAX_AFF0] = 4;
- platform_config[CONFIG_MAX_AFF1] = 1;
- platform_config[CONFIG_CPU_SETUP] = 0;
- platform_config[CONFIG_BASE_MMAP] = 0;
- platform_config[CONFIG_HAS_CCI] = 0;
- platform_config[CONFIG_HAS_TZC] = 0;
+ fvp_config[CONFIG_MAX_AFF0] = 4;
+ fvp_config[CONFIG_MAX_AFF1] = 1;
+ fvp_config[CONFIG_CPU_SETUP] = 0;
+ fvp_config[CONFIG_BASE_MMAP] = 0;
+ fvp_config[CONFIG_HAS_CCI] = 0;
+ fvp_config[CONFIG_HAS_TZC] = 0;
break;
case HBI_FVP_BASE:
midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
if ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
- platform_config[CONFIG_CPU_SETUP] = 1;
+ fvp_config[CONFIG_CPU_SETUP] = 1;
else
- platform_config[CONFIG_CPU_SETUP] = 0;
+ fvp_config[CONFIG_CPU_SETUP] = 0;
- platform_config[CONFIG_MAX_AFF0] = 4;
- platform_config[CONFIG_MAX_AFF1] = 2;
- platform_config[CONFIG_BASE_MMAP] = 1;
- platform_config[CONFIG_HAS_CCI] = 1;
- platform_config[CONFIG_HAS_TZC] = 1;
+ fvp_config[CONFIG_MAX_AFF0] = 4;
+ fvp_config[CONFIG_MAX_AFF1] = 2;
+ fvp_config[CONFIG_BASE_MMAP] = 1;
+ fvp_config[CONFIG_HAS_CCI] = 1;
+ fvp_config[CONFIG_HAS_TZC] = 1;
break;
default:
assert(0);
@@ -264,7 +264,7 @@ void fvp_cci_setup(void)
* for locks as no other cpu is active at the
* moment
*/
- cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+ cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
if (cci_setup)
cci_enable_coherency(read_mpidr());
}
diff --git a/plat/fvp/aarch64/plat_helpers.S b/plat/fvp/aarch64/fvp_helpers.S
similarity index 98%
rename from plat/fvp/aarch64/plat_helpers.S
rename to plat/fvp/aarch64/fvp_helpers.S
index fbb2fce36abe6702365def139105aae93f078423..f856f460574dc7497929b67c3860d41b1d4d93ef 100644
--- a/plat/fvp/aarch64/plat_helpers.S
+++ b/plat/fvp/aarch64/fvp_helpers.S
@@ -40,7 +40,7 @@
.globl platform_mem_init
.globl plat_report_exception
- .macro platform_choose_gicmmap param1, param2, x_tmp, w_tmp, res
+ .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
ldr \x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID
ldr \w_tmp, [\x_tmp]
ubfx \w_tmp, \w_tmp, #SYS_ID_BLD_SHIFT, #SYS_ID_BLD_LENGTH
@@ -78,7 +78,7 @@ func plat_secondary_cold_boot_setup
*/
ldr x0, =VE_GICC_BASE
ldr x1, =BASE_GICC_BASE
- platform_choose_gicmmap x0, x1, x2, w2, x1
+ fvp_choose_gicmmap x0, x1, x2, w2, x1
mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
str w0, [x1, #GICC_CTLR]
diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_fvp_setup.c
similarity index 95%
rename from plat/fvp/bl1_plat_setup.c
rename to plat/fvp/bl1_fvp_setup.c
index 34e74e259a1808814e78192ad664278089bbe6f2..f758082c59dc7fe43b7087b664ab22eb2c1ddc9d 100644
--- a/plat/fvp/bl1_plat_setup.c
+++ b/plat/fvp/bl1_fvp_setup.c
@@ -105,7 +105,7 @@ void bl1_early_platform_setup(void)
}
/* Initialize the platform config for future decision making */
- platform_config_setup();
+ fvp_config_setup();
}
/*******************************************************************************
@@ -116,7 +116,7 @@ void bl1_early_platform_setup(void)
void bl1_platform_setup(void)
{
/* Initialise the IO layer and register platform IO devices */
- io_setup();
+ fvp_io_setup();
}
@@ -129,12 +129,12 @@ void bl1_plat_arch_setup(void)
{
fvp_cci_setup();
- configure_mmu_el3(bl1_tzram_layout.total_base,
- bl1_tzram_layout.total_size,
- TZROM_BASE,
- TZROM_BASE + TZROM_SIZE,
- BL1_COHERENT_RAM_BASE,
- BL1_COHERENT_RAM_LIMIT);
+ fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
+ bl1_tzram_layout.total_size,
+ TZROM_BASE,
+ TZROM_BASE + TZROM_SIZE,
+ BL1_COHERENT_RAM_BASE,
+ BL1_COHERENT_RAM_LIMIT);
}
diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_fvp_setup.c
similarity index 97%
rename from plat/fvp/bl2_plat_setup.c
rename to plat/fvp/bl2_fvp_setup.c
index 2cfb8bca9dec10a23319f9872862b4172c097879..e18cf7ddb43ca800095a39d7b03d7c2044c11a06 100644
--- a/plat/fvp/bl2_plat_setup.c
+++ b/plat/fvp/bl2_fvp_setup.c
@@ -179,7 +179,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
bl2_tzram_layout.next = 0;
/* Initialize the platform config for future decision making */
- platform_config_setup();
+ fvp_config_setup();
}
/*******************************************************************************
@@ -194,10 +194,10 @@ void bl2_platform_setup(void)
* other platforms might have more programmable security devices
* present.
*/
- plat_security_setup();
+ fvp_security_setup();
/* Initialise the IO layer and register platform IO devices */
- io_setup();
+ fvp_io_setup();
}
/* Flush the TF params and the TF plat params */
@@ -214,12 +214,12 @@ void bl2_plat_flush_bl31_params(void)
******************************************************************************/
void bl2_plat_arch_setup()
{
- configure_mmu_el1(bl2_tzram_layout.total_base,
- bl2_tzram_layout.total_size,
- BL2_RO_BASE,
- BL2_RO_LIMIT,
- BL2_COHERENT_RAM_BASE,
- BL2_COHERENT_RAM_LIMIT);
+ fvp_configure_mmu_el1(bl2_tzram_layout.total_base,
+ bl2_tzram_layout.total_size,
+ BL2_RO_BASE,
+ BL2_RO_LIMIT,
+ BL2_COHERENT_RAM_BASE,
+ BL2_COHERENT_RAM_LIMIT);
}
/*******************************************************************************
diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_fvp_setup.c
similarity index 95%
rename from plat/fvp/bl31_plat_setup.c
rename to plat/fvp/bl31_fvp_setup.c
index d1e16bd52248a57bda3bf69e36fb726f836ec279..d867fbac9035d433eb96cdf10321c6b03b01ae4d 100644
--- a/plat/fvp/bl31_plat_setup.c
+++ b/plat/fvp/bl31_fvp_setup.c
@@ -95,9 +95,9 @@ entry_point_info_t *bl31_get_next_image_info(uint32_t type)
#if RESET_TO_BL31
if (type == NON_SECURE)
- plat_get_entry_point_info(NON_SECURE, &bl33_entrypoint_info);
+ fvp_get_entry_point_info(NON_SECURE, &bl33_entrypoint_info);
else
- plat_get_entry_point_info(SECURE, &bl32_entrypoint_info);
+ fvp_get_entry_point_info(SECURE, &bl32_entrypoint_info);
next_image_info = (type == NON_SECURE) ?
&bl33_entrypoint_info :
@@ -134,7 +134,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
console_init(PL011_UART0_BASE);
/* Initialize the platform config for future decision making */
- platform_config_setup();
+ fvp_config_setup();
#if RESET_TO_BL31
/* There are no parameters from BL2 if BL31 is a reset vector */
@@ -148,7 +148,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
* other platforms might have more programmable security devices
* present.
*/
- plat_security_setup();
+ fvp_security_setup();
#else
/* Check params passed from BL2 should not be NULL,
* We are not checking plat_params_from_bl2 as NULL as we are not
@@ -199,7 +199,7 @@ void bl31_platform_setup()
fvp_pwrc_setup();
/* Topologies are best known to the platform. */
- plat_setup_topology();
+ fvp_setup_topology();
}
/*******************************************************************************
@@ -210,14 +210,14 @@ void bl31_plat_arch_setup()
{
#if RESET_TO_BL31
fvp_cci_setup();
-#endif
- configure_mmu_el3(BL31_RO_BASE,
- (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
- BL31_RO_BASE,
- BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+#endif
+ fvp_configure_mmu_el3(BL31_RO_BASE,
+ (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
+ BL31_RO_BASE,
+ BL31_RO_LIMIT,
+ BL31_COHERENT_RAM_BASE,
+ BL31_COHERENT_RAM_LIMIT);
}
#if RESET_TO_BL31
@@ -225,7 +225,7 @@ void bl31_plat_arch_setup()
* Generate the entry point info for Non Secure and Secure images
* for transferring control from BL31
******************************************************************************/
-void plat_get_entry_point_info(unsigned long target_security,
+void fvp_get_entry_point_info(unsigned long target_security,
entry_point_info_t *target_entry_info)
{
if (target_security == NON_SECURE) {
diff --git a/plat/fvp/bl32_plat_setup.c b/plat/fvp/bl32_fvp_setup.c
similarity index 94%
rename from plat/fvp/bl32_plat_setup.c
rename to plat/fvp/bl32_fvp_setup.c
index b583349fcc6153ec3c1cf163e76a43ca0be09dc6..f8dc3c73dbab51a4691bade10de17822328e3e90 100644
--- a/plat/fvp/bl32_plat_setup.c
+++ b/plat/fvp/bl32_fvp_setup.c
@@ -75,7 +75,7 @@ void bl32_early_platform_setup(void)
console_init(PL011_UART1_BASE);
/* Initialize the platform config for future decision making */
- platform_config_setup();
+ fvp_config_setup();
}
/*******************************************************************************
@@ -92,10 +92,10 @@ void bl32_platform_setup()
******************************************************************************/
void bl32_plat_arch_setup()
{
- configure_mmu_el1(BL32_RO_BASE,
- (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
- BL32_RO_BASE,
- BL32_RO_LIMIT,
- BL32_COHERENT_RAM_BASE,
- BL32_COHERENT_RAM_LIMIT);
+ fvp_configure_mmu_el1(BL32_RO_BASE,
+ (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
+ BL32_RO_BASE,
+ BL32_RO_LIMIT,
+ BL32_COHERENT_RAM_BASE,
+ BL32_COHERENT_RAM_LIMIT);
}
diff --git a/plat/fvp/plat_gic.c b/plat/fvp/fvp_gic.c
similarity index 96%
rename from plat/fvp/plat_gic.c
rename to plat/fvp/fvp_gic.c
index 6b29723bb0ba20f69f6c7c944df235d8fab2aba1..fed2fca1f4cf4a767ea3abacc8323c1cdbc63e22 100644
--- a/plat/fvp/plat_gic.c
+++ b/plat/fvp/fvp_gic.c
@@ -277,8 +277,8 @@ void gic_setup(void)
{
unsigned int gicd_base, gicc_base;
- gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
gic_cpuif_setup(gicc_base);
gic_distif_setup(gicd_base);
@@ -298,7 +298,7 @@ void gic_setup(void)
******************************************************************************/
uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
{
- uint32_t gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ uint32_t gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
assert(type == INTR_TYPE_S_EL1 ||
type == INTR_TYPE_EL3 ||
@@ -328,7 +328,7 @@ uint32_t ic_get_pending_interrupt_type()
{
uint32_t id, gicc_base;
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
id = gicc_read_hppir(gicc_base);
/* Assume that all secure interrupts are S-EL1 interrupts */
@@ -350,7 +350,7 @@ uint32_t ic_get_pending_interrupt_id()
{
uint32_t id, gicc_base;
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
id = gicc_read_hppir(gicc_base);
if (id < 1022)
@@ -372,7 +372,7 @@ uint32_t ic_get_pending_interrupt_id()
******************************************************************************/
uint32_t ic_acknowledge_interrupt()
{
- return gicc_read_IAR(platform_get_cfgvar(CONFIG_GICC_ADDR));
+ return gicc_read_IAR(fvp_get_cfgvar(CONFIG_GICC_ADDR));
}
/*******************************************************************************
@@ -381,7 +381,7 @@ uint32_t ic_acknowledge_interrupt()
******************************************************************************/
void ic_end_of_interrupt(uint32_t id)
{
- gicc_write_EOIR(platform_get_cfgvar(CONFIG_GICC_ADDR), id);
+ gicc_write_EOIR(fvp_get_cfgvar(CONFIG_GICC_ADDR), id);
return;
}
@@ -394,7 +394,7 @@ uint32_t ic_get_interrupt_type(uint32_t id)
{
uint32_t group;
- group = gicd_get_igroupr(platform_get_cfgvar(CONFIG_GICD_ADDR), id);
+ group = gicd_get_igroupr(fvp_get_cfgvar(CONFIG_GICD_ADDR), id);
/* Assume that all secure interrupts are S-EL1 interrupts */
if (group == GRP0)
diff --git a/plat/fvp/plat_io_storage.c b/plat/fvp/fvp_io_storage.c
similarity index 99%
rename from plat/fvp/plat_io_storage.c
rename to plat/fvp/fvp_io_storage.c
index baa98ffe9e6bb4f5487218cf35a09a6ee9967df2..c32cca928969bc90da47357241c1f91855f39d9e 100644
--- a/plat/fvp/plat_io_storage.c
+++ b/plat/fvp/fvp_io_storage.c
@@ -168,7 +168,7 @@ static int open_semihosting(const uintptr_t spec)
return result;
}
-void io_setup (void)
+void fvp_io_setup (void)
{
int io_result = IO_FAIL;
diff --git a/plat/fvp/plat_pm.c b/plat/fvp/fvp_pm.c
similarity index 96%
rename from plat/fvp/plat_pm.c
rename to plat/fvp/fvp_pm.c
index ad4ce7939ee4e55301d6d5357769821f00e21209..d70264304abace76af4f338d95cf3fc2c4532f14 100644
--- a/plat/fvp/plat_pm.c
+++ b/plat/fvp/fvp_pm.c
@@ -139,7 +139,7 @@ int fvp_affinst_off(unsigned long mpidr,
* Disable coherency if this cluster is to be
* turned off
*/
- cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+ cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
if (cci_setup) {
cci_disable_coherency(mpidr);
}
@@ -160,7 +160,7 @@ int fvp_affinst_off(unsigned long mpidr,
* Take this cpu out of intra-cluster coherency if
* the FVP flavour supports the SMP bit.
*/
- cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
+ cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
if (cpu_setup) {
ectlr = read_cpuectlr();
ectlr &= ~CPUECTLR_SMP_BIT;
@@ -171,7 +171,7 @@ int fvp_affinst_off(unsigned long mpidr,
* Prevent interrupts from spuriously waking up
* this cpu
*/
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
gic_cpuif_deactivate(gicc_base);
/*
@@ -219,7 +219,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
* Disable coherency if this cluster is to be
* turned off
*/
- cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+ cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
if (cci_setup) {
cci_disable_coherency(mpidr);
}
@@ -239,7 +239,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
* Take this cpu out of intra-cluster coherency if
* the FVP flavour supports the SMP bit.
*/
- cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
+ cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
if (cpu_setup) {
ectlr = read_cpuectlr();
ectlr &= ~CPUECTLR_SMP_BIT;
@@ -257,7 +257,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
* Prevent interrupts from spuriously waking up
* this cpu
*/
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
gic_cpuif_deactivate(gicc_base);
/*
@@ -325,7 +325,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
* Turn on intra-cluster coherency if the FVP flavour supports
* it.
*/
- cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
+ cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
if (cpu_setup) {
ectlr = read_cpuectlr();
ectlr |= CPUECTLR_SMP_BIT;
@@ -345,8 +345,8 @@ int fvp_affinst_on_finish(unsigned long mpidr,
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
sizeof(unsigned long));
- gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
- gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+ gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR);
+ gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
/* Enable the gic cpu interface */
gic_cpuif_setup(gicc_base);
diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h
index 04e8b818256a134096da8485a640ec7c329da38c..2331bb7eb68306163103b5313be4e93aa3ebc2e5 100644
--- a/plat/fvp/fvp_private.h
+++ b/plat/fvp/fvp_private.h
@@ -63,23 +63,23 @@ struct meminfo;
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
-void configure_mmu_el1(unsigned long total_base,
- unsigned long total_size,
- unsigned long,
- unsigned long,
- unsigned long,
- unsigned long);
-void configure_mmu_el3(unsigned long total_base,
- unsigned long total_size,
- unsigned long,
- unsigned long,
- unsigned long,
- unsigned long);
-unsigned long platform_get_cfgvar(unsigned int);
-int platform_config_setup(void);
+void fvp_configure_mmu_el1(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long,
+ unsigned long,
+ unsigned long,
+ unsigned long);
+void fvp_configure_mmu_el3(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long,
+ unsigned long,
+ unsigned long,
+ unsigned long);
+unsigned long fvp_get_cfgvar(unsigned int);
+int fvp_config_setup(void);
#if RESET_TO_BL31
-void plat_get_entry_point_info(unsigned long target_security,
+void fvp_get_entry_point_info(unsigned long target_security,
struct entry_point_info *target_entry_info);
#endif
void fvp_cci_setup(void);
@@ -91,13 +91,13 @@ void gic_pcpu_distif_setup(unsigned int);
void gic_setup(void);
/* Declarations for fvp_topology.c */
-int plat_setup_topology(void);
+int fvp_setup_topology(void);
-/* Declarations for plat_io_storage.c */
-void io_setup(void);
+/* Declarations for fvp_io_storage.c */
+void fvp_io_setup(void);
-/* Declarations for plat_security.c */
-void plat_security_setup(void);
+/* Declarations for fvp_security.c */
+void fvp_security_setup(void);
/* Sets the entrypoint for BL32 */
void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep);
diff --git a/plat/fvp/plat_security.c b/plat/fvp/fvp_security.c
similarity index 98%
rename from plat/fvp/plat_security.c
rename to plat/fvp/fvp_security.c
index 976f75e98e070827202a6a493c4e05b424e90dcb..76c45413fbf3d662bc218d51e9ed86d5eceae2ea 100644
--- a/plat/fvp/plat_security.c
+++ b/plat/fvp/fvp_security.c
@@ -43,7 +43,7 @@
* TODO:
* Might want to enable interrupt on violations when supported?
*/
-void plat_security_setup(void)
+void fvp_security_setup(void)
{
tzc_instance_t controller;
@@ -56,7 +56,7 @@ void plat_security_setup(void)
* configurations, those would be configured here.
*/
- if (!platform_get_cfgvar(CONFIG_HAS_TZC))
+ if (!fvp_get_cfgvar(CONFIG_HAS_TZC))
return;
/*
diff --git a/plat/fvp/plat_topology.c b/plat/fvp/fvp_topology.c
similarity index 99%
rename from plat/fvp/plat_topology.c
rename to plat/fvp/fvp_topology.c
index f06b4f7470653b123b97f9af9c9ca9223ce10a09..cf21503773bf4964d221dc520a12304f640061ce 100644
--- a/plat/fvp/plat_topology.c
+++ b/plat/fvp/fvp_topology.c
@@ -190,7 +190,7 @@ int plat_get_max_afflvl()
* the FVP flavour its running on. We construct all the mpidrs we can handle
* and rely on the PWRC.PSYSR to flag absent cpus when their status is queried.
******************************************************************************/
-int plat_setup_topology()
+int fvp_setup_topology()
{
unsigned char aff0, aff1, aff_state, aff0_offset = 0;
unsigned long mpidr;
diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S
index 1fa50fd14ff1d5256cd7e200eb984e779bccf9d5..bdd402dc07a7e64fdba864fe94844c1b950c413e 100644
--- a/plat/fvp/include/plat_macros.S
+++ b/plat/fvp/include/plat_macros.S
@@ -44,7 +44,7 @@ gic_regs: .asciz "gic_iar", "gic_ctlr", ""
*/
.macro plat_print_gic_regs
mov x0, #CONFIG_GICC_ADDR
- bl platform_get_cfgvar
+ bl fvp_get_cfgvar
/* gic base address is now in x0 */
ldr w1, [x0, #GICC_IAR]
ldr w2, [x0, #GICD_CTLR]
diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk
index f1d6f878d6e9b6507a256a585cdbb7382d88fa78..105cdfa4a8093fcd7358414d69a0c032ee2bfaf5 100644
--- a/plat/fvp/platform.mk
+++ b/plat/fvp/platform.mk
@@ -51,40 +51,40 @@ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011.c \
drivers/io/io_memmap.c \
drivers/io/io_semihosting.c \
lib/mmio.c \
- lib/aarch64/sysreg_helpers.S \
+ lib/aarch64/sysreg_helpers.S \
lib/aarch64/xlat_tables.c \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
- plat/fvp/plat_io_storage.c
+ plat/fvp/fvp_io_storage.c
BL1_SOURCES += drivers/arm/cci400/cci400.c \
plat/common/aarch64/platform_up_stack.S \
- plat/fvp/bl1_plat_setup.c \
- plat/fvp/aarch64/plat_common.c \
- plat/fvp/aarch64/plat_helpers.S
+ plat/fvp/bl1_fvp_setup.c \
+ plat/fvp/aarch64/fvp_common.c \
+ plat/fvp/aarch64/fvp_helpers.S
BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
plat/common/aarch64/platform_up_stack.S \
- plat/fvp/bl2_plat_setup.c \
- plat/fvp/plat_security.c \
- plat/fvp/aarch64/plat_common.c
+ plat/fvp/bl2_fvp_setup.c \
+ plat/fvp/fvp_security.c \
+ plat/fvp/aarch64/fvp_common.c
BL31_SOURCES += drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
drivers/arm/gic/aarch64/gic_v3_sysregs.S \
drivers/arm/cci400/cci400.c \
plat/common/aarch64/platform_mp_stack.S \
- plat/fvp/bl31_plat_setup.c \
- plat/fvp/plat_gic.c \
- plat/fvp/plat_pm.c \
- plat/fvp/plat_topology.c \
- plat/fvp/aarch64/plat_helpers.S \
- plat/fvp/aarch64/plat_common.c \
+ plat/fvp/bl31_fvp_setup.c \
+ plat/fvp/fvp_gic.c \
+ plat/fvp/fvp_pm.c \
+ plat/fvp/fvp_topology.c \
+ plat/fvp/aarch64/fvp_helpers.S \
+ plat/fvp/aarch64/fvp_common.c \
plat/fvp/drivers/pwrc/fvp_pwrc.c
ifeq (${RESET_TO_BL31}, 1)
- BL31_SOURCES += drivers/arm/tzc400/tzc400.c \
- plat/fvp/plat_security.c
+BL31_SOURCES += drivers/arm/tzc400/tzc400.c \
+ plat/fvp/fvp_security.c
endif
# Flag used by the FVP port to determine the version of ARM GIC architecture