diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 2b578d5cf2f51d349138ae5d85a1c70220ef50c8..0037b49e3a81bf539e45dc0088be6b41b6a69320 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -156,16 +156,21 @@
  * Tegra scratch registers constants
  ******************************************************************************/
 #define TEGRA_SCRATCH_BASE		U(0x0C390000)
-#define  SECURE_SCRATCH_RSV1_LO		U(0x06C)
-#define  SECURE_SCRATCH_RSV1_HI		U(0x070)
-#define  SECURE_SCRATCH_RSV6		U(0x094)
-#define  SECURE_SCRATCH_RSV11_LO	U(0x0BC)
-#define  SECURE_SCRATCH_RSV11_HI	U(0x0C0)
-#define  SECURE_SCRATCH_RSV53_LO	U(0x20C)
-#define  SECURE_SCRATCH_RSV53_HI	U(0x210)
-#define  SECURE_SCRATCH_RSV54_HI	U(0x218)
-#define  SECURE_SCRATCH_RSV55_LO	U(0x21C)
-#define  SECURE_SCRATCH_RSV55_HI	U(0x220)
+#define  SECURE_SCRATCH_RSV44_LO	U(0x1C4)
+#define  SECURE_SCRATCH_RSV44_HI	U(0x1C8)
+#define  SECURE_SCRATCH_RSV97		U(0x36C)
+#define  SECURE_SCRATCH_RSV99_LO	U(0x37C)
+#define  SECURE_SCRATCH_RSV99_HI	U(0x380)
+#define  SECURE_SCRATCH_RSV109_LO	U(0x3CC)
+#define  SECURE_SCRATCH_RSV109_HI	U(0x3D0)
+
+#define SCRATCH_BL31_PARAMS_ADDR	SECURE_SCRATCH_RSV44_LO
+#define SCRATCH_BL31_PLAT_PARAMS_ADDR	SECURE_SCRATCH_RSV44_HI
+#define SCRATCH_SECURE_BOOTP_FCFG	SECURE_SCRATCH_RSV97
+#define SCRATCH_SMMU_TABLE_ADDR_LO	SECURE_SCRATCH_RSV99_LO
+#define SCRATCH_SMMU_TABLE_ADDR_HI	SECURE_SCRATCH_RSV99_HI
+#define SCRATCH_RESET_VECTOR_LO		SECURE_SCRATCH_RSV109_LO
+#define SCRATCH_RESET_VECTOR_HI		SECURE_SCRATCH_RSV109_HI
 
 /*******************************************************************************
  * Tegra Memory Mapped Control Register Access Bus constants
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
index 0bacc86c0244c238d6b5c0e647e4c876c876f6d5..0a6345dcc07953cb03ddb3d83cfb516ef5d6a655 100644
--- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -639,4 +639,4 @@ static tegra_mc_settings_t tegra194_mc_settings = {
 tegra_mc_settings_t *tegra_get_mc_settings(void)
 {
 	return &tegra194_mc_settings;
-}
+}
\ No newline at end of file
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index 47a502a118d542d37fdf03e7034dd3830d545017..0932061d01958b2b23ee5a121d5093e24c922916 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -144,7 +144,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 
 		/* save 'Secure Boot' Processor Feature Config Register */
 		val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
-		mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val);
+		mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
 
 #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
 		/* save SMMU context */
diff --git a/plat/nvidia/tegra/soc/t194/plat_secondary.c b/plat/nvidia/tegra/soc/t194/plat_secondary.c
index c54ca28b8de04553e5fb6094f0fe87a6182c2474..0947c31b3df3d83b764d64aed7d5de2fd5c4fa87 100644
--- a/plat/nvidia/tegra/soc/t194/plat_secondary.c
+++ b/plat/nvidia/tegra/soc/t194/plat_secondary.c
@@ -55,8 +55,8 @@ void plat_secondary_setup(void)
 	mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
 
 	/* save reset vector to be used during SYSTEM_SUSPEND exit */
-	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_LO,
+	mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
 			addr_low);
-	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI,
+	mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
 			addr_high);
 }
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index 08bd71073cf8402aa2080c4d22b8945bebbbc914..195ee9f9ddcb29b693bf46bb0e44de0fcd038e5e 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -269,7 +269,7 @@ struct tegra_bl31_params *plat_get_bl31_params(void)
 {
 	uint32_t val;
 
-	val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
+	val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
 
 	return (struct tegra_bl31_params *)(uintptr_t)val;
 }
@@ -281,7 +281,7 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
 {
 	uint32_t val;
 
-	val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI);
+	val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
 
 	return (plat_params_from_bl2_t *)(uintptr_t)val;
 }
diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c
index 8913a0117a65a675ef1615b081ac90235dfee6c3..19917a9ce33e9af13b6ec0fed3b993f6148dba01 100644
--- a/plat/nvidia/tegra/soc/t194/plat_smmu.c
+++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c
@@ -436,4 +436,4 @@ uint32_t plat_get_num_smmu_devices(void)
 	}
 
 	return ret_num;
-}
+}
\ No newline at end of file