Merge "allwinner: Fix incorrect ARISC code patch offset check" into integration

plat/allwinner/common/include/sunxi_private.h

 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -20,7 +20,6 @@ void sunxi_security_setup(void);
 uint16_t sunxi_read_soc_id(void);
 void sunxi_set_gpio_out(char port, int pin, bool level_high);
 int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb);
-void sunxi_execute_arisc_code(uint32_t *code, size_t size,
-			      int patch_offset, uint16_t param);
+void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param);
 
 #endif /* SUNXI_PRIVATE_H */

plat/allwinner/common/sunxi_common.c

 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -172,8 +172,7 @@ DEFINE_BAKERY_LOCK(arisc_lock);
  * in SRAM, put the address of that into the reset vector and release the
  * arisc reset line. The SCP will execute that code and pull the line up again.
  */
-void sunxi_execute_arisc_code(uint32_t *code, size_t size,
-			      int patch_offset, uint16_t param)
+void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param)
 {
 	uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE - 0x4000 + 0x100;
 
@@ -187,8 +186,7 @@ void sunxi_execute_arisc_code(uint32_t *code, size_t size,
 	} while (1);
 
 	/* Patch up the code to feed in an input parameter. */
-	if (patch_offset >= 0 && patch_offset <= (size - 4))
-		code[patch_offset] = (code[patch_offset] & ~0xffff) | param;
+	code[0] = (code[0] & ~0xffff) | param;
 	clean_dcache_range((uintptr_t)code, size);
 
 	/*

plat/allwinner/common/sunxi_cpu_ops.c

@@ -78,7 +78,7 @@ void sunxi_cpu_off(u_register_t mpidr)
 	 * patched into the first instruction.
 	 */
 	sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off),
-				 0, BIT_32(core));
+				 BIT_32(core));
 }
 
 void sunxi_cpu_on(u_register_t mpidr)