diff --git a/plat/hisilicon/hikey/hikey_pm.c b/plat/hisilicon/hikey/hikey_pm.c
index c796e8a5466731f862debc97bfed203330077759..d4dd683e0121cec03b39ca8ea418bd6f61900020 100644
--- a/plat/hisilicon/hikey/hikey_pm.c
+++ b/plat/hisilicon/hikey/hikey_pm.c
@@ -40,7 +40,9 @@ static int hikey_pwr_domain_on(u_register_t mpidr)
 		hisi_ipc_cluster_on(cpu, cluster);
 
 	hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint);
+	hisi_pwrc_enable_debug(cpu, cluster);
 	hisi_ipc_cpu_on(cpu, cluster);
+
 	return 0;
 }
 
diff --git a/plat/hisilicon/hikey/hisi_pwrc.c b/plat/hisilicon/hikey/hisi_pwrc.c
index 8e9d1fc44dfe6a63f851223d986284d0f96d384a..b635fb16faec07017b398a6909ebbe262f540acb 100644
--- a/plat/hisilicon/hikey/hisi_pwrc.c
+++ b/plat/hisilicon/hikey/hisi_pwrc.c
@@ -51,6 +51,21 @@ void hisi_pwrc_set_cluster_wfi(unsigned int cluster)
 	}
 }
 
+void hisi_pwrc_enable_debug(unsigned int core, unsigned int cluster)
+{
+	unsigned int val, enable;
+
+	enable = 1U << (core + PDBGUP_CLUSTER1_SHIFT * cluster);
+
+	/* Enable debug module */
+	val = mmio_read_32(ACPU_SC_PDBGUP_MBIST);
+	mmio_write_32(ACPU_SC_PDBGUP_MBIST, val | enable);
+	do {
+		/* RAW barrier */
+		val = mmio_read_32(ACPU_SC_PDBGUP_MBIST);
+	} while (!(val & enable));
+}
+
 int hisi_pwrc_setup(void)
 {
 	unsigned int reg, sec_entrypoint;
diff --git a/plat/hisilicon/hikey/include/hisi_pwrc.h b/plat/hisilicon/hikey/include/hisi_pwrc.h
index 3a87e72bee36f2b5161a90a490f5819ee9ca7f94..cffe70e3b31e27906afb9572814fe744cbbc65a6 100644
--- a/plat/hisilicon/hikey/include/hisi_pwrc.h
+++ b/plat/hisilicon/hikey/include/hisi_pwrc.h
@@ -13,6 +13,8 @@ void hisi_pwrc_set_cluster_wfi(unsigned int id);
 void hisi_pwrc_set_core_bx_addr(unsigned int core,
 				unsigned int cluster,
 				uintptr_t entry_point);
+void hisi_pwrc_enable_debug(unsigned int core,
+			    unsigned int cluster);
 int hisi_pwrc_setup(void);
 
 #endif /*__ASSEMBLY__*/