Skip to content

GitLab

Commit 2049b6f9 authored by Sandrine Bailleux's avatar Sandrine Bailleux Committed by TrustedFirmware Code Review
Browse files

Merge changes from topic "add-versal-soc-support" into integration 

* changes:
  zynqmp: pm: Add LPD WDT clock to the pm_clock structure
  zynqmp: pm: Fix clock models and IDs of GEM-related clocks
  zynqmp: pm: Rename FPD WDT clock ID
  plat: xilinx: zynqmp: Correct syscnt freq for QEMU
  arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
  arm64: zynqmp: Add id for new RFSoC device ZU39DR
parents f1f8ea20 b3ce966a
Show whitespace changes
Inline Side-by-side
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
View file @ 2049b6f9
...@@ -189,6 +189,18 @@ static const struct { ...@@ -189,6 +189,18 @@ static const struct {
.id = 0x65, .id = 0x65,
.name = "25DR", .name = "25DR",
}, },
{
.id = 0x66,
.name = "39DR",
},
{
.id = 0x7b,
.name = "48DR",
},
{
.id = 0x7e,
.name = "49DR",
},
}; };
#define ZYNQMP_PL_STATUS_BIT 9 #define ZYNQMP_PL_STATUS_BIT 9
...@@ -338,7 +350,7 @@ unsigned int plat_get_syscnt_freq2(void) ...@@ -338,7 +350,7 @@ unsigned int plat_get_syscnt_freq2(void)
unsigned int ver = zynqmp_get_silicon_ver(); unsigned int ver = zynqmp_get_silicon_ver();
if (ver == ZYNQMP_CSU_VERSION_QEMU) if (ver == ZYNQMP_CSU_VERSION_QEMU)
return 50000000; return 65000000;
else else
return mmio_read_32(IOU_SCNTRS_BASEFREQ); return mmio_read_32(IOU_SCNTRS_BASEFREQ);
} }
plat/xilinx/zynqmp/include/zynqmp_def.h
View file @ 2049b6f9
/* /*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -330,6 +330,7 @@ ...@@ -330,6 +330,7 @@
#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) #define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) #define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) #define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100)
#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
/* Global general storage register base address */ /* Global general storage register base address */
#define GGS_BASEADDR (0xFFD80030U) #define GGS_BASEADDR (0xFFD80030U)
......
plat/xilinx/zynqmp/pm_service/pm_api_clock.c
View file @ 2049b6f9
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -562,13 +562,13 @@ static struct pm_clock_node gpu_pp1_nodes[] = { ...@@ -562,13 +562,13 @@ static struct pm_clock_node gpu_pp1_nodes[] = {
}, },
}; };
static struct pm_clock_node gem_nodes[] = { static struct pm_clock_node gem_ref_ungated_nodes[] = {
GENERIC_MUX, GENERIC_MUX,
{ {
.type = TYPE_DIV1, .type = TYPE_DIV1,
.offset = 8, .offset = 8,
.width = 6, .width = 6,
.clkflags = CLK_IS_BASIC, .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
.mult = NA_MULT, .mult = NA_MULT,
.div = NA_DIV, .div = NA_DIV,
...@@ -577,77 +577,73 @@ static struct pm_clock_node gem_nodes[] = { ...@@ -577,77 +577,73 @@ static struct pm_clock_node gem_nodes[] = {
.type = TYPE_DIV2, .type = TYPE_DIV2,
.offset = 16, .offset = 16,
.width = 6, .width = 6,
.clkflags = CLK_IS_BASIC, .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
.mult = NA_MULT, .mult = NA_MULT,
.div = NA_DIV, .div = NA_DIV,
}, },
{
.type = TYPE_GATE,
.offset = 25,
.width = PERIPH_GATE_WIDTH,
.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
},
}; };
static struct pm_clock_node gem0_tx_nodes[] = { static struct pm_clock_node gem0_ref_nodes[] = {
{ {
.type = TYPE_MUX, .type = TYPE_MUX,
.offset = 1, .offset = 1,
.width = 1, .width = 1,
.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC, .clkflags = CLK_SET_RATE_PARENT |
.typeflags = NA_TYPE_FLAGS, CLK_SET_RATE_NO_REPARENT |
.mult = NA_MULT, CLK_IS_BASIC,
.div = NA_DIV,
},
{
.type = TYPE_GATE,
.offset = 26,
.width = PERIPH_GATE_WIDTH,
.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS, .typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT, .mult = NA_MULT,
.div = NA_DIV, .div = NA_DIV,
}, },
}; };
static struct pm_clock_node gem1_tx_nodes[] = { static struct pm_clock_node gem1_ref_nodes[] = {
{ {
.type = TYPE_MUX, .type = TYPE_MUX,
.offset = 6, .offset = 6,
.width = 1, .width = 1,
.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC, .clkflags = CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS, .typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT, .mult = NA_MULT,
.div = NA_DIV, .div = NA_DIV,
}, },
};
static struct pm_clock_node gem2_ref_nodes[] = {
{ {
.type = TYPE_GATE, .type = TYPE_MUX,
.offset = 26, .offset = 11,
.width = PERIPH_GATE_WIDTH, .width = 1,
.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC, .clkflags = CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS, .typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT, .mult = NA_MULT,
.div = NA_DIV, .div = NA_DIV,
}, },
}; };
static struct pm_clock_node gem2_tx_nodes[] = { static struct pm_clock_node gem3_ref_nodes[] = {
{ {
.type = TYPE_MUX, .type = TYPE_MUX,
.offset = 11, .offset = 16,
.width = 1, .width = 1,
.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC, .clkflags = CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS, .typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT, .mult = NA_MULT,
.div = NA_DIV, .div = NA_DIV,
}, },
};
static struct pm_clock_node gem_tx_nodes[] = {
{ {
.type = TYPE_GATE, .type = TYPE_GATE,
.offset = 26, .offset = 25,
.width = PERIPH_GATE_WIDTH, .width = PERIPH_GATE_WIDTH,
.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC, .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS, .typeflags = NA_TYPE_FLAGS,
...@@ -656,21 +652,12 @@ static struct pm_clock_node gem2_tx_nodes[] = { ...@@ -656,21 +652,12 @@ static struct pm_clock_node gem2_tx_nodes[] = {
}, },
}; };
static struct pm_clock_node gem3_tx_nodes[] = { static struct pm_clock_node gem_rx_nodes[] = {
{
.type = TYPE_MUX,
.offset = 16,
.width = 1,
.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
},
{ {
.type = TYPE_GATE, .type = TYPE_GATE,
.offset = 26, .offset = 26,
.width = PERIPH_GATE_WIDTH, .width = PERIPH_GATE_WIDTH,
.clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC, .clkflags = CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS, .typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT, .mult = NA_MULT,
.div = NA_DIV, .div = NA_DIV,
...@@ -1442,8 +1429,8 @@ static struct pm_clock clocks[] = { ...@@ -1442,8 +1429,8 @@ static struct pm_clock clocks[] = {
.nodes = &generic_mux_div_unused_gate_nodes, .nodes = &generic_mux_div_unused_gate_nodes,
.num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes), .num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
}, },
[CLK_GEM0_REF] = { [CLK_GEM0_REF_UNGATED] = {
.name = "gem0_ref", .name = "gem0_ref_ung",
.control_reg = CRL_APB_GEM0_REF_CTRL, .control_reg = CRL_APB_GEM0_REF_CTRL,
.status_reg = 0, .status_reg = 0,
.parents = &((int32_t []) { .parents = &((int32_t []) {
...@@ -1453,11 +1440,11 @@ static struct pm_clock clocks[] = { ...@@ -1453,11 +1440,11 @@ static struct pm_clock clocks[] = {
CLK_DPLL_TO_LPD, CLK_DPLL_TO_LPD,
CLK_NA_PARENT CLK_NA_PARENT
}), }),
.nodes = &gem_nodes, .nodes = &gem_ref_ungated_nodes,
.num_nodes = ARRAY_SIZE(gem_nodes), .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes),
}, },
[CLK_GEM1_REF] = { [CLK_GEM1_REF_UNGATED] = {
.name = "gem1_ref", .name = "gem1_ref_ung",
.control_reg = CRL_APB_GEM1_REF_CTRL, .control_reg = CRL_APB_GEM1_REF_CTRL,
.status_reg = 0, .status_reg = 0,
.parents = &((int32_t []) { .parents = &((int32_t []) {
...@@ -1467,11 +1454,11 @@ static struct pm_clock clocks[] = { ...@@ -1467,11 +1454,11 @@ static struct pm_clock clocks[] = {
CLK_DPLL_TO_LPD, CLK_DPLL_TO_LPD,
CLK_NA_PARENT CLK_NA_PARENT
}), }),
.nodes = &gem_nodes, .nodes = &gem_ref_ungated_nodes,
.num_nodes = ARRAY_SIZE(gem_nodes), .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes),
}, },
[CLK_GEM2_REF] = { [CLK_GEM2_REF_UNGATED] = {
.name = "gem2_ref", .name = "gem2_ref_ung",
.control_reg = CRL_APB_GEM2_REF_CTRL, .control_reg = CRL_APB_GEM2_REF_CTRL,
.status_reg = 0, .status_reg = 0,
.parents = &((int32_t []) { .parents = &((int32_t []) {
...@@ -1481,11 +1468,11 @@ static struct pm_clock clocks[] = { ...@@ -1481,11 +1468,11 @@ static struct pm_clock clocks[] = {
CLK_DPLL_TO_LPD, CLK_DPLL_TO_LPD,
CLK_NA_PARENT CLK_NA_PARENT
}), }),
.nodes = &gem_nodes, .nodes = &gem_ref_ungated_nodes,
.num_nodes = ARRAY_SIZE(gem_nodes), .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes),
}, },
[CLK_GEM3_REF] = { [CLK_GEM3_REF_UNGATED] = {
.name = "gem3_ref", .name = "gem3_ref_ung",
.control_reg = CRL_APB_GEM3_REF_CTRL, .control_reg = CRL_APB_GEM3_REF_CTRL,
.status_reg = 0, .status_reg = 0,
.parents = &((int32_t []) { .parents = &((int32_t []) {
...@@ -1495,8 +1482,60 @@ static struct pm_clock clocks[] = { ...@@ -1495,8 +1482,60 @@ static struct pm_clock clocks[] = {
CLK_DPLL_TO_LPD, CLK_DPLL_TO_LPD,
CLK_NA_PARENT CLK_NA_PARENT
}), }),
.nodes = &gem_nodes, .nodes = &gem_ref_ungated_nodes,
.num_nodes = ARRAY_SIZE(gem_nodes), .num_nodes = ARRAY_SIZE(gem_ref_ungated_nodes),
},
[CLK_GEM0_REF] = {
.name = "gem0_ref",
.control_reg = IOU_SLCR_GEM_CLK_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_GEM0_REF_UNGATED |
(PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
EXT_CLK_GEM0_TX_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
.nodes = &gem0_ref_nodes,
.num_nodes = ARRAY_SIZE(gem0_ref_nodes),
},
[CLK_GEM1_REF] = {
.name = "gem1_ref",
.control_reg = IOU_SLCR_GEM_CLK_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_GEM1_REF_UNGATED |
(PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
EXT_CLK_GEM1_TX_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
.nodes = &gem1_ref_nodes,
.num_nodes = ARRAY_SIZE(gem1_ref_nodes),
},
[CLK_GEM2_REF] = {
.name = "gem2_ref",
.control_reg = IOU_SLCR_GEM_CLK_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_GEM2_REF_UNGATED |
(PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
EXT_CLK_GEM2_TX_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
.nodes = &gem2_ref_nodes,
.num_nodes = ARRAY_SIZE(gem2_ref_nodes),
},
[CLK_GEM3_REF] = {
.name = "gem3_ref",
.control_reg = IOU_SLCR_GEM_CLK_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_GEM3_REF_UNGATED |
(PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN),
EXT_CLK_GEM3_TX_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
.nodes = &gem3_ref_nodes,
.num_nodes = ARRAY_SIZE(gem3_ref_nodes),
}, },
[CLK_USB0_BUS_REF] = { [CLK_USB0_BUS_REF] = {
.name = "usb0_bus_ref", .name = "usb0_bus_ref",
...@@ -1960,69 +1999,93 @@ static struct pm_clock clocks[] = { ...@@ -1960,69 +1999,93 @@ static struct pm_clock clocks[] = {
.nodes = &generic_domain_crossing_nodes, .nodes = &generic_domain_crossing_nodes,
.num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes), .num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes),
}, },
/*
* This clock control requires different registers for mux and gate.
* Use control and status registers for the same.
*/
[CLK_GEM0_TX] = { [CLK_GEM0_TX] = {
.name = "gem0_tx", .name = "gem0_tx",
.control_reg = IOU_SLCR_GEM_CLK_CTRL, .control_reg = CRL_APB_GEM0_REF_CTRL,
.status_reg = CRL_APB_GEM0_REF_CTRL, .status_reg = 0,
.parents = &((int32_t []) { .parents = &((int32_t []) {
CLK_GEM0_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), CLK_GEM0_REF,
EXT_CLK_GEM0_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT CLK_NA_PARENT
}), }),
.nodes = &gem0_tx_nodes, .nodes = &gem_tx_nodes,
.num_nodes = ARRAY_SIZE(gem0_tx_nodes), .num_nodes = ARRAY_SIZE(gem_tx_nodes),
}, },
/*
* This clock control requires different registers for mux and gate.
* Use control and status registers for the same.
*/
[CLK_GEM1_TX] = { [CLK_GEM1_TX] = {
.name = "gem1_tx", .name = "gem1_tx",
.control_reg = IOU_SLCR_GEM_CLK_CTRL, .control_reg = CRL_APB_GEM1_REF_CTRL,
.status_reg = CRL_APB_GEM1_REF_CTRL, .status_reg = 0,
.parents = &((int32_t []) { .parents = &((int32_t []) {
CLK_GEM1_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), CLK_GEM1_REF,
EXT_CLK_GEM1_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT CLK_NA_PARENT
}), }),
.nodes = &gem1_tx_nodes, .nodes = &gem_tx_nodes,
.num_nodes = ARRAY_SIZE(gem1_tx_nodes), .num_nodes = ARRAY_SIZE(gem_tx_nodes),
}, },
/*
* This clock control requires different registers for mux and gate.
* Use control and status registers for the same.
*/
[CLK_GEM2_TX] = { [CLK_GEM2_TX] = {
.name = "gem2_tx", .name = "gem2_tx",
.control_reg = IOU_SLCR_GEM_CLK_CTRL, .control_reg = CRL_APB_GEM2_REF_CTRL,
.status_reg = CRL_APB_GEM2_REF_CTRL, .status_reg = 0,
.parents = &((int32_t []) { .parents = &((int32_t []) {
CLK_GEM2_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), CLK_GEM2_REF,
EXT_CLK_GEM2_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT CLK_NA_PARENT
}), }),
.nodes = &gem2_tx_nodes, .nodes = &gem_tx_nodes,
.num_nodes = ARRAY_SIZE(gem2_tx_nodes), .num_nodes = ARRAY_SIZE(gem_tx_nodes),
}, },
/*
* This clock control requires different registers for mux and gate.
* Use control and status registers for the same.
*/
[CLK_GEM3_TX] = { [CLK_GEM3_TX] = {
.name = "gem3_tx", .name = "gem3_tx",
.control_reg = IOU_SLCR_GEM_CLK_CTRL, .control_reg = CRL_APB_GEM3_REF_CTRL,
.status_reg = CRL_APB_GEM3_REF_CTRL, .status_reg = 0,
.parents = &((int32_t []) {
CLK_GEM3_REF,
CLK_NA_PARENT
}),
.nodes = &gem_tx_nodes,
.num_nodes = ARRAY_SIZE(gem_tx_nodes),
},
[CLK_GEM0_RX] = {
.name = "gem0_rx",
.control_reg = CRL_APB_GEM0_REF_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
EXT_CLK_GEM0_RX_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
.nodes = &gem_rx_nodes,
.num_nodes = ARRAY_SIZE(gem_rx_nodes),
},
[CLK_GEM1_RX] = {
.name = "gem1_rx",
.control_reg = CRL_APB_GEM1_REF_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
EXT_CLK_GEM1_RX_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
.nodes = &gem_rx_nodes,
.num_nodes = ARRAY_SIZE(gem_rx_nodes),
},
[CLK_GEM2_RX] = {
.name = "gem2_rx",
.control_reg = CRL_APB_GEM2_REF_CTRL,
.status_reg = 0,
.parents = &((int32_t []) { .parents = &((int32_t []) {
CLK_GEM3_REF | (PARENT_CLK_NODE3 << CLK_PARENTS_ID_LEN), EXT_CLK_GEM2_RX_EMIO | CLK_EXTERNAL_PARENT,
EXT_CLK_GEM3_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT CLK_NA_PARENT
}), }),
.nodes = &gem3_tx_nodes, .nodes = &gem_rx_nodes,
.num_nodes = ARRAY_SIZE(gem3_tx_nodes), .num_nodes = ARRAY_SIZE(gem_rx_nodes),
},
[CLK_GEM3_RX] = {
.name = "gem3_rx",
.control_reg = CRL_APB_GEM3_REF_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
EXT_CLK_GEM3_RX_EMIO | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
.nodes = &gem_rx_nodes,
.num_nodes = ARRAY_SIZE(gem_rx_nodes),
}, },
[CLK_ACPU_HALF] = { [CLK_ACPU_HALF] = {
.name = "acpu_half", .name = "acpu_half",
...@@ -2035,8 +2098,8 @@ static struct pm_clock clocks[] = { ...@@ -2035,8 +2098,8 @@ static struct pm_clock clocks[] = {
.nodes = &acpu_half_nodes, .nodes = &acpu_half_nodes,
.num_nodes = ARRAY_SIZE(acpu_half_nodes), .num_nodes = ARRAY_SIZE(acpu_half_nodes),
}, },
[CLK_WDT] = { [CLK_FPD_WDT] = {
.name = "wdt", .name = "fpd_wdt",
.control_reg = FPD_SLCR_WDT_CLK_SEL, .control_reg = FPD_SLCR_WDT_CLK_SEL,
.status_reg = 0, .status_reg = 0,
.parents = &((int32_t []) { .parents = &((int32_t []) {
...@@ -2135,6 +2198,18 @@ static struct pm_clock clocks[] = { ...@@ -2135,6 +2198,18 @@ static struct pm_clock clocks[] = {
.nodes = &can1_nodes, .nodes = &can1_nodes,
.num_nodes = ARRAY_SIZE(can1_nodes), .num_nodes = ARRAY_SIZE(can1_nodes),
}, },
[CLK_LPD_WDT] = {
.name = "lpd_wdt",
.control_reg = IOU_SLCR_WDT_CLK_SEL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_LPD_LSBUS,
EXT_CLK_SWDT1 | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
.nodes = &wdt_nodes,
.num_nodes = ARRAY_SIZE(wdt_nodes),
},
}; };
static struct pm_ext_clock ext_clocks[] = { static struct pm_ext_clock ext_clocks[] = {
...@@ -2159,17 +2234,29 @@ static struct pm_ext_clock ext_clocks[] = { ...@@ -2159,17 +2234,29 @@ static struct pm_ext_clock ext_clocks[] = {
[EXT_CLK_INDEX(EXT_CLK_SWDT1)] = { [EXT_CLK_INDEX(EXT_CLK_SWDT1)] = {
.name = "swdt1_ext_clk", .name = "swdt1_ext_clk",
}, },
[EXT_CLK_INDEX(EXT_CLK_GEM0_EMIO)] = { [EXT_CLK_INDEX(EXT_CLK_GEM0_TX_EMIO)] = {
.name = "gem0_emio_clk", .name = "gem0_tx_ext",
},
[EXT_CLK_INDEX(EXT_CLK_GEM1_TX_EMIO)] = {
.name = "gem1_tx_ext",
}, },
[EXT_CLK_INDEX(EXT_CLK_GEM1_EMIO)] = { [EXT_CLK_INDEX(EXT_CLK_GEM2_TX_EMIO)] = {
.name = "gem1_emio_clk", .name = "gem2_tx_ext",
}, },
[EXT_CLK_INDEX(EXT_CLK_GEM2_EMIO)] = { [EXT_CLK_INDEX(EXT_CLK_GEM3_TX_EMIO)] = {
.name = "gem2_emio_clk", .name = "gem3_tx_ext",
}, },
[EXT_CLK_INDEX(EXT_CLK_GEM3_EMIO)] = { [EXT_CLK_INDEX(EXT_CLK_GEM0_RX_EMIO)] = {
.name = "gem3_emio_clk", .name = "gem0_rx_ext",
},
[EXT_CLK_INDEX(EXT_CLK_GEM1_RX_EMIO)] = {
.name = "gem1_rx_ext",
},
[EXT_CLK_INDEX(EXT_CLK_GEM2_RX_EMIO)] = {
.name = "gem2_rx_ext",
},
[EXT_CLK_INDEX(EXT_CLK_GEM3_RX_EMIO)] = {
.name = "gem3_rx_ext",
}, },
[EXT_CLK_INDEX(EXT_CLK_MIO50_OR_MIO51)] = { [EXT_CLK_INDEX(EXT_CLK_MIO50_OR_MIO51)] = {
.name = "mio_clk_50_51", .name = "mio_clk_50_51",
...@@ -2268,7 +2355,6 @@ static uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB, ...@@ -2268,7 +2355,6 @@ static uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB,
CLK_TOPSW_LSBUS, CLK_TOPSW_LSBUS,
CLK_GTGREF0_REF, CLK_GTGREF0_REF,
CLK_LPD_SWITCH, CLK_LPD_SWITCH,
CLK_LPD_LSBUS,
CLK_CPU_R5, CLK_CPU_R5,
CLK_CPU_R5_CORE, CLK_CPU_R5_CORE,
CLK_CSU_SPB, CLK_CSU_SPB,
......
plat/xilinx/zynqmp/pm_service/pm_api_clock.h
View file @ 2049b6f9
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -102,14 +102,14 @@ enum clock_id { ...@@ -102,14 +102,14 @@ enum clock_id {
CLK_IOU_SWITCH, CLK_IOU_SWITCH,
CLK_GEM_TSU_REF, CLK_GEM_TSU_REF,
CLK_GEM_TSU, CLK_GEM_TSU,
CLK_GEM0_REF,
CLK_GEM1_REF,
CLK_GEM2_REF,
CLK_GEM3_REF,
CLK_GEM0_TX, CLK_GEM0_TX,
CLK_GEM1_TX, CLK_GEM1_TX,
CLK_GEM2_TX, CLK_GEM2_TX,
CLK_GEM3_TX, CLK_GEM3_TX,
CLK_GEM0_RX,
CLK_GEM1_RX,
CLK_GEM2_RX,
CLK_GEM3_RX,
CLK_QSPI_REF, CLK_QSPI_REF,
CLK_SDIO0_REF, CLK_SDIO0_REF,
CLK_SDIO1_REF, CLK_SDIO1_REF,
...@@ -132,7 +132,7 @@ enum clock_id { ...@@ -132,7 +132,7 @@ enum clock_id {
CLK_PL1_REF, CLK_PL1_REF,
CLK_PL2_REF, CLK_PL2_REF,
CLK_PL3_REF, CLK_PL3_REF,
CLK_WDT, CLK_FPD_WDT,
CLK_IOPLL_INT, CLK_IOPLL_INT,
CLK_IOPLL_PRE_SRC, CLK_IOPLL_PRE_SRC,
CLK_IOPLL_HALF, CLK_IOPLL_HALF,
...@@ -161,6 +161,15 @@ enum clock_id { ...@@ -161,6 +161,15 @@ enum clock_id {
CLK_CAN0_MIO, CLK_CAN0_MIO,
CLK_CAN1_MIO, CLK_CAN1_MIO,
CLK_ACPU_FULL, CLK_ACPU_FULL,
CLK_GEM0_REF,
CLK_GEM1_REF,
CLK_GEM2_REF,
CLK_GEM3_REF,
CLK_GEM0_REF_UNGATED,
CLK_GEM1_REF_UNGATED,
CLK_GEM2_REF_UNGATED,
CLK_GEM3_REF_UNGATED,
CLK_LPD_WDT,
END_OF_OUTPUT_CLKS, END_OF_OUTPUT_CLKS,
}; };
...@@ -175,10 +184,14 @@ enum { ...@@ -175,10 +184,14 @@ enum {
EXT_CLK_GT_CRX_REF, EXT_CLK_GT_CRX_REF,
EXT_CLK_SWDT0, EXT_CLK_SWDT0,
EXT_CLK_SWDT1, EXT_CLK_SWDT1,
EXT_CLK_GEM0_EMIO, EXT_CLK_GEM0_TX_EMIO,
EXT_CLK_GEM1_EMIO, EXT_CLK_GEM1_TX_EMIO,
EXT_CLK_GEM2_EMIO, EXT_CLK_GEM2_TX_EMIO,
EXT_CLK_GEM3_EMIO, EXT_CLK_GEM3_TX_EMIO,
EXT_CLK_GEM0_RX_EMIO,
EXT_CLK_GEM1_RX_EMIO,
EXT_CLK_GEM2_RX_EMIO,
EXT_CLK_GEM3_RX_EMIO,
EXT_CLK_MIO50_OR_MIO51, EXT_CLK_MIO50_OR_MIO51,
EXT_CLK_MIO0, EXT_CLK_MIO0,
EXT_CLK_MIO1, EXT_CLK_MIO1,
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment