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Commit 22e002da authored by Dan Handley's avatar Dan Handley
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Merge pull request #112 from danh-arm:dh/refactor-plat-header-v4 into for-v0.4

parents f53d0fce 9865ac15
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include/bl2/bl2.h → plat/fvp/fvp_private.h
View file @ 22e002da
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -28,46 +28,82 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BL2_H__
#define __BL2_H__
#ifndef __FVP_PRIVATE_H__
#define __FVP_PRIVATE_H__
/******************************************
* Data declarations
*****************************************/
extern unsigned long long bl2_entrypoint;
#include <bl_common.h>
#include <platform_def.h>
/******************************************
* Forward declarations
*****************************************/
struct meminfo;
struct bl31_args;
/******************************************
* Function prototypes
*****************************************/
extern void bl2_platform_setup(void);
extern struct meminfo *bl2_plat_sec_mem_layout(void);
typedef volatile struct mailbox {
unsigned long value
__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
} mailbox_t;
/*******************************************************************************
* This function returns a pointer to the shared memory that the platform has
* kept aside to pass trusted firmware related information that BL3-1
* could need
* This structure represents the superset of information that is passed to
* BL31 e.g. while passing control to it from BL2 which is bl31_params
* and bl31_plat_params and its elements
******************************************************************************/
extern struct bl31_params *bl2_plat_get_bl31_params(void);
typedef struct bl2_to_bl31_params_mem {
bl31_params_t bl31_params;
image_info_t bl31_image_info;
image_info_t bl32_image_info;
image_info_t bl33_image_info;
entry_point_info_t bl33_ep_info;
entry_point_info_t bl32_ep_info;
entry_point_info_t bl31_ep_info;
} bl2_to_bl31_params_mem_t;
/*******************************************************************************
* Forward declarations
******************************************************************************/
struct meminfo;
/*******************************************************************************
* This function returns a pointer to the shared memory that the platform
* has kept to point to entry point information of BL31 to BL2
* Function and variable prototypes
******************************************************************************/
extern struct entry_point_info *bl2_plat_get_bl31_ep_info(void);
void fvp_configure_mmu_el1(unsigned long total_base,
unsigned long total_size,
unsigned long,
unsigned long,
unsigned long,
unsigned long);
void fvp_configure_mmu_el3(unsigned long total_base,
unsigned long total_size,
unsigned long,
unsigned long,
unsigned long,
unsigned long);
unsigned long fvp_get_cfgvar(unsigned int);
int fvp_config_setup(void);
#if RESET_TO_BL31
void fvp_get_entry_point_info(unsigned long target_security,
struct entry_point_info *target_entry_info);
#endif
void fvp_cci_setup(void);
/* Declarations for fvp_gic.c */
void gic_cpuif_deactivate(unsigned int);
void gic_cpuif_setup(unsigned int);
void gic_pcpu_distif_setup(unsigned int);
void gic_setup(void);
/* Declarations for fvp_topology.c */
int fvp_setup_topology(void);
/* Declarations for fvp_io_storage.c */
void fvp_io_setup(void);
/* Declarations for fvp_security.c */
void fvp_security_setup(void);
/* Sets the entrypoint for BL32 */
void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep);
/************************************************************************
* This function flushes to main memory all the params that are
* passed to BL3-1
**************************************************************************/
extern void bl2_plat_flush_bl31_params(void);
/* Sets the entrypoint for BL33 */
void fvp_set_bl33_ep_info(struct entry_point_info *bl33_ep);
#endif /* __BL2_H__ */
#endif /* __FVP_PRIVATE_H__ */
plat/fvp/plat_security.c → plat/fvp/fvp_security.c
View file @ 22e002da
......@@ -29,9 +29,10 @@
*/
#include <assert.h>
#include <platform.h>
#include <tzc400.h>
#include <debug.h>
#include <tzc400.h>
#include "fvp_def.h"
#include "fvp_private.h"
/* Used to improve readability for configuring regions. */
#define FILTER_SHIFT(filter) (1 << filter)
......@@ -42,7 +43,7 @@
* TODO:
* Might want to enable interrupt on violations when supported?
*/
void plat_security_setup(void)
void fvp_security_setup(void)
{
tzc_instance_t controller;
......@@ -55,7 +56,7 @@ void plat_security_setup(void)
* configurations, those would be configured here.
*/
if (!platform_get_cfgvar(CONFIG_HAS_TZC))
if (!fvp_get_cfgvar(CONFIG_HAS_TZC))
return;
/*
......
plat/fvp/plat_topology.c → plat/fvp/fvp_topology.c
View file @ 22e002da
......@@ -29,7 +29,7 @@
*/
#include <assert.h>
#include <platform.h>
#include <platform_def.h>
/* TODO: Reusing psci error codes & state information. Get our own! */
#include <psci.h>
#include "drivers/pwrc/fvp_pwrc.h"
......@@ -190,7 +190,7 @@ int plat_get_max_afflvl()
* the FVP flavour its running on. We construct all the mpidrs we can handle
* and rely on the PWRC.PSYSR to flag absent cpus when their status is queried.
******************************************************************************/
int plat_setup_topology()
int fvp_setup_topology()
{
unsigned char aff0, aff1, aff_state, aff0_offset = 0;
unsigned long mpidr;
......
plat/fvp/include/plat_macros.S
View file @ 22e002da
......@@ -29,7 +29,7 @@
*/
#include <gic_v2.h>
#include <platform.h>
#include "../fvp_def.h"
.section .rodata.gic_reg_name, "aS"
gic_regs: .asciz "gic_iar", "gic_ctlr", ""
......@@ -44,7 +44,7 @@ gic_regs: .asciz "gic_iar", "gic_ctlr", ""
*/
.macro plat_print_gic_regs
mov x0, #CONFIG_GICC_ADDR
bl platform_get_cfgvar
bl fvp_get_cfgvar
/* gic base address is now in x0 */
ldr w1, [x0, #GICC_IAR]
ldr w2, [x0, #GICD_CTLR]
......
plat/fvp/include/platform_def.h 0 → 100644
View file @ 22e002da
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_DEF_H__
#define __PLATFORM_DEF_H__
#include <arch.h>
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
/*******************************************************************************
* Generic platform constants
******************************************************************************/
/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0x800
/* Size of coherent stacks for debug and release builds */
#if DEBUG
#define PCPU_DV_MEM_STACK_SIZE 0x400
#else
#define PCPU_DV_MEM_STACK_SIZE 0x300
#endif
#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r"
/* Trusted Boot Firmware BL2 */
#define BL2_IMAGE_NAME "bl2.bin"
/* EL3 Runtime Firmware BL31 */
#define BL31_IMAGE_NAME "bl31.bin"
/* Secure Payload BL32 (Trusted OS) */
#define BL32_IMAGE_NAME "bl32.bin"
/* Non-Trusted Firmware BL33 */
#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
#define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_CLUSTER_COUNT 2ull
#define PLATFORM_CLUSTER0_CORE_COUNT 4
#define PLATFORM_CLUSTER1_CORE_COUNT 4
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
PLATFORM_CLUSTER0_CORE_COUNT)
#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
#define PRIMARY_CPU 0x0
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
#define TZROM_BASE 0x00000000
#define TZROM_SIZE 0x04000000
#define TZRAM_BASE 0x04000000
#define TZRAM_SIZE 0x40000
/* Location of trusted dram on the base fvp */
#define TZDRAM_BASE 0x06000000
#define TZDRAM_SIZE 0x02000000
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
* addresses.
******************************************************************************/
#define BL1_RO_BASE TZROM_BASE
#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
#define BL1_RW_BASE TZRAM_BASE
#define BL1_RW_LIMIT BL31_BASE
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000)
#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
#define BL31_BASE (TZRAM_BASE + 0x6000)
#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
#define BL31_LIMIT BL32_BASE
#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
#define BL31_LIMIT BL2_BASE
#endif
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
/*
* On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
*/
#define TSP_IN_TZRAM 0
#define TSP_IN_TZDRAM 1
#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
# define TSP_SEC_MEM_BASE TZRAM_BASE
# define TSP_SEC_MEM_SIZE TZRAM_SIZE
# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1c000)
# define BL32_LIMIT BL2_BASE
#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
# define TSP_SEC_MEM_BASE TZDRAM_BASE
# define TSP_SEC_MEM_SIZE TZDRAM_SIZE
# define BL32_BASE (TZDRAM_BASE + 0x2000)
# define BL32_LIMIT (TZDRAM_BASE + (1 << 21))
#else
# error "Unsupported TSP_RAM_LOCATION_ID value"
#endif
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define ADDR_SPACE_SIZE (1ull << 32)
#define MAX_XLAT_TABLES 3
#define MAX_MMAP_REGIONS 16
/*******************************************************************************
* ID of the secure physical generic timer interrupt.
******************************************************************************/
#define IRQ_SEC_PHY_TIMER 29
/*******************************************************************************
* CCI-400 related constants
******************************************************************************/
#define CCI400_BASE 0x2c090000
#define CCI400_SL_IFACE_CLUSTER0 3
#define CCI400_SL_IFACE_CLUSTER1 4
#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
CCI400_SL_IFACE_CLUSTER1 : \
CCI400_SL_IFACE_CLUSTER0)
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#endif /* __PLATFORM_DEF_H__ */
plat/fvp/platform.mk
View file @ 22e002da
......@@ -55,36 +55,37 @@ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011.c \
lib/aarch64/xlat_tables.c \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
plat/fvp/plat_io_storage.c
plat/common/aarch64/plat_common.c \
plat/fvp/fvp_io_storage.c
BL1_SOURCES += drivers/arm/cci400/cci400.c \
plat/common/aarch64/platform_up_stack.S \
plat/fvp/bl1_plat_setup.c \
plat/fvp/aarch64/plat_common.c \
plat/fvp/aarch64/plat_helpers.S
plat/fvp/bl1_fvp_setup.c \
plat/fvp/aarch64/fvp_common.c \
plat/fvp/aarch64/fvp_helpers.S
BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
plat/common/aarch64/platform_up_stack.S \
plat/fvp/bl2_plat_setup.c \
plat/fvp/plat_security.c \
plat/fvp/aarch64/plat_common.c
plat/fvp/bl2_fvp_setup.c \
plat/fvp/fvp_security.c \
plat/fvp/aarch64/fvp_common.c
BL31_SOURCES += drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
drivers/arm/gic/aarch64/gic_v3_sysregs.S \
drivers/arm/cci400/cci400.c \
plat/common/aarch64/platform_mp_stack.S \
plat/fvp/bl31_plat_setup.c \
plat/fvp/plat_gic.c \
plat/fvp/plat_pm.c \
plat/fvp/plat_topology.c \
plat/fvp/aarch64/plat_helpers.S \
plat/fvp/aarch64/plat_common.c \
plat/fvp/bl31_fvp_setup.c \
plat/fvp/fvp_gic.c \
plat/fvp/fvp_pm.c \
plat/fvp/fvp_topology.c \
plat/fvp/aarch64/fvp_helpers.S \
plat/fvp/aarch64/fvp_common.c \
plat/fvp/drivers/pwrc/fvp_pwrc.c
ifeq (${RESET_TO_BL31}, 1)
BL31_SOURCES += drivers/arm/tzc400/tzc400.c \
plat/fvp/plat_security.c
BL31_SOURCES += drivers/arm/tzc400/tzc400.c \
plat/fvp/fvp_security.c
endif
# Flag used by the FVP port to determine the version of ARM GIC architecture
......
services/spd/tspd/tspd_common.c
View file @ 22e002da
......@@ -32,7 +32,6 @@
#include <assert.h>
#include <bl_common.h>
#include <context_mgmt.h>
#include <platform.h>
#include <string.h>
#include "tspd_private.h"
......
services/spd/tspd/tspd_main.c
View file @ 22e002da
......@@ -160,7 +160,7 @@ int32_t tspd_setup(void)
* absence is a critical failure. TODO: Add support to
* conditionally include the SPD service
*/
image_info = bl31_get_next_image_info(SECURE);
image_info = bl31_plat_get_next_image_ep_info(SECURE);
assert(image_info);
/*
......
services/spd/tspd/tspd_pm.c
View file @ 22e002da
......@@ -33,6 +33,7 @@
#include <bl_common.h>
#include <context_mgmt.h>
#include <debug.h>
#include <platform.h>
#include <tsp.h>
#include "tspd_private.h"
......
services/spd/tspd/tspd_private.h
View file @ 22e002da
......@@ -34,7 +34,7 @@
#include <arch.h>
#include <context.h>
#include <interrupt_mgmt.h>
#include <platform.h>
#include <platform_def.h>
#include <psci.h>
/*******************************************************************************
......@@ -188,11 +188,11 @@ struct tsp_vectors;
/*******************************************************************************
* Function & Data prototypes
******************************************************************************/
extern uint64_t tspd_enter_sp(uint64_t *c_rt_ctx);
extern void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret);
extern uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx);
extern void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret);
extern int32_t tspd_init_secure_context(uint64_t entrypoint,
uint64_t tspd_enter_sp(uint64_t *c_rt_ctx);
void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret);
uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx);
void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret);
int32_t tspd_init_secure_context(uint64_t entrypoint,
uint32_t rw,
uint64_t mpidr,
tsp_context_t *tsp_ctx);
......
services/std_svc/psci/psci_afflvl_on.c
View file @ 22e002da
......@@ -34,6 +34,7 @@
#include <bl_common.h>
#include <bl31.h>
#include <context_mgmt.h>
#include <platform.h>
#include <runtime_svc.h>
#include <stddef.h>
#include "psci_private.h"
......@@ -362,7 +363,7 @@ static unsigned int psci_afflvl0_on_finish(unsigned long mpidr,
/*
* Arch. management: Turn on mmu & restore architectural state
*/
enable_mmu_el3();
bl31_plat_enable_mmu();
/*
* All the platform specific actions for turning this cpu
......
services/std_svc/psci/psci_common.c
View file @ 22e002da
......@@ -35,6 +35,7 @@
#include <context.h>
#include <context_mgmt.h>
#include <debug.h>
#include <platform.h>
#include "psci_private.h"
/*
......@@ -45,13 +46,11 @@ const spd_pm_ops_t *psci_spd_pm;
/*******************************************************************************
* Arrays that contains information needs to resume a cpu's execution when woken
* out of suspend or off states. 'psci_ns_einfo_idx' keeps track of the next
* free index in the 'psci_ns_entry_info' & 'psci_suspend_context' arrays. Each
* cpu is allocated a single entry in each array during startup.
* out of suspend or off states. Each cpu is allocated a single entry in each
* array during startup.
******************************************************************************/
suspend_context_t psci_suspend_context[PSCI_NUM_AFFS];
ns_entry_info_t psci_ns_entry_info[PSCI_NUM_AFFS];
unsigned int psci_ns_einfo_idx;
/*******************************************************************************
* Grand array that holds the platform's topology information for state
......@@ -61,16 +60,6 @@ unsigned int psci_ns_einfo_idx;
aff_map_node_t psci_aff_map[PSCI_NUM_AFFS]
__attribute__ ((section("tzfw_coherent_mem")));
/*******************************************************************************
* In a system, a certain number of affinity instances are present at an
* affinity level. The cumulative number of instances across all levels are
* stored in 'psci_aff_map'. The topology tree has been flattenned into this
* array. To retrieve nodes, information about the extents of each affinity
* level i.e. start index and end index needs to be present. 'psci_aff_limits'
* stores this information.
******************************************************************************/
aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1];
/*******************************************************************************
* Pointer to functions exported by the platform to complete power mgmt. ops
******************************************************************************/
......
services/std_svc/psci/psci_private.h
View file @ 22e002da
......@@ -86,12 +86,8 @@ typedef unsigned int (*afflvl_power_on_finisher_t)(unsigned long,
******************************************************************************/
extern suspend_context_t psci_suspend_context[PSCI_NUM_AFFS];
extern ns_entry_info_t psci_ns_entry_info[PSCI_NUM_AFFS];
extern unsigned int psci_ns_einfo_idx;
extern aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1];
extern const plat_pm_ops_t *psci_plat_pm_ops;
extern aff_map_node_t psci_aff_map[PSCI_NUM_AFFS];
extern afflvl_power_on_finisher_t psci_afflvl_off_finish_handlers[];
extern afflvl_power_on_finisher_t psci_afflvl_sus_finish_handlers[];
/*******************************************************************************
* SPD's power management hooks registered with PSCI
......@@ -102,59 +98,59 @@ extern const spd_pm_ops_t *psci_spd_pm;
* Function prototypes
******************************************************************************/
/* Private exported functions from psci_common.c */
extern int get_max_afflvl(void);
extern unsigned short psci_get_state(aff_map_node_t *node);
extern unsigned short psci_get_phys_state(aff_map_node_t *node);
extern void psci_set_state(aff_map_node_t *node, unsigned short state);
extern void psci_get_ns_entry_info(unsigned int index);
extern unsigned long mpidr_set_aff_inst(unsigned long, unsigned char, int);
extern int psci_validate_mpidr(unsigned long, int);
extern int get_power_on_target_afflvl(unsigned long mpidr);
extern void psci_afflvl_power_on_finish(unsigned long,
int get_max_afflvl(void);
unsigned short psci_get_state(aff_map_node_t *node);
unsigned short psci_get_phys_state(aff_map_node_t *node);
void psci_set_state(aff_map_node_t *node, unsigned short state);
void psci_get_ns_entry_info(unsigned int index);
unsigned long mpidr_set_aff_inst(unsigned long, unsigned char, int);
int psci_validate_mpidr(unsigned long, int);
int get_power_on_target_afflvl(unsigned long mpidr);
void psci_afflvl_power_on_finish(unsigned long,
int,
int,
afflvl_power_on_finisher_t *);
extern int psci_set_ns_entry_info(unsigned int index,
int psci_set_ns_entry_info(unsigned int index,
unsigned long entrypoint,
unsigned long context_id);
extern int psci_check_afflvl_range(int start_afflvl, int end_afflvl);
extern void psci_acquire_afflvl_locks(unsigned long mpidr,
int psci_check_afflvl_range(int start_afflvl, int end_afflvl);
void psci_acquire_afflvl_locks(unsigned long mpidr,
int start_afflvl,
int end_afflvl,
mpidr_aff_map_nodes_t mpidr_nodes);
extern void psci_release_afflvl_locks(unsigned long mpidr,
void psci_release_afflvl_locks(unsigned long mpidr,
int start_afflvl,
int end_afflvl,
mpidr_aff_map_nodes_t mpidr_nodes);
/* Private exported functions from psci_setup.c */
extern int psci_get_aff_map_nodes(unsigned long mpidr,
int psci_get_aff_map_nodes(unsigned long mpidr,
int start_afflvl,
int end_afflvl,
mpidr_aff_map_nodes_t mpidr_nodes);
extern aff_map_node_t *psci_get_aff_map_node(unsigned long, int);
aff_map_node_t *psci_get_aff_map_node(unsigned long, int);
/* Private exported functions from psci_affinity_on.c */
extern int psci_afflvl_on(unsigned long,
int psci_afflvl_on(unsigned long,
unsigned long,
unsigned long,
int,
int);
/* Private exported functions from psci_affinity_off.c */
extern int psci_afflvl_off(unsigned long, int, int);
int psci_afflvl_off(unsigned long, int, int);
/* Private exported functions from psci_affinity_suspend.c */
extern void psci_set_suspend_power_state(aff_map_node_t *node,
void psci_set_suspend_power_state(aff_map_node_t *node,
unsigned int power_state);
extern int psci_get_aff_map_node_suspend_afflvl(aff_map_node_t *node);
extern int psci_afflvl_suspend(unsigned long,
int psci_get_aff_map_node_suspend_afflvl(aff_map_node_t *node);
int psci_afflvl_suspend(unsigned long,
unsigned long,
unsigned long,
unsigned int,
int,
int);
extern unsigned int psci_afflvl_suspend_finish(unsigned long, int, int);
unsigned int psci_afflvl_suspend_finish(unsigned long, int, int);
#endif /* __PSCI_PRIVATE_H__ */
services/std_svc/psci/psci_setup.c
View file @ 22e002da
......@@ -47,6 +47,22 @@
******************************************************************************/
static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
/*******************************************************************************
* In a system, a certain number of affinity instances are present at an
* affinity level. The cumulative number of instances across all levels are
* stored in 'psci_aff_map'. The topology tree has been flattenned into this
* array. To retrieve nodes, information about the extents of each affinity
* level i.e. start index and end index needs to be present. 'psci_aff_limits'
* stores this information.
******************************************************************************/
static aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1];
/*******************************************************************************
* 'psci_ns_einfo_idx' keeps track of the next free index in the
* 'psci_ns_entry_info' & 'psci_suspend_context' arrays.
******************************************************************************/
static unsigned int psci_ns_einfo_idx;
/*******************************************************************************
* Routines for retrieving the node corresponding to an affinity level instance
* in the mpidr. The first one uses binary search to find the node corresponding
......
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