doc: Reformat platform port documents

The platform port documents are not very standardised right now and
they don't integrate properly into the document tree so:

1) Make sure each port has a proper name and title (incl. owner)
2) Correct use of headings, subheadings, etc in each port
3) Resolve any naming conflicts between documents

Change-Id: I4c2da6f57172b7f2af3512e766ae9ce3b840b50f
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

docs/plat/xilinx-versal.md → docs/plat/xilinx-versal.rst

-Trusted Firmware-A for Xilinx Versal
-================================
+Xilinx Versal
+=============
 
 Trusted Firmware-A implements the EL3 firmware layer for Xilinx Versal.
 The platform only uses the runtime part of TF-A as Xilinx Versal already has a
@@ -19,7 +19,9 @@ To build ATF for different platform (for now its just versal virtual "versal_vir
 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal VERSAL_PLATFORM=versal_virt bl31
 ```
 
-# Xilinx Versal platform specific build options
+Xilinx Versal platform specific build options
+---------------------------------------------
+
 *   `VERSAL_ATF_MEM_BASE`: Specifies the base address of the bl31 binary.
 *   `VERSAL_ATF_MEM_SIZE`: Specifies the size of the memory region of the bl31 binary.
 *   `VERSAL_BL32_MEM_BASE`: Specifies the base address of the bl32 binary.

docs/plat/xilinx-zynqmp.rst

-Trusted Firmware-A for Xilinx Zynq UltraScale+ MPSoC
-====================================================
+Xilinx Zynq UltraScale+ MPSoC
+=============================
 
 Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq
 UltraScale + MPSoC.
@@ -23,7 +23,7 @@ To build bl32 TSP you have to rebuild bl31 too:
     make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32
 
 ZynqMP platform specific build options
-======================================
+--------------------------------------
 
 -  ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary.
 -  ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary.
@@ -36,7 +36,7 @@ ZynqMP platform specific build options
    -  ``cadence1`` : Cadence UART 1
 
 FSBL->TF-A Parameter Passing
-===========================
+----------------------------
 
 The FSBL populates a data structure with image information for TF-A. TF-A uses
 that data to hand off to the loaded images. The address of the handoff data
@@ -45,7 +45,7 @@ register is free to be used by other software once TF-A has brought up
 further firmware images.
 
 Power Domain Tree
-=================
+-----------------
 
 The following power domain tree represents the power domain model used by TF-A
 for ZynqMP: