From 256d133a8a489b8731e5f499457468a4b8a13ab4 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 24 Sep 2018 22:51:49 -0700 Subject: [PATCH] plat: xilinx: zynqmp: Use GIC framework for warm restart - Flag GICV2_G0_FOR_EL3 needs to be set for group interrupts to be targeted to EL3. - Raise SGI interrupts for individual CPU cores as GIC API uses CPU num as parameter, not CPU mask. - Flag WARMBOOT_ENABLE_DCACHE_EARLY needs to be set to enable CPU interface mask work properly for all CPU cores which is required when generating SGI. - Call plat_ic_end_of_interrupt() from ttc_fiq_handler() to clear GIC interrupt to avoid same interrupt again. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: I71d4935b8d4688a3729c62753ca8a1a77cd92ae7 --- plat/xilinx/zynqmp/plat_psci.c | 5 ++--- plat/xilinx/zynqmp/platform.mk | 2 ++ plat/xilinx/zynqmp/pm_service/pm_svc_main.c | 10 ++++++++-- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c index a32e08988..f579f795f 100644 --- a/plat/xilinx/zynqmp/plat_psci.c +++ b/plat/xilinx/zynqmp/plat_psci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -100,9 +100,8 @@ static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); - + plat_arm_gic_pcpu_init(); gicv2_cpuif_enable(); - gicv2_pcpu_distif_init(); } static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index 1039e2751..33d648860 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -11,6 +11,8 @@ SEPARATE_CODE_AND_RODATA := 1 ZYNQMP_WDT_RESTART := 0 ZYNQMP_IPI_CRC_CHECK := 0 override RESET_TO_BL31 := 1 +override GICV2_G0_FOR_EL3 := 1 +override WARMBOOT_ENABLE_DCACHE_EARLY := 1 # Do not enable SVE ENABLE_SVE_FOR_NS := 0 diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c index 5a320f1ba..98dbe7d6e 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c +++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c @@ -77,8 +77,12 @@ static void trigger_wdt_restart(void) INFO("Active Cores: %d\n", active_cores); - /* trigger SGI to active cores */ - gicv2_raise_sgi(ARM_IRQ_SEC_SGI_7, target_cpu_list); + for (i = PLATFORM_CORE_COUNT - 1; i >= 0; i--) { + if (target_cpu_list & (1 << i)) { + /* trigger SGI to active cores */ + plat_ic_raise_el3_sgi(ARM_IRQ_SEC_SGI_7, i); + } + } } /** @@ -106,6 +110,8 @@ static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle, { INFO("BL31: Got TTC FIQ\n"); + plat_ic_end_of_interrupt(id); + /* Clear TTC interrupt by reading interrupt register */ mmio_read_32(TTC3_INTR_REGISTER_1); -- GitLab