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Commit 258f6a2d authored by Madhukar Pappireddy's avatar Madhukar Pappireddy Committed by TrustedFirmware Code Review
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Merge changes I4bd4612a,Id13a06d4,I0ea7f610,Ie6a7063b into integration 

* changes:
  mediatek: mt8192: Add Vcore DVFS driver
  mediatek: mt8192: Add SPM suspend driver
  mediatek: mt8192: supports mcusys off when system suspend
  mediatek: mt8192: Add lpm driver
parents c0f0ab53 f3febcca
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plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_CONSERVATION_H
#define MT_SPM_CONSERVATION_H
#include <mt_spm_internal.h>
extern int spm_conservation(int state_id, unsigned int ext_opand,
struct spm_lp_scen *spm_lp,
unsigned int resource_req);
extern void spm_conservation_finish(int state_id, unsigned int ext_opand,
struct spm_lp_scen *spm_lp,
struct wake_status **status);
extern int spm_conservation_get_result(struct wake_status **res);
extern void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl);
#endif /* MT_SPM_CONSERVATION_H */
plat/mediatek/mt8192/drivers/spm/mt_spm_constraint.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_CONSTRAINT_H
#define MT_SPM_CONSTRAINT_H
#include <mt_lp_rm.h>
#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF (1U << 0)
#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 (1U << 1)
#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 (1U << 2)
#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP (1U << 3)
#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN (1U << 4)
#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF (1U << 5)
#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND (1U << 6)
#define MT_RM_CONSTRAINT_ALLOW_BBLPM (1U << 7)
#define MT_RM_CONSTRAINT_ALLOW_XO_UFS (1U << 8)
#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE (1U << 9)
#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE (1U << 10)
#define MT_SPM_RC_INVALID 0x0
#define MT_SPM_RC_VALID_SW (1U << 0)
#define MT_SPM_RC_VALID_FW (1U << 1)
#define MT_SPM_RC_VALID_RESIDNECY (1U << 2)
#define MT_SPM_RC_VALID_COND_CHECK (1U << 3)
#define MT_SPM_RC_VALID_COND_LATCH (1U << 4)
#define MT_SPM_RC_VALID_UFS_H8 (1U << 5)
#define MT_SPM_RC_VALID_FLIGHTMODE (1U << 6)
#define MT_SPM_RC_VALID_XSOC_BBLPM (1U << 7)
#define MT_SPM_RC_VALID_TRACE_EVENT (1U << 8)
#define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW)
#define IS_MT_RM_RC_READY(status) \
((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
#define MT_SPM_RC_BBLPM_MODE \
(MT_SPM_RC_VALID_UFS_H8 | \
MT_SPM_RC_VALID_FLIGHTMODE | \
MT_SPM_RC_VALID_XSOC_BBLPM)
#define IS_MT_SPM_RC_BBLPM_MODE(st) \
((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
struct constraint_status {
uint16_t id;
uint16_t valid;
uint32_t cond_block;
uint32_t enter_cnt;
struct mt_spm_cond_tables *cond_res;
};
enum MT_SPM_RM_RC_TYPE {
MT_RM_CONSTRAINT_ID_BUS26M,
MT_RM_CONSTRAINT_ID_SYSPLL,
MT_RM_CONSTRAINT_ID_DRAM,
MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO,
MT_RM_CONSTRAINT_ID_ALL,
};
#endif /* MT_SPM_CONSTRAINT_H */
plat/mediatek/mt8192/drivers/spm/mt_spm_idle.c 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_conservation.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_reg.h>
#include <mt_spm_resource_req.h>
#include <plat_pm.h>
#define __WAKE_SRC_FOR_IDLE_COMMON__ \
(R12_PCM_TIMER | \
R12_KP_IRQ_B | \
R12_APWDT_EVENT_B | \
R12_APXGPT1_EVENT_B | \
R12_CONN2AP_SPM_WAKEUP_B | \
R12_EINT_EVENT_B | \
R12_CONN_WDT_IRQ_B | \
R12_CCIF0_EVENT_B | \
R12_SSPM2SPM_WAKEUP_B | \
R12_SCP2SPM_WAKEUP_B | \
R12_ADSP2SPM_WAKEUP_B | \
R12_USBX_CDSC_B | \
R12_USBX_POWERDWN_B | \
R12_SYS_TIMER_EVENT_B | \
R12_EINT_EVENT_SECURE_B | \
R12_CCIF1_EVENT_B | \
R12_AFE_IRQ_MCU_B | \
R12_SYS_CIRQ_IRQ_B | \
R12_MD2AP_PEER_EVENT_B | \
R12_MD1_WDT_B | \
R12_CLDMA_EVENT_B | \
R12_REG_CPU_WAKEUP | \
R12_APUSYS_WAKE_HOST_B | \
R12_PCIE_BRIDGE_IRQ | \
R12_PCIE_IRQ)
#if defined(CFG_MICROTRUST_TEE_SUPPORT)
#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__)
#else
#define WAKE_SRC_FOR_IDLE \
(__WAKE_SRC_FOR_IDLE_COMMON__ | \
R12_SEJ_EVENT_B)
#endif
static struct pwr_ctrl idle_spm_pwr = {
.timer_val = 0x28000,
.wake_src = WAKE_SRC_FOR_IDLE,
/* Auto-gen Start */
/* SPM_AP_STANDBY_CON */
.reg_wfi_op = 0,
.reg_wfi_type = 0,
.reg_mp0_cputop_idle_mask = 0,
.reg_mp1_cputop_idle_mask = 0,
.reg_mcusys_idle_mask = 0,
.reg_md_apsrc_1_sel = 0,
.reg_md_apsrc_0_sel = 0,
.reg_conn_apsrc_sel = 0,
/* SPM_SRC6_MASK */
.reg_dpmaif_srcclkena_mask_b = 1,
.reg_dpmaif_infra_req_mask_b = 1,
.reg_dpmaif_apsrc_req_mask_b = 1,
.reg_dpmaif_vrf18_req_mask_b = 1,
.reg_dpmaif_ddr_en_mask_b = 1,
/* SPM_SRC_REQ */
.reg_spm_apsrc_req = 1,
.reg_spm_f26m_req = 1,
.reg_spm_infra_req = 1,
.reg_spm_vrf18_req = 1,
.reg_spm_ddr_en_req = 1,
.reg_spm_dvfs_req = 0,
.reg_spm_sw_mailbox_req = 0,
.reg_spm_sspm_mailbox_req = 0,
.reg_spm_adsp_mailbox_req = 0,
.reg_spm_scp_mailbox_req = 0,
/* SPM_SRC_MASK */
.reg_md_srcclkena_0_mask_b = 1,
.reg_md_srcclkena2infra_req_0_mask_b = 0,
.reg_md_apsrc2infra_req_0_mask_b = 1,
.reg_md_apsrc_req_0_mask_b = 1,
.reg_md_vrf18_req_0_mask_b = 1,
.reg_md_ddr_en_0_mask_b = 1,
.reg_md_srcclkena_1_mask_b = 0,
.reg_md_srcclkena2infra_req_1_mask_b = 0,
.reg_md_apsrc2infra_req_1_mask_b = 0,
.reg_md_apsrc_req_1_mask_b = 0,
.reg_md_vrf18_req_1_mask_b = 0,
.reg_md_ddr_en_1_mask_b = 0,
.reg_conn_srcclkena_mask_b = 1,
.reg_conn_srcclkenb_mask_b = 0,
.reg_conn_infra_req_mask_b = 1,
.reg_conn_apsrc_req_mask_b = 1,
.reg_conn_vrf18_req_mask_b = 1,
.reg_conn_ddr_en_mask_b = 1,
.reg_conn_vfe28_mask_b = 0,
.reg_srcclkeni0_srcclkena_mask_b = 1,
.reg_srcclkeni0_infra_req_mask_b = 1,
.reg_srcclkeni1_srcclkena_mask_b = 0,
.reg_srcclkeni1_infra_req_mask_b = 0,
.reg_srcclkeni2_srcclkena_mask_b = 0,
.reg_srcclkeni2_infra_req_mask_b = 0,
.reg_infrasys_apsrc_req_mask_b = 0,
.reg_infrasys_ddr_en_mask_b = 1,
.reg_md32_srcclkena_mask_b = 1,
.reg_md32_infra_req_mask_b = 1,
.reg_md32_apsrc_req_mask_b = 1,
.reg_md32_vrf18_req_mask_b = 1,
.reg_md32_ddr_en_mask_b = 1,
/* SPM_SRC2_MASK */
.reg_scp_srcclkena_mask_b = 1,
.reg_scp_infra_req_mask_b = 1,
.reg_scp_apsrc_req_mask_b = 1,
.reg_scp_vrf18_req_mask_b = 1,
.reg_scp_ddr_en_mask_b = 1,
.reg_audio_dsp_srcclkena_mask_b = 1,
.reg_audio_dsp_infra_req_mask_b = 1,
.reg_audio_dsp_apsrc_req_mask_b = 1,
.reg_audio_dsp_vrf18_req_mask_b = 1,
.reg_audio_dsp_ddr_en_mask_b = 1,
.reg_ufs_srcclkena_mask_b = 1,
.reg_ufs_infra_req_mask_b = 1,
.reg_ufs_apsrc_req_mask_b = 1,
.reg_ufs_vrf18_req_mask_b = 1,
.reg_ufs_ddr_en_mask_b = 1,
.reg_disp0_apsrc_req_mask_b = 1,
.reg_disp0_ddr_en_mask_b = 1,
.reg_disp1_apsrc_req_mask_b = 1,
.reg_disp1_ddr_en_mask_b = 1,
.reg_gce_infra_req_mask_b = 1,
.reg_gce_apsrc_req_mask_b = 1,
.reg_gce_vrf18_req_mask_b = 1,
.reg_gce_ddr_en_mask_b = 1,
.reg_apu_srcclkena_mask_b = 1,
.reg_apu_infra_req_mask_b = 1,
.reg_apu_apsrc_req_mask_b = 1,
.reg_apu_vrf18_req_mask_b = 1,
.reg_apu_ddr_en_mask_b = 1,
.reg_cg_check_srcclkena_mask_b = 0,
.reg_cg_check_apsrc_req_mask_b = 0,
.reg_cg_check_vrf18_req_mask_b = 0,
.reg_cg_check_ddr_en_mask_b = 0,
/* SPM_SRC3_MASK */
.reg_dvfsrc_event_trigger_mask_b = 1,
.reg_sw2spm_int0_mask_b = 0,
.reg_sw2spm_int1_mask_b = 0,
.reg_sw2spm_int2_mask_b = 0,
.reg_sw2spm_int3_mask_b = 0,
.reg_sc_adsp2spm_wakeup_mask_b = 0,
.reg_sc_sspm2spm_wakeup_mask_b = 0,
.reg_sc_scp2spm_wakeup_mask_b = 0,
.reg_csyspwrreq_mask = 1,
.reg_spm_srcclkena_reserved_mask_b = 0,
.reg_spm_infra_req_reserved_mask_b = 0,
.reg_spm_apsrc_req_reserved_mask_b = 0,
.reg_spm_vrf18_req_reserved_mask_b = 0,
.reg_spm_ddr_en_reserved_mask_b = 0,
.reg_mcupm_srcclkena_mask_b = 1,
.reg_mcupm_infra_req_mask_b = 1,
.reg_mcupm_apsrc_req_mask_b = 1,
.reg_mcupm_vrf18_req_mask_b = 1,
.reg_mcupm_ddr_en_mask_b = 1,
.reg_msdc0_srcclkena_mask_b = 1,
.reg_msdc0_infra_req_mask_b = 1,
.reg_msdc0_apsrc_req_mask_b = 1,
.reg_msdc0_vrf18_req_mask_b = 1,
.reg_msdc0_ddr_en_mask_b = 1,
.reg_msdc1_srcclkena_mask_b = 1,
.reg_msdc1_infra_req_mask_b = 1,
.reg_msdc1_apsrc_req_mask_b = 1,
.reg_msdc1_vrf18_req_mask_b = 1,
.reg_msdc1_ddr_en_mask_b = 1,
/* SPM_SRC4_MASK */
.ccif_event_mask_b = 0xFFF,
.reg_bak_psri_srcclkena_mask_b = 0,
.reg_bak_psri_infra_req_mask_b = 0,
.reg_bak_psri_apsrc_req_mask_b = 0,
.reg_bak_psri_vrf18_req_mask_b = 0,
.reg_bak_psri_ddr_en_mask_b = 0,
.reg_dramc0_md32_infra_req_mask_b = 1,
.reg_dramc0_md32_vrf18_req_mask_b = 0,
.reg_dramc1_md32_infra_req_mask_b = 1,
.reg_dramc1_md32_vrf18_req_mask_b = 0,
.reg_conn_srcclkenb2pwrap_mask_b = 0,
.reg_dramc0_md32_wakeup_mask = 1,
.reg_dramc1_md32_wakeup_mask = 1,
/* SPM_SRC5_MASK */
.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
.reg_mcusys_merge_ddr_en_mask_b = 0x11,
.reg_msdc2_srcclkena_mask_b = 1,
.reg_msdc2_infra_req_mask_b = 1,
.reg_msdc2_apsrc_req_mask_b = 1,
.reg_msdc2_vrf18_req_mask_b = 1,
.reg_msdc2_ddr_en_mask_b = 1,
.reg_pcie_srcclkena_mask_b = 1,
.reg_pcie_infra_req_mask_b = 1,
.reg_pcie_apsrc_req_mask_b = 1,
.reg_pcie_vrf18_req_mask_b = 1,
.reg_pcie_ddr_en_mask_b = 1,
/* SPM_WAKEUP_EVENT_MASK */
.reg_wakeup_event_mask = 0x01282202,
/* SPM_WAKEUP_EVENT_EXT_MASK */
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
/* Auto-gen End */
};
struct spm_lp_scen idle_spm_lp = {
.pwrctrl = &idle_spm_pwr,
};
int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
spm_idle_conduct fn)
{
unsigned int src_req = 0;
if (fn != NULL) {
fn(&idle_spm_lp, &src_req);
}
return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
}
void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
struct wake_status **status)
{
spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
}
void mt_spm_idle_generic_init(void)
{
spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl);
}
plat/mediatek/mt8192/drivers/spm/mt_spm_idle.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_IDLE_H
#define MT_SPM_IDLE_H
typedef void (*spm_idle_conduct)(struct spm_lp_scen *spm_lp,
unsigned int *resource_req);
int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
spm_idle_conduct fn);
void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
struct wake_status **status);
void mt_spm_idle_generic_init(void);
#endif /* MT_SPM_IDLE_H */
plat/mediatek/mt8192/drivers/spm/mt_spm_internal.c 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
#include <assert.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_internal.h>
#include <mt_spm_pmic_wrap.h>
#include <mt_spm_reg.h>
#include <mt_spm_resource_req.h>
#include <platform_def.h>
#include <plat_pm.h>
/**************************************
* Define and Declare
**************************************/
#define ROOT_CORE_ADDR_OFFSET 0x20000000
#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK 0xefffffff
#define SPM_INIT_DONE_US 20
static unsigned int mt_spm_bblpm_cnt;
const char *wakeup_src_str[32] = {
[0] = "R12_PCM_TIMER",
[1] = "R12_RESERVED_DEBUG_B",
[2] = "R12_KP_IRQ_B",
[3] = "R12_APWDT_EVENT_B",
[4] = "R12_APXGPT1_EVENT_B",
[5] = "R12_CONN2AP_SPM_WAKEUP_B",
[6] = "R12_EINT_EVENT_B",
[7] = "R12_CONN_WDT_IRQ_B",
[8] = "R12_CCIF0_EVENT_B",
[9] = "R12_LOWBATTERY_IRQ_B",
[10] = "R12_SC_SSPM2SPM_WAKEUP_B",
[11] = "R12_SC_SCP2SPM_WAKEUP_B",
[12] = "R12_SC_ADSP2SPM_WAKEUP_B",
[13] = "R12_PCM_WDT_WAKEUP_B",
[14] = "R12_USB_CDSC_B",
[15] = "R12_USB_POWERDWN_B",
[16] = "R12_SYS_TIMER_EVENT_B",
[17] = "R12_EINT_EVENT_SECURE_B",
[18] = "R12_CCIF1_EVENT_B",
[19] = "R12_UART0_IRQ_B",
[20] = "R12_AFE_IRQ_MCU_B",
[21] = "R12_THERM_CTRL_EVENT_B",
[22] = "R12_SYS_CIRQ_IRQ_B",
[23] = "R12_MD2AP_PEER_EVENT_B",
[24] = "R12_CSYSPWREQ_B",
[25] = "R12_MD1_WDT_B",
[26] = "R12_AP2AP_PEER_WAKEUPEVENT_B",
[27] = "R12_SEJ_EVENT_B",
[28] = "R12_SPM_CPU_WAKEUPEVENT_B",
[29] = "R12_APUSYS",
[30] = "R12_PCIE_BRIDGE_IRQ",
[31] = "R12_PCIE_IRQ",
};
/**************************************
* Function and API
**************************************/
wake_reason_t __spm_output_wake_reason(int state_id,
const struct wake_status *wakesta)
{
uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
wake_reason_t wr = WR_UNKNOWN;
if (wakesta == NULL) {
return WR_UNKNOWN;
}
if (wakesta->abort != 0U) {
ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n",
wakesta->abort, wakesta->timer_out);
} else {
for (i = 0U; i < 32U; i++) {
if ((wakesta->r12 & (1U << i)) != 0U) {
INFO("wake up by %s, timer_out = %u\n",
wakeup_src_str[i], wakesta->timer_out);
wr = WR_WAKE_SRC;
break;
}
}
}
INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
wakesta->debug_flag1);
INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
wakesta->md32pcm_event_sta, wakesta->idle_sta,
wakesta->cg_check_sta);
INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
mmio_read_32(SYS_TIMER_VALUE_H));
if (wakesta->timer_out != 0U) {
bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
}
return wr;
}
void __spm_set_cpu_status(unsigned int cpu)
{
uint32_t root_core_addr;
if (cpu < 8U) {
mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu));
root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
root_core_addr += ROOT_CORE_ADDR_OFFSET;
mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
/* Notify MCUPM that preferred cpu wakeup */
mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
} else {
ERROR("%s: error cpu number %d\n", __func__, cpu);
}
}
void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
unsigned int resource_usage)
{
uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
1 : pwrctrl->reg_spm_apsrc_req;
uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
1 : pwrctrl->reg_spm_ddr_en_req;
uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
1 : pwrctrl->reg_spm_vrf18_req;
uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
1 : pwrctrl->reg_spm_infra_req;
uint8_t f26m_req = ((resource_usage &
(MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
1 : pwrctrl->reg_spm_f26m_req;
mmio_write_32(SPM_SRC_REQ,
((apsrc_req & 0x1) << 0) |
((f26m_req & 0x1) << 1) |
((infra_req & 0x1) << 3) |
((vrf18_req & 0x1) << 4) |
((ddr_en_req & 0x1) << 7) |
((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
}
void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
{
/* Auto-gen Start */
/* SPM_AP_STANDBY_CON */
mmio_write_32(SPM_AP_STANDBY_CON,
((pwrctrl->reg_wfi_op & 0x1) << 0) |
((pwrctrl->reg_wfi_type & 0x1) << 1) |
((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
/* SPM_SRC6_MASK */
mmio_write_32(SPM_SRC6_MASK,
((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) |
((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) |
((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) |
((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) |
((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4));
/* SPM_SRC_REQ */
mmio_write_32(SPM_SRC_REQ,
((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
/* SPM_SRC_MASK */
mmio_write_32(SPM_SRC_MASK,
((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) |
((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) |
((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) |
((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) |
((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) |
((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) |
((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) |
((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) |
((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) |
((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) |
((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) |
((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) |
((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) |
((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) |
((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) |
((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) |
((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) |
((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) |
((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) |
((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) |
((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) |
((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) |
((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) |
((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) |
((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) |
((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) |
((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) |
((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) |
((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) |
((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) |
((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31));
/* SPM_SRC2_MASK */
mmio_write_32(SPM_SRC2_MASK,
((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) |
((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) |
((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) |
((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) |
((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) |
((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) |
((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) |
((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31));
/* SPM_SRC3_MASK */
mmio_write_32(SPM_SRC3_MASK,
((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) |
((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) |
((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) |
((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) |
((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) |
((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) |
((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) |
((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) |
((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) |
((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) |
((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) |
((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) |
((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) |
((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) |
((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) |
((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31));
/* SPM_SRC4_MASK */
mmio_write_32(SPM_SRC4_MASK,
((pwrctrl->ccif_event_mask_b & 0xffff) << 0) |
((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) |
((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) |
((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) |
((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) |
((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) |
((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) |
((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27));
/* SPM_SRC5_MASK */
mmio_write_32(SPM_SRC5_MASK,
((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) |
((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) |
((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) |
((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) |
((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) |
((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) |
((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) |
((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) |
((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27));
/* SPM_WAKEUP_EVENT_MASK */
mmio_write_32(SPM_WAKEUP_EVENT_MASK,
((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
/* SPM_WAKEUP_EVENT_EXT_MASK */
mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
/* Auto-gen End */
}
void __spm_disable_pcm_timer(void)
{
mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
}
void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{
uint32_t val, mask;
/* toggle event counter clear */
mmio_setbits_32(PCM_CON1,
SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
/* toggle for reset SYS TIMER start point */
mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
if (pwrctrl->timer_val_cust == 0U) {
val = pwrctrl->timer_val;
} else {
val = pwrctrl->timer_val_cust;
}
mmio_write_32(PCM_TIMER_VAL, val);
mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
/* unmask AP wakeup source */
if (pwrctrl->wake_src_cust == 0U) {
mask = pwrctrl->wake_src;
} else {
mask = pwrctrl->wake_src_cust;
}
if (pwrctrl->reg_csyspwrreq_mask != 0U) {
mask &= ~R12_CSYSPWREQ_B;
}
mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
/* unmask SPM ISR (keep TWAM setting) */
mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
/* toggle event counter clear */
mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB,
SPM_REGWR_CFG_KEY);
/* toggle for reset SYS TIMER start point */
mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
}
void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
{
/* set PCM flags and data */
if (pwrctrl->pcm_flags_cust_clr != 0U) {
pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
}
if (pwrctrl->pcm_flags_cust_set != 0U) {
pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
}
if (pwrctrl->pcm_flags1_cust_clr != 0U) {
pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
}
if (pwrctrl->pcm_flags1_cust_set != 0U) {
pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
}
mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
}
void __spm_get_wakeup_status(struct wake_status *wakesta,
unsigned int ext_status)
{
wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
mmio_write_32(PCM_WDT_LATCH_SPARE_0,
wakesta->tr.comm.debug_flag);
}
wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
/* record below spm info for debug */
wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
/* backup of SPM_WAKEUP_MISC */
wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
/* get sleep time, backup of PCM_TIMER_OUT */
wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
/* get other SYS and co-clock status */
wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
/* get HW CG check status */
wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
/* get debug flag for PCM execution check */
wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
/* get backup SW flag status */
wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
/* get ISR status */
wakesta->isr = mmio_read_32(SPM_IRQ_STA);
/* get SW flag status */
wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
/* get CLK SETTLE */
wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
/* check abort */
wakesta->abort = (wakesta->debug_flag & DEBUG_ABORT_MASK) |
(wakesta->debug_flag1 & DEBUG_ABORT_MASK_1);
}
void __spm_clean_after_wakeup(void)
{
mmio_write_32(SPM_BK_WAKE_EVENT,
mmio_read_32(SPM_WAKEUP_STA) |
mmio_read_32(SPM_BK_WAKE_EVENT));
mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0);
/*
* clean wakeup event raw status (for edge trigger event)
* bit[28] for cpu wake up event
*/
mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
/* clean ISR status (except TWAM) */
mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
}
void __spm_set_pcm_wdt(int en)
{
mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
SPM_REGWR_CFG_KEY);
if (en == 1) {
mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
SPM_REGWR_CFG_KEY);
if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
}
mmio_write_32(PCM_WDT_VAL,
mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
mmio_setbits_32(PCM_CON1,
SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
}
}
void __spm_send_cpu_wakeup_event(void)
{
/* SPM will clear SPM_CPU_WAKEUP_EVENT */
mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
}
void __spm_ext_int_wakeup_req_clr(void)
{
mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
/* Clear spm2mcupm wakeup interrupt status */
mmio_write_32(SPM2MCUPM_CON, 0);
}
void __spm_xo_soc_bblpm(int en)
{
if (en == 1) {
mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
RC_SW_SRCLKEN_FPM, RC_SW_SRCLKEN_RC);
assert(mt_spm_bblpm_cnt == 0);
mt_spm_bblpm_cnt += 1;
} else {
mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
RC_SW_SRCLKEN_RC, RC_SW_SRCLKEN_FPM);
mt_spm_bblpm_cnt -= 1;
}
}
void __spm_hw_s1_state_monitor(int en, unsigned int *status)
{
unsigned int reg;
reg = mmio_read_32(SPM_ACK_CHK_CON_3);
if (en == 1) {
reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
mmio_write_32(SPM_ACK_CHK_CON_3, reg);
reg |= SPM_ACK_CHK_3_CON_EN;
mmio_write_32(SPM_ACK_CHK_CON_3, reg);
} else {
if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
(status != NULL)) {
*status |= SPM_INTERNAL_STATUS_HW_S1;
}
mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
SPM_ACK_CHK_3_CON_CLR_ALL);
}
}
plat/mediatek/mt8192/drivers/spm/mt_spm_internal.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_INTERNAL_H
#define MT_SPM_INTERNAL_H
#include "mt_spm.h"
/**************************************
* Config and Parameter
**************************************/
#define POWER_ON_VAL0_DEF 0x0000F100
#define POWER_ON_VAL1_DEF 0x80015860
#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */
#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
/**************************************
* Define and Declare
**************************************/
/* PCM_PWR_IO_EN */
#define PCM_PWRIO_EN_R0 (1U << 0)
#define PCM_PWRIO_EN_R7 (1U << 7)
#define PCM_RF_SYNC_R0 (1U << 16)
#define PCM_RF_SYNC_R6 (1U << 22)
#define PCM_RF_SYNC_R7 (1U << 23)
/* SPM_SWINT */
#define PCM_SW_INT0 (1U << 0)
#define PCM_SW_INT1 (1U << 1)
#define PCM_SW_INT2 (1U << 2)
#define PCM_SW_INT3 (1U << 3)
#define PCM_SW_INT4 (1U << 4)
#define PCM_SW_INT5 (1U << 5)
#define PCM_SW_INT6 (1U << 6)
#define PCM_SW_INT7 (1U << 7)
#define PCM_SW_INT8 (1U << 8)
#define PCM_SW_INT9 (1U << 9)
#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
PCM_SW_INT0)
/* SPM_AP_STANDBY_CON */
#define WFI_OP_AND 1
#define WFI_OP_OR 0
/* SPM_IRQ_MASK */
#define ISRM_TWAM (1U << 2)
#define ISRM_PCM_RETURN (1U << 3)
#define ISRM_RET_IRQ0 (1U << 8)
#define ISRM_RET_IRQ1 (1U << 9)
#define ISRM_RET_IRQ2 (1U << 10)
#define ISRM_RET_IRQ3 (1U << 11)
#define ISRM_RET_IRQ4 (1U << 12)
#define ISRM_RET_IRQ5 (1U << 13)
#define ISRM_RET_IRQ6 (1U << 14)
#define ISRM_RET_IRQ7 (1U << 15)
#define ISRM_RET_IRQ8 (1U << 16)
#define ISRM_RET_IRQ9 (1U << 17)
#define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
(ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
(ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
(ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
(ISRM_RET_IRQ1))
#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
/* SPM_IRQ_STA */
#define ISRS_TWAM (1U << 2)
#define ISRS_PCM_RETURN (1U << 3)
#define ISRC_TWAM ISRS_TWAM
#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
/* SPM_WAKEUP_MISC */
#define WAKE_MISC_GIC_WAKEUP 0x3FF
#define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB
#define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
#define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB
#define WAKE_MISC_PMIC_OUT_B ((1U << 19) | (1U << 20))
#define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB
#define WAKE_MISC_PMSR_IRQ_B_SET0 PMSR_IRQ_B_SET0_LSB
#define WAKE_MISC_PMSR_IRQ_B_SET1 PMSR_IRQ_B_SET1_LSB
#define WAKE_MISC_PMSR_IRQ_B_SET2 PMSR_IRQ_B_SET2_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB
#define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB
#define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB
/* ABORT MASK for DEBUG FOORTPRINT */
#define DEBUG_ABORT_MASK \
(SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \
SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
#define DEBUG_ABORT_MASK_1 \
(SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \
SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \
SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \
SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \
SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \
SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \
SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
#define MCUPM_MBOX_WAKEUP_CPU 0x0C55FD10
struct pwr_ctrl {
uint32_t pcm_flags;
uint32_t pcm_flags_cust;
uint32_t pcm_flags_cust_set;
uint32_t pcm_flags_cust_clr;
uint32_t pcm_flags1;
uint32_t pcm_flags1_cust;
uint32_t pcm_flags1_cust_set;
uint32_t pcm_flags1_cust_clr;
uint32_t timer_val;
uint32_t timer_val_cust;
uint32_t timer_val_ramp_en;
uint32_t timer_val_ramp_en_sec;
uint32_t wake_src;
uint32_t wake_src_cust;
uint32_t wakelock_timer_val;
uint8_t wdt_disable;
/* Auto-gen Start */
/* SPM_CLK_CON */
uint8_t reg_srcclken0_ctl;
uint8_t reg_srcclken1_ctl;
uint8_t reg_spm_lock_infra_dcm;
uint8_t reg_srcclken_mask;
uint8_t reg_md1_c32rm_en;
uint8_t reg_md2_c32rm_en;
uint8_t reg_clksq0_sel_ctrl;
uint8_t reg_clksq1_sel_ctrl;
uint8_t reg_srcclken0_en;
uint8_t reg_srcclken1_en;
uint32_t reg_sysclk0_src_mask_b;
uint32_t reg_sysclk1_src_mask_b;
/* SPM_AP_STANDBY_CON */
uint8_t reg_wfi_op;
uint8_t reg_wfi_type;
uint8_t reg_mp0_cputop_idle_mask;
uint8_t reg_mp1_cputop_idle_mask;
uint8_t reg_mcusys_idle_mask;
uint8_t reg_md_apsrc_1_sel;
uint8_t reg_md_apsrc_0_sel;
uint8_t reg_conn_apsrc_sel;
/* SPM_SRC6_MASK */
uint8_t reg_dpmaif_srcclkena_mask_b;
uint8_t reg_dpmaif_infra_req_mask_b;
uint8_t reg_dpmaif_apsrc_req_mask_b;
uint8_t reg_dpmaif_vrf18_req_mask_b;
uint8_t reg_dpmaif_ddr_en_mask_b;
/* SPM_SRC_REQ */
uint8_t reg_spm_apsrc_req;
uint8_t reg_spm_f26m_req;
uint8_t reg_spm_infra_req;
uint8_t reg_spm_vrf18_req;
uint8_t reg_spm_ddr_en_req;
uint8_t reg_spm_dvfs_req;
uint8_t reg_spm_sw_mailbox_req;
uint8_t reg_spm_sspm_mailbox_req;
uint8_t reg_spm_adsp_mailbox_req;
uint8_t reg_spm_scp_mailbox_req;
/* SPM_SRC_MASK */
uint8_t reg_md_srcclkena_0_mask_b;
uint8_t reg_md_srcclkena2infra_req_0_mask_b;
uint8_t reg_md_apsrc2infra_req_0_mask_b;
uint8_t reg_md_apsrc_req_0_mask_b;
uint8_t reg_md_vrf18_req_0_mask_b;
uint8_t reg_md_ddr_en_0_mask_b;
uint8_t reg_md_srcclkena_1_mask_b;
uint8_t reg_md_srcclkena2infra_req_1_mask_b;
uint8_t reg_md_apsrc2infra_req_1_mask_b;
uint8_t reg_md_apsrc_req_1_mask_b;
uint8_t reg_md_vrf18_req_1_mask_b;
uint8_t reg_md_ddr_en_1_mask_b;
uint8_t reg_conn_srcclkena_mask_b;
uint8_t reg_conn_srcclkenb_mask_b;
uint8_t reg_conn_infra_req_mask_b;
uint8_t reg_conn_apsrc_req_mask_b;
uint8_t reg_conn_vrf18_req_mask_b;
uint8_t reg_conn_ddr_en_mask_b;
uint8_t reg_conn_vfe28_mask_b;
uint8_t reg_srcclkeni0_srcclkena_mask_b;
uint8_t reg_srcclkeni0_infra_req_mask_b;
uint8_t reg_srcclkeni1_srcclkena_mask_b;
uint8_t reg_srcclkeni1_infra_req_mask_b;
uint8_t reg_srcclkeni2_srcclkena_mask_b;
uint8_t reg_srcclkeni2_infra_req_mask_b;
uint8_t reg_infrasys_apsrc_req_mask_b;
uint8_t reg_infrasys_ddr_en_mask_b;
uint8_t reg_md32_srcclkena_mask_b;
uint8_t reg_md32_infra_req_mask_b;
uint8_t reg_md32_apsrc_req_mask_b;
uint8_t reg_md32_vrf18_req_mask_b;
uint8_t reg_md32_ddr_en_mask_b;
/* SPM_SRC2_MASK */
uint8_t reg_scp_srcclkena_mask_b;
uint8_t reg_scp_infra_req_mask_b;
uint8_t reg_scp_apsrc_req_mask_b;
uint8_t reg_scp_vrf18_req_mask_b;
uint8_t reg_scp_ddr_en_mask_b;
uint8_t reg_audio_dsp_srcclkena_mask_b;
uint8_t reg_audio_dsp_infra_req_mask_b;
uint8_t reg_audio_dsp_apsrc_req_mask_b;
uint8_t reg_audio_dsp_vrf18_req_mask_b;
uint8_t reg_audio_dsp_ddr_en_mask_b;
uint8_t reg_ufs_srcclkena_mask_b;
uint8_t reg_ufs_infra_req_mask_b;
uint8_t reg_ufs_apsrc_req_mask_b;
uint8_t reg_ufs_vrf18_req_mask_b;
uint8_t reg_ufs_ddr_en_mask_b;
uint8_t reg_disp0_apsrc_req_mask_b;
uint8_t reg_disp0_ddr_en_mask_b;
uint8_t reg_disp1_apsrc_req_mask_b;
uint8_t reg_disp1_ddr_en_mask_b;
uint8_t reg_gce_infra_req_mask_b;
uint8_t reg_gce_apsrc_req_mask_b;
uint8_t reg_gce_vrf18_req_mask_b;
uint8_t reg_gce_ddr_en_mask_b;
uint8_t reg_apu_srcclkena_mask_b;
uint8_t reg_apu_infra_req_mask_b;
uint8_t reg_apu_apsrc_req_mask_b;
uint8_t reg_apu_vrf18_req_mask_b;
uint8_t reg_apu_ddr_en_mask_b;
uint8_t reg_cg_check_srcclkena_mask_b;
uint8_t reg_cg_check_apsrc_req_mask_b;
uint8_t reg_cg_check_vrf18_req_mask_b;
uint8_t reg_cg_check_ddr_en_mask_b;
/* SPM_SRC3_MASK */
uint8_t reg_dvfsrc_event_trigger_mask_b;
uint8_t reg_sw2spm_int0_mask_b;
uint8_t reg_sw2spm_int1_mask_b;
uint8_t reg_sw2spm_int2_mask_b;
uint8_t reg_sw2spm_int3_mask_b;
uint8_t reg_sc_adsp2spm_wakeup_mask_b;
uint8_t reg_sc_sspm2spm_wakeup_mask_b;
uint8_t reg_sc_scp2spm_wakeup_mask_b;
uint8_t reg_csyspwrreq_mask;
uint8_t reg_spm_srcclkena_reserved_mask_b;
uint8_t reg_spm_infra_req_reserved_mask_b;
uint8_t reg_spm_apsrc_req_reserved_mask_b;
uint8_t reg_spm_vrf18_req_reserved_mask_b;
uint8_t reg_spm_ddr_en_reserved_mask_b;
uint8_t reg_mcupm_srcclkena_mask_b;
uint8_t reg_mcupm_infra_req_mask_b;
uint8_t reg_mcupm_apsrc_req_mask_b;
uint8_t reg_mcupm_vrf18_req_mask_b;
uint8_t reg_mcupm_ddr_en_mask_b;
uint8_t reg_msdc0_srcclkena_mask_b;
uint8_t reg_msdc0_infra_req_mask_b;
uint8_t reg_msdc0_apsrc_req_mask_b;
uint8_t reg_msdc0_vrf18_req_mask_b;
uint8_t reg_msdc0_ddr_en_mask_b;
uint8_t reg_msdc1_srcclkena_mask_b;
uint8_t reg_msdc1_infra_req_mask_b;
uint8_t reg_msdc1_apsrc_req_mask_b;
uint8_t reg_msdc1_vrf18_req_mask_b;
uint8_t reg_msdc1_ddr_en_mask_b;
/* SPM_SRC4_MASK */
uint32_t ccif_event_mask_b;
uint8_t reg_bak_psri_srcclkena_mask_b;
uint8_t reg_bak_psri_infra_req_mask_b;
uint8_t reg_bak_psri_apsrc_req_mask_b;
uint8_t reg_bak_psri_vrf18_req_mask_b;
uint8_t reg_bak_psri_ddr_en_mask_b;
uint8_t reg_dramc0_md32_infra_req_mask_b;
uint8_t reg_dramc0_md32_vrf18_req_mask_b;
uint8_t reg_dramc1_md32_infra_req_mask_b;
uint8_t reg_dramc1_md32_vrf18_req_mask_b;
uint8_t reg_conn_srcclkenb2pwrap_mask_b;
uint8_t reg_dramc0_md32_wakeup_mask;
uint8_t reg_dramc1_md32_wakeup_mask;
/* SPM_SRC5_MASK */
uint32_t reg_mcusys_merge_apsrc_req_mask_b;
uint32_t reg_mcusys_merge_ddr_en_mask_b;
uint8_t reg_msdc2_srcclkena_mask_b;
uint8_t reg_msdc2_infra_req_mask_b;
uint8_t reg_msdc2_apsrc_req_mask_b;
uint8_t reg_msdc2_vrf18_req_mask_b;
uint8_t reg_msdc2_ddr_en_mask_b;
uint8_t reg_pcie_srcclkena_mask_b;
uint8_t reg_pcie_infra_req_mask_b;
uint8_t reg_pcie_apsrc_req_mask_b;
uint8_t reg_pcie_vrf18_req_mask_b;
uint8_t reg_pcie_ddr_en_mask_b;
/* SPM_WAKEUP_EVENT_MASK */
uint32_t reg_wakeup_event_mask;
/* SPM_WAKEUP_EVENT_EXT_MASK */
uint32_t reg_ext_wakeup_event_mask;
/* Auto-gen End */
};
/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
enum pwr_ctrl_enum {
PW_PCM_FLAGS,
PW_PCM_FLAGS_CUST,
PW_PCM_FLAGS_CUST_SET,
PW_PCM_FLAGS_CUST_CLR,
PW_PCM_FLAGS1,
PW_PCM_FLAGS1_CUST,
PW_PCM_FLAGS1_CUST_SET,
PW_PCM_FLAGS1_CUST_CLR,
PW_TIMER_VAL,
PW_TIMER_VAL_CUST,
PW_TIMER_VAL_RAMP_EN,
PW_TIMER_VAL_RAMP_EN_SEC,
PW_WAKE_SRC,
PW_WAKE_SRC_CUST,
PW_WAKELOCK_TIMER_VAL,
PW_WDT_DISABLE,
/* SPM_CLK_CON */
PW_REG_SRCCLKEN0_CTL,
PW_REG_SRCCLKEN1_CTL,
PW_REG_SPM_LOCK_INFRA_DCM,
PW_REG_SRCCLKEN_MASK,
PW_REG_MD1_C32RM_EN,
PW_REG_MD2_C32RM_EN,
PW_REG_CLKSQ0_SEL_CTRL,
PW_REG_CLKSQ1_SEL_CTRL,
PW_REG_SRCCLKEN0_EN,
PW_REG_SRCCLKEN1_EN,
PW_REG_SYSCLK0_SRC_MASK_B,
PW_REG_SYSCLK1_SRC_MASK_B,
/* SPM_AP_STANDBY_CON */
PW_REG_WFI_OP,
PW_REG_WFI_TYPE,
PW_REG_MP0_CPUTOP_IDLE_MASK,
PW_REG_MP1_CPUTOP_IDLE_MASK,
PW_REG_MCUSYS_IDLE_MASK,
PW_REG_MD_APSRC_1_SEL,
PW_REG_MD_APSRC_0_SEL,
PW_REG_CONN_APSRC_SEL,
/* SPM_SRC6_MASK */
PW_REG_DPMAIF_SRCCLKENA_MASK_B,
PW_REG_DPMAIF_INFRA_REQ_MASK_B,
PW_REG_DPMAIF_APSRC_REQ_MASK_B,
PW_REG_DPMAIF_VRF18_REQ_MASK_B,
PW_REG_DPMAIF_DDR_EN_MASK_B,
/* SPM_SRC_REQ */
PW_REG_SPM_APSRC_REQ,
PW_REG_SPM_F26M_REQ,
PW_REG_SPM_INFRA_REQ,
PW_REG_SPM_VRF18_REQ,
PW_REG_SPM_DDR_EN_REQ,
PW_REG_SPM_DVFS_REQ,
PW_REG_SPM_SW_MAILBOX_REQ,
PW_REG_SPM_SSPM_MAILBOX_REQ,
PW_REG_SPM_ADSP_MAILBOX_REQ,
PW_REG_SPM_SCP_MAILBOX_REQ,
/* SPM_SRC_MASK */
PW_REG_MD_SRCCLKENA_0_MASK_B,
PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B,
PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B,
PW_REG_MD_APSRC_REQ_0_MASK_B,
PW_REG_MD_VRF18_REQ_0_MASK_B,
PW_REG_MD_DDR_EN_0_MASK_B,
PW_REG_MD_SRCCLKENA_1_MASK_B,
PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B,
PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B,
PW_REG_MD_APSRC_REQ_1_MASK_B,
PW_REG_MD_VRF18_REQ_1_MASK_B,
PW_REG_MD_DDR_EN_1_MASK_B,
PW_REG_CONN_SRCCLKENA_MASK_B,
PW_REG_CONN_SRCCLKENB_MASK_B,
PW_REG_CONN_INFRA_REQ_MASK_B,
PW_REG_CONN_APSRC_REQ_MASK_B,
PW_REG_CONN_VRF18_REQ_MASK_B,
PW_REG_CONN_DDR_EN_MASK_B,
PW_REG_CONN_VFE28_MASK_B,
PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B,
PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B,
PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B,
PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B,
PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B,
PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B,
PW_REG_INFRASYS_APSRC_REQ_MASK_B,
PW_REG_INFRASYS_DDR_EN_MASK_B,
PW_REG_MD32_SRCCLKENA_MASK_B,
PW_REG_MD32_INFRA_REQ_MASK_B,
PW_REG_MD32_APSRC_REQ_MASK_B,
PW_REG_MD32_VRF18_REQ_MASK_B,
PW_REG_MD32_DDR_EN_MASK_B,
/* SPM_SRC2_MASK */
PW_REG_SCP_SRCCLKENA_MASK_B,
PW_REG_SCP_INFRA_REQ_MASK_B,
PW_REG_SCP_APSRC_REQ_MASK_B,
PW_REG_SCP_VRF18_REQ_MASK_B,
PW_REG_SCP_DDR_EN_MASK_B,
PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
PW_REG_UFS_SRCCLKENA_MASK_B,
PW_REG_UFS_INFRA_REQ_MASK_B,
PW_REG_UFS_APSRC_REQ_MASK_B,
PW_REG_UFS_VRF18_REQ_MASK_B,
PW_REG_UFS_DDR_EN_MASK_B,
PW_REG_DISP0_APSRC_REQ_MASK_B,
PW_REG_DISP0_DDR_EN_MASK_B,
PW_REG_DISP1_APSRC_REQ_MASK_B,
PW_REG_DISP1_DDR_EN_MASK_B,
PW_REG_GCE_INFRA_REQ_MASK_B,
PW_REG_GCE_APSRC_REQ_MASK_B,
PW_REG_GCE_VRF18_REQ_MASK_B,
PW_REG_GCE_DDR_EN_MASK_B,
PW_REG_APU_SRCCLKENA_MASK_B,
PW_REG_APU_INFRA_REQ_MASK_B,
PW_REG_APU_APSRC_REQ_MASK_B,
PW_REG_APU_VRF18_REQ_MASK_B,
PW_REG_APU_DDR_EN_MASK_B,
PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
PW_REG_CG_CHECK_DDR_EN_MASK_B,
/* SPM_SRC3_MASK */
PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
PW_REG_SW2SPM_INT0_MASK_B,
PW_REG_SW2SPM_INT1_MASK_B,
PW_REG_SW2SPM_INT2_MASK_B,
PW_REG_SW2SPM_INT3_MASK_B,
PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
PW_REG_CSYSPWRREQ_MASK,
PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
PW_REG_MCUPM_SRCCLKENA_MASK_B,
PW_REG_MCUPM_INFRA_REQ_MASK_B,
PW_REG_MCUPM_APSRC_REQ_MASK_B,
PW_REG_MCUPM_VRF18_REQ_MASK_B,
PW_REG_MCUPM_DDR_EN_MASK_B,
PW_REG_MSDC0_SRCCLKENA_MASK_B,
PW_REG_MSDC0_INFRA_REQ_MASK_B,
PW_REG_MSDC0_APSRC_REQ_MASK_B,
PW_REG_MSDC0_VRF18_REQ_MASK_B,
PW_REG_MSDC0_DDR_EN_MASK_B,
PW_REG_MSDC1_SRCCLKENA_MASK_B,
PW_REG_MSDC1_INFRA_REQ_MASK_B,
PW_REG_MSDC1_APSRC_REQ_MASK_B,
PW_REG_MSDC1_VRF18_REQ_MASK_B,
PW_REG_MSDC1_DDR_EN_MASK_B,
/* SPM_SRC4_MASK */
PW_CCIF_EVENT_MASK_B,
PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
PW_REG_BAK_PSRI_DDR_EN_MASK_B,
PW_REG_DRAMC0_MD32_INFRA_REQ_MASK_B,
PW_REG_DRAMC0_MD32_VRF18_REQ_MASK_B,
PW_REG_DRAMC1_MD32_INFRA_REQ_MASK_B,
PW_REG_DRAMC1_MD32_VRF18_REQ_MASK_B,
PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
PW_REG_DRAMC0_MD32_WAKEUP_MASK,
PW_REG_DRAMC1_MD32_WAKEUP_MASK,
/* SPM_SRC5_MASK */
PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
PW_REG_MSDC2_SRCCLKENA_MASK_B,
PW_REG_MSDC2_INFRA_REQ_MASK_B,
PW_REG_MSDC2_APSRC_REQ_MASK_B,
PW_REG_MSDC2_VRF18_REQ_MASK_B,
PW_REG_MSDC2_DDR_EN_MASK_B,
PW_REG_PCIE_SRCCLKENA_MASK_B,
PW_REG_PCIE_INFRA_REQ_MASK_B,
PW_REG_PCIE_APSRC_REQ_MASK_B,
PW_REG_PCIE_VRF18_REQ_MASK_B,
PW_REG_PCIE_DDR_EN_MASK_B,
/* SPM_WAKEUP_EVENT_MASK */
PW_REG_WAKEUP_EVENT_MASK,
/* SPM_WAKEUP_EVENT_EXT_MASK */
PW_REG_EXT_WAKEUP_EVENT_MASK,
PW_MAX_COUNT,
};
#define SPM_INTERNAL_STATUS_HW_S1 (1U << 0)
#define SPM_ACK_CHK_3_SEL_HW_S1 0x00350098
#define SPM_ACK_CHK_3_HW_S1_CNT 1
#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG 0x800
#define SPM_ACK_CHK_3_CON_EN 0x110
#define SPM_ACK_CHK_3_CON_CLR_ALL 0x2
#define SPM_ACK_CHK_3_CON_RESULT 0x8000
struct wake_status_trace_comm {
uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
uint32_t timer_out; /* SPM_SW_RSV_6*/
uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
uint32_t b_sw_flag1; /* SPM_SW_RSV_7 */
uint32_t r12; /* SPM_SW_RSV_0 */
uint32_t r13; /* PCM_REG13_DATA */
uint32_t req_sta0; /* SRC_REQ_STA_0 */
uint32_t req_sta1; /* SRC_REQ_STA_1 */
uint32_t req_sta2; /* SRC_REQ_STA_2 */
uint32_t req_sta3; /* SRC_REQ_STA_3 */
uint32_t req_sta4; /* SRC_REQ_STA_4 */
};
struct wake_status_trace {
struct wake_status_trace_comm comm;
};
struct wake_status {
struct wake_status_trace tr;
uint32_t r12; /* SPM_BK_WAKE_EVENT */
uint32_t r12_ext; /* SPM_WAKEUP_EXT_STA */
uint32_t raw_sta; /* SPM_WAKEUP_STA */
uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */
uint32_t md32pcm_wakeup_sta; /* MD32CPM_WAKEUP_STA */
uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */
uint32_t wake_misc; /* SPM_BK_WAKE_MISC */
uint32_t timer_out; /* SPM_BK_PCM_TIMER */
uint32_t r13; /* PCM_REG13_DATA */
uint32_t idle_sta; /* SUBSYS_IDLE_STA */
uint32_t req_sta0; /* SRC_REQ_STA_0 */
uint32_t req_sta1; /* SRC_REQ_STA_1 */
uint32_t req_sta2; /* SRC_REQ_STA_2 */
uint32_t req_sta3; /* SRC_REQ_STA_3 */
uint32_t req_sta4; /* SRC_REQ_STA_4 */
uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */
uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
uint32_t b_sw_flag1; /* SPM_SW_RSV_8 */
uint32_t isr; /* SPM_IRQ_STA */
uint32_t sw_flag0; /* SPM_SW_FLAG_0 */
uint32_t sw_flag1; /* SPM_SW_FLAG_1 */
uint32_t clk_settle; /* SPM_CLK_SETTLE */
uint32_t src_req; /* SPM_SRC_REQ */
uint32_t log_index;
uint32_t abort;
uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */
uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */
uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */
uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */
uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */
uint32_t mcupm_req_sta;
};
struct spm_lp_scen {
struct pcm_desc *pcmdesc;
struct pwr_ctrl *pwrctrl;
};
extern struct spm_lp_scen __spm_vcorefs;
extern void __spm_set_cpu_status(unsigned int cpu);
extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc);
extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
extern void __spm_init_pcm_register(void);
extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
unsigned int resource_usage);
extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
extern void __spm_disable_pcm_timer(void);
extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
extern void __spm_send_cpu_wakeup_event(void);
extern void __spm_get_wakeup_status(struct wake_status *wakesta,
unsigned int ext_status);
extern void __spm_clean_after_wakeup(void);
extern wake_reason_t
__spm_output_wake_reason(int state_id, const struct wake_status *wakesta);
extern void
__spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
const struct pwr_ctrl *src_pwr_ctrl);
extern void __spm_set_pcm_wdt(int en);
extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr);
extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl);
extern void __spm_ext_int_wakeup_req_clr(void);
extern void __spm_xo_soc_bblpm(int en);
static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
uint32_t flags)
{
if (pwrctrl->pcm_flags_cust == 0U) {
pwrctrl->pcm_flags = flags;
} else {
pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
}
}
static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl,
uint32_t flags)
{
if (pwrctrl->pcm_flags1_cust == 0U) {
pwrctrl->pcm_flags1 = flags;
} else {
pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust;
}
}
extern void __spm_hw_s1_state_monitor(int en, unsigned int *status);
static inline void spm_hw_s1_state_monitor_resume(void)
{
__spm_hw_s1_state_monitor(1, NULL);
}
static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
{
__spm_hw_s1_state_monitor(0, status);
}
#endif /* MT_SPM_INTERNAL_H */
plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.c 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <string.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_internal.h>
#include <mt_spm_pmic_wrap.h>
#include <mt_spm_reg.h>
#include <plat_pm.h>
#include <platform_def.h>
/* PMIC_WRAP MT6359 */
#define VCORE_BASE_UV 40000
#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV)
#define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
#define SPM_DATA_SHIFT 16
#define BUCK_VGPU11_ELR0 0x15B4
#define TOP_SPI_CON0 0x0456
#define BUCK_TOP_CON1 0x1443
#define TOP_CON 0x0013
#define TOP_DIG_WPK 0x03a9
#define TOP_CON_LOCK 0x03a8
#define TOP_CLK_CON0 0x0134
struct pmic_wrap_cmd {
unsigned long cmd_addr;
unsigned long cmd_wdata;
};
struct pmic_wrap_setting {
enum pmic_wrap_phase_id phase;
struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
struct {
struct {
unsigned long cmd_addr;
unsigned long cmd_wdata;
} _[NR_PMIC_WRAP_CMD];
const int nr_idx;
} set[NR_PMIC_WRAP_PHASE];
};
static struct pmic_wrap_setting pw = {
.phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
.addr = { {0UL, 0UL} },
.set[PMIC_WRAP_PHASE_ALLINONE] = {
._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(72500),},
._[CMD_1] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),},
._[CMD_2] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),},
._[CMD_3] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(57500),},
._[CMD_4] = {TOP_SPI_CON0, 0x1,},
._[CMD_5] = {TOP_SPI_CON0, 0x0,},
._[CMD_6] = {BUCK_TOP_CON1, 0x0,},
._[CMD_7] = {BUCK_TOP_CON1, 0xf,},
._[CMD_8] = {TOP_CON, 0x3,},
._[CMD_9] = {TOP_CON, 0x0,},
._[CMD_10] = {TOP_DIG_WPK, 0x63,},
._[CMD_11] = {TOP_CON_LOCK, 0x15,},
._[CMD_12] = {TOP_DIG_WPK, 0x0,},
._[CMD_13] = {TOP_CON_LOCK, 0x0,},
._[CMD_14] = {TOP_CLK_CON0, 0x40,},
._[CMD_15] = {TOP_CLK_CON0, 0x0,},
.nr_idx = NR_IDX_ALL,
},
};
void _mt_spm_pmic_table_init(void)
{
struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
{(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,},
{(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,},
{(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,},
{(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,},
{(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,},
{(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,},
{(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,},
{(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,},
{(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,},
{(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,},
{(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,},
{(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,},
{(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,},
{(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,},
{(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,},
{(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,},
};
memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
}
void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
{
uint32_t idx, addr, data;
if (phase >= NR_PMIC_WRAP_PHASE) {
return;
}
if (pw.phase == phase) {
return;
}
if (pw.addr[0].cmd_addr == 0UL) {
_mt_spm_pmic_table_init();
}
pw.phase = phase;
mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) {
addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
data = pw.set[phase]._[idx].cmd_wdata;
mmio_write_32(pw.addr[idx].cmd_addr, addr | data);
}
}
void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
uint32_t cmd_wdata)
{
uint32_t addr;
if (phase >= NR_PMIC_WRAP_PHASE) {
return;
}
if (idx >= pw.set[phase].nr_idx) {
return;
}
pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
if (pw.phase == phase) {
addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata);
}
}
uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
{
if (phase >= NR_PMIC_WRAP_PHASE) {
return 0UL;
}
if (idx >= pw.set[phase].nr_idx) {
return 0UL;
}
return pw.set[phase]._[idx].cmd_wdata;
}
plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/****************************************************************
* Auto generated by DE, please DO NOT modify this file directly.
*****************************************************************/
#ifndef MT_SPM_PMIC_WRAP_H
#define MT_SPM_PMIC_WRAP_H
enum pmic_wrap_phase_id {
PMIC_WRAP_PHASE_ALLINONE,
NR_PMIC_WRAP_PHASE,
};
/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
enum {
CMD_0, /* 0x0 */
CMD_1, /* 0x1 */
CMD_2, /* 0x2 */
CMD_3, /* 0x3 */
CMD_4, /* 0x4 */
CMD_5, /* 0x5 */
CMD_6, /* 0x6 */
CMD_7, /* 0x7 */
CMD_8, /* 0x8 */
CMD_9, /* 0x9 */
CMD_10, /* 0xA */
CMD_11, /* 0xB */
CMD_12, /* 0xC */
CMD_13, /* 0xD */
CMD_14, /* 0xE */
CMD_15, /* 0xF */
NR_IDX_ALL,
};
/* APIs */
extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
uint32_t idx, uint32_t cmd_wdata);
extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
uint32_t idx);
#endif /* MT_SPM_PMIC_WRAP_H */
plat/mediatek/mt8192/drivers/spm/mt_spm_reg.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/****************************************************************
* Auto generated by DE, please DO NOT modify this file directly.
*****************************************************************/
#ifndef MT_SPM_REG
#define MT_SPM_REG
#include "pcm_def.h"
#include <platform_def.h>
#include "sleep_def.h"
/**************************************
* Define and Declare
**************************************/
#define POWERON_CONFIG_EN (SPM_BASE + 0x000)
#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
#define SPM_CLK_CON (SPM_BASE + 0x00C)
#define SPM_CLK_SETTLE (SPM_BASE + 0x010)
#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
#define PCM_CON0 (SPM_BASE + 0x018)
#define PCM_CON1 (SPM_BASE + 0x01C)
#define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
#define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024)
#define PCM_REG_DATA_INI (SPM_BASE + 0x028)
#define PCM_PWR_IO_EN (SPM_BASE + 0x02C)
#define PCM_TIMER_VAL (SPM_BASE + 0x030)
#define PCM_WDT_VAL (SPM_BASE + 0x034)
#define SPM_SRC6_MASK (SPM_BASE + 0x038)
#define SPM_SW_RST_CON (SPM_BASE + 0x040)
#define SPM_SW_RST_CON_SET (SPM_BASE + 0x044)
#define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048)
#define VS1_PSR_MASK_B (SPM_BASE + 0x04C)
#define VS2_PSR_MASK_B (SPM_BASE + 0x050)
#define MD32_CLK_CON (SPM_BASE + 0x084)
#define SPM_SRAM_RSV_CON (SPM_BASE + 0x088)
#define SPM_SWINT (SPM_BASE + 0x08C)
#define SPM_SWINT_SET (SPM_BASE + 0x090)
#define SPM_SWINT_CLR (SPM_BASE + 0x094)
#define SPM_SCP_MAILBOX (SPM_BASE + 0x098)
#define SCP_SPM_MAILBOX (SPM_BASE + 0x09C)
#define SPM_TWAM_CON (SPM_BASE + 0x0A0)
#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4)
#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8)
#define SPM_SCP_IRQ (SPM_BASE + 0x0AC)
#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0)
#define SPM_IRQ_MASK (SPM_BASE + 0x0B4)
#define SPM_SRC_REQ (SPM_BASE + 0x0B8)
#define SPM_SRC_MASK (SPM_BASE + 0x0BC)
#define SPM_SRC2_MASK (SPM_BASE + 0x0C0)
#define SPM_SRC3_MASK (SPM_BASE + 0x0C4)
#define SPM_SRC4_MASK (SPM_BASE + 0x0C8)
#define SPM_SRC5_MASK (SPM_BASE + 0x0CC)
#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0D0)
#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0D4)
#define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x0D8)
#define SCP_CLK_CON (SPM_BASE + 0x0DC)
#define PCM_DEBUG_CON (SPM_BASE + 0x0E0)
#define AHB_BUS_CON (SPM_BASE + 0x0E4)
#define DDR_EN_DBC_CON0 (SPM_BASE + 0x0E8)
#define DDR_EN_DBC_CON1 (SPM_BASE + 0x0EC)
#define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x0F0)
#define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x0F4)
#define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x0F8)
#define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x0FC)
#define PCM_REG0_DATA (SPM_BASE + 0x100)
#define PCM_REG2_DATA (SPM_BASE + 0x104)
#define PCM_REG6_DATA (SPM_BASE + 0x108)
#define PCM_REG7_DATA (SPM_BASE + 0x10C)
#define PCM_REG13_DATA (SPM_BASE + 0x110)
#define SRC_REQ_STA_0 (SPM_BASE + 0x114)
#define SRC_REQ_STA_1 (SPM_BASE + 0x118)
#define SRC_REQ_STA_2 (SPM_BASE + 0x11C)
#define PCM_TIMER_OUT (SPM_BASE + 0x120)
#define PCM_WDT_OUT (SPM_BASE + 0x124)
#define SPM_IRQ_STA (SPM_BASE + 0x128)
#define SRC_REQ_STA_4 (SPM_BASE + 0x12C)
#define MD32PCM_WAKEUP_STA (SPM_BASE + 0x130)
#define MD32PCM_EVENT_STA (SPM_BASE + 0x134)
#define SPM_WAKEUP_STA (SPM_BASE + 0x138)
#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x13C)
#define SPM_WAKEUP_MISC (SPM_BASE + 0x140)
#define MM_DVFS_HALT (SPM_BASE + 0x144)
#define BUS_PROTECT_RDY (SPM_BASE + 0x150)
#define BUS_PROTECT1_RDY (SPM_BASE + 0x154)
#define BUS_PROTECT2_RDY (SPM_BASE + 0x158)
#define BUS_PROTECT3_RDY (SPM_BASE + 0x15C)
#define SUBSYS_IDLE_STA (SPM_BASE + 0x160)
#define PCM_STA (SPM_BASE + 0x164)
#define SRC_REQ_STA_3 (SPM_BASE + 0x168)
#define PWR_STATUS (SPM_BASE + 0x16C)
#define PWR_STATUS_2ND (SPM_BASE + 0x170)
#define CPU_PWR_STATUS (SPM_BASE + 0x174)
#define OTHER_PWR_STATUS (SPM_BASE + 0x178)
#define SPM_VTCXO_EVENT_COUNT_STA (SPM_BASE + 0x17C)
#define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x180)
#define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x184)
#define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x188)
#define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x18C)
#define MD32PCM_STA (SPM_BASE + 0x190)
#define MD32PCM_PC (SPM_BASE + 0x194)
#define DVFSRC_EVENT_STA (SPM_BASE + 0x1A4)
#define BUS_PROTECT4_RDY (SPM_BASE + 0x1A8)
#define BUS_PROTECT5_RDY (SPM_BASE + 0x1AC)
#define BUS_PROTECT6_RDY (SPM_BASE + 0x1B0)
#define BUS_PROTECT7_RDY (SPM_BASE + 0x1B4)
#define BUS_PROTECT8_RDY (SPM_BASE + 0x1B8)
#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1D0)
#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1D4)
#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1D8)
#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1DC)
#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1E0)
#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1E4)
#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1E8)
#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1EC)
#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1F0)
#define SPM_CG_CHECK_STA (SPM_BASE + 0x1F4)
#define SPM_DVFS_STA (SPM_BASE + 0x1F8)
#define SPM_DVFS_OPP_STA (SPM_BASE + 0x1FC)
#define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x200)
#define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x204)
#define SPM_CPU0_PWR_CON (SPM_BASE + 0x208)
#define SPM_CPU1_PWR_CON (SPM_BASE + 0x20C)
#define SPM_CPU2_PWR_CON (SPM_BASE + 0x210)
#define SPM_CPU3_PWR_CON (SPM_BASE + 0x214)
#define SPM_CPU4_PWR_CON (SPM_BASE + 0x218)
#define SPM_CPU5_PWR_CON (SPM_BASE + 0x21C)
#define SPM_CPU6_PWR_CON (SPM_BASE + 0x220)
#define SPM_CPU7_PWR_CON (SPM_BASE + 0x224)
#define ARMPLL_CLK_CON (SPM_BASE + 0x22C)
#define MCUSYS_IDLE_STA (SPM_BASE + 0x230)
#define GIC_WAKEUP_STA (SPM_BASE + 0x234)
#define CPU_SPARE_CON (SPM_BASE + 0x238)
#define CPU_SPARE_CON_SET (SPM_BASE + 0x23C)
#define CPU_SPARE_CON_CLR (SPM_BASE + 0x240)
#define ARMPLL_CLK_SEL (SPM_BASE + 0x244)
#define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x248)
#define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x24C)
#define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x250)
#define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x260)
#define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x264)
#define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x268)
#define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x26C)
#define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x270)
#define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x274)
#define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x278)
#define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x27C)
#define MP0_CPU0_WFI_EN (SPM_BASE + 0x280)
#define MP0_CPU1_WFI_EN (SPM_BASE + 0x284)
#define MP0_CPU2_WFI_EN (SPM_BASE + 0x288)
#define MP0_CPU3_WFI_EN (SPM_BASE + 0x28C)
#define MP0_CPU4_WFI_EN (SPM_BASE + 0x290)
#define MP0_CPU5_WFI_EN (SPM_BASE + 0x294)
#define MP0_CPU6_WFI_EN (SPM_BASE + 0x298)
#define MP0_CPU7_WFI_EN (SPM_BASE + 0x29C)
#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0)
#define ROOT_CORE_ADDR (SPM_BASE + 0x2A4)
#define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0)
#define SPM2SW_MAILBOX_1 (SPM_BASE + 0x2D4)
#define SPM2SW_MAILBOX_2 (SPM_BASE + 0x2D8)
#define SPM2SW_MAILBOX_3 (SPM_BASE + 0x2DC)
#define SW2SPM_INT (SPM_BASE + 0x2E0)
#define SW2SPM_INT_SET (SPM_BASE + 0x2E4)
#define SW2SPM_INT_CLR (SPM_BASE + 0x2E8)
#define SW2SPM_MAILBOX_0 (SPM_BASE + 0x2EC)
#define SW2SPM_MAILBOX_1 (SPM_BASE + 0x2F0)
#define SW2SPM_MAILBOX_2 (SPM_BASE + 0x2F4)
#define SW2SPM_MAILBOX_3 (SPM_BASE + 0x2F8)
#define SW2SPM_CFG (SPM_BASE + 0x2FC)
#define MD1_PWR_CON (SPM_BASE + 0x300)
#define CONN_PWR_CON (SPM_BASE + 0x304)
#define MFG0_PWR_CON (SPM_BASE + 0x308)
#define MFG1_PWR_CON (SPM_BASE + 0x30C)
#define MFG2_PWR_CON (SPM_BASE + 0x310)
#define MFG3_PWR_CON (SPM_BASE + 0x314)
#define MFG4_PWR_CON (SPM_BASE + 0x318)
#define MFG5_PWR_CON (SPM_BASE + 0x31C)
#define MFG6_PWR_CON (SPM_BASE + 0x320)
#define IFR_PWR_CON (SPM_BASE + 0x324)
#define IFR_SUB_PWR_CON (SPM_BASE + 0x328)
#define DPY_PWR_CON (SPM_BASE + 0x32C)
#define ISP_PWR_CON (SPM_BASE + 0x330)
#define ISP2_PWR_CON (SPM_BASE + 0x334)
#define IPE_PWR_CON (SPM_BASE + 0x338)
#define VDE_PWR_CON (SPM_BASE + 0x33C)
#define VDE2_PWR_CON (SPM_BASE + 0x340)
#define VEN_PWR_CON (SPM_BASE + 0x344)
#define VEN_CORE1_PWR_CON (SPM_BASE + 0x348)
#define MDP_PWR_CON (SPM_BASE + 0x34C)
#define DIS_PWR_CON (SPM_BASE + 0x350)
#define AUDIO_PWR_CON (SPM_BASE + 0x354)
#define ADSP_PWR_CON (SPM_BASE + 0x358)
#define CAM_PWR_CON (SPM_BASE + 0x35C)
#define CAM_RAWA_PWR_CON (SPM_BASE + 0x360)
#define CAM_RAWB_PWR_CON (SPM_BASE + 0x364)
#define CAM_RAWC_PWR_CON (SPM_BASE + 0x368)
#define SYSRAM_CON (SPM_BASE + 0x36C)
#define SYSROM_CON (SPM_BASE + 0x370)
#define SSPM_SRAM_CON (SPM_BASE + 0x374)
#define SCP_SRAM_CON (SPM_BASE + 0x378)
#define DPY_SHU_SRAM_CON (SPM_BASE + 0x37C)
#define UFS_SRAM_CON (SPM_BASE + 0x380)
#define DEVAPC_IFR_SRAM_CON (SPM_BASE + 0x384)
#define DEVAPC_SUBIFR_SRAM_CON (SPM_BASE + 0x388)
#define DEVAPC_ACP_SRAM_CON (SPM_BASE + 0x38C)
#define USB_SRAM_CON (SPM_BASE + 0x390)
#define DUMMY_SRAM_CON (SPM_BASE + 0x394)
#define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x398)
#define EXT_BUCK_ISO (SPM_BASE + 0x39C)
#define DXCC_SRAM_CON (SPM_BASE + 0x3A0)
#define MSDC_SRAM_CON (SPM_BASE + 0x3A4)
#define DEBUGTOP_SRAM_CON (SPM_BASE + 0x3A8)
#define DP_TX_PWR_CON (SPM_BASE + 0x3AC)
#define DPMAIF_SRAM_CON (SPM_BASE + 0x3B0)
#define DPY_SHU2_SRAM_CON (SPM_BASE + 0x3B4)
#define DRAMC_MCU2_SRAM_CON (SPM_BASE + 0x3B8)
#define DRAMC_MCU_SRAM_CON (SPM_BASE + 0x3BC)
#define MCUPM_SRAM_CON (SPM_BASE + 0x3C0)
#define DPY2_PWR_CON (SPM_BASE + 0x3C4)
#define PERI_PWR_CON (SPM_BASE + 0x3C8)
#define SPM_MEM_CK_SEL (SPM_BASE + 0x400)
#define SPM_BUS_PROTECT_MASK_B (SPM_BASE + 0x404)
#define SPM_BUS_PROTECT1_MASK_B (SPM_BASE + 0x408)
#define SPM_BUS_PROTECT2_MASK_B (SPM_BASE + 0x40C)
#define SPM_BUS_PROTECT3_MASK_B (SPM_BASE + 0x410)
#define SPM_BUS_PROTECT4_MASK_B (SPM_BASE + 0x414)
#define SPM_EMI_BW_MODE (SPM_BASE + 0x418)
#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x41C)
#define ULPOSC_CON (SPM_BASE + 0x420)
#define SPM2MM_CON (SPM_BASE + 0x424)
#define SPM_BUS_PROTECT5_MASK_B (SPM_BASE + 0x428)
#define SPM2MCUPM_CON (SPM_BASE + 0x42C)
#define AP_MDSRC_REQ (SPM_BASE + 0x430)
#define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x434)
#define SPM2MD_DVFS_CON (SPM_BASE + 0x438)
#define MD2SPM_DVFS_CON (SPM_BASE + 0x43C)
#define SPM_BUS_PROTECT6_MASK_B (SPM_BASE + 0x440)
#define SPM_BUS_PROTECT7_MASK_B (SPM_BASE + 0x444)
#define SPM_BUS_PROTECT8_MASK_B (SPM_BASE + 0x448)
#define SPM_PLL_CON (SPM_BASE + 0x44C)
#define CPU_DVFS_REQ (SPM_BASE + 0x450)
#define SPM_DRAM_MCU_SW_CON_0 (SPM_BASE + 0x454)
#define SPM_DRAM_MCU_SW_CON_1 (SPM_BASE + 0x458)
#define SPM_DRAM_MCU_SW_CON_2 (SPM_BASE + 0x45C)
#define SPM_DRAM_MCU_SW_CON_3 (SPM_BASE + 0x460)
#define SPM_DRAM_MCU_SW_CON_4 (SPM_BASE + 0x464)
#define SPM_DRAM_MCU_STA_0 (SPM_BASE + 0x468)
#define SPM_DRAM_MCU_STA_1 (SPM_BASE + 0x46C)
#define SPM_DRAM_MCU_STA_2 (SPM_BASE + 0x470)
#define SPM_DRAM_MCU_SW_SEL_0 (SPM_BASE + 0x474)
#define RELAY_DVFS_LEVEL (SPM_BASE + 0x478)
#define DRAMC_DPY_CLK_SW_CON_0 (SPM_BASE + 0x480)
#define DRAMC_DPY_CLK_SW_CON_1 (SPM_BASE + 0x484)
#define DRAMC_DPY_CLK_SW_CON_2 (SPM_BASE + 0x488)
#define DRAMC_DPY_CLK_SW_CON_3 (SPM_BASE + 0x48C)
#define DRAMC_DPY_CLK_SW_SEL_0 (SPM_BASE + 0x490)
#define DRAMC_DPY_CLK_SW_SEL_1 (SPM_BASE + 0x494)
#define DRAMC_DPY_CLK_SW_SEL_2 (SPM_BASE + 0x498)
#define DRAMC_DPY_CLK_SW_SEL_3 (SPM_BASE + 0x49C)
#define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x4A0)
#define SPM_DVFS_LEVEL (SPM_BASE + 0x4A4)
#define SPM_CIRQ_CON (SPM_BASE + 0x4A8)
#define SPM_DVFS_MISC (SPM_BASE + 0x4AC)
#define SPM_VS1_VS2_RC_CON (SPM_BASE + 0x4B0)
#define RG_MODULE_SW_CG_0_MASK_REQ_0 (SPM_BASE + 0x4B4)
#define RG_MODULE_SW_CG_0_MASK_REQ_1 (SPM_BASE + 0x4B8)
#define RG_MODULE_SW_CG_0_MASK_REQ_2 (SPM_BASE + 0x4BC)
#define RG_MODULE_SW_CG_1_MASK_REQ_0 (SPM_BASE + 0x4C0)
#define RG_MODULE_SW_CG_1_MASK_REQ_1 (SPM_BASE + 0x4C4)
#define RG_MODULE_SW_CG_1_MASK_REQ_2 (SPM_BASE + 0x4C8)
#define RG_MODULE_SW_CG_2_MASK_REQ_0 (SPM_BASE + 0x4CC)
#define RG_MODULE_SW_CG_2_MASK_REQ_1 (SPM_BASE + 0x4D0)
#define RG_MODULE_SW_CG_2_MASK_REQ_2 (SPM_BASE + 0x4D4)
#define RG_MODULE_SW_CG_3_MASK_REQ_0 (SPM_BASE + 0x4D8)
#define RG_MODULE_SW_CG_3_MASK_REQ_1 (SPM_BASE + 0x4DC)
#define RG_MODULE_SW_CG_3_MASK_REQ_2 (SPM_BASE + 0x4E0)
#define PWR_STATUS_MASK_REQ_0 (SPM_BASE + 0x4E4)
#define PWR_STATUS_MASK_REQ_1 (SPM_BASE + 0x4E8)
#define PWR_STATUS_MASK_REQ_2 (SPM_BASE + 0x4EC)
#define SPM_CG_CHECK_CON (SPM_BASE + 0x4F0)
#define SPM_SRC_RDY_STA (SPM_BASE + 0x4F4)
#define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x4F8)
#define SPM_FORCE_DVFS (SPM_BASE + 0x4FC)
#define SRCLKEN_RC_CFG (SPM_BASE + 0x500)
#define RC_CENTRAL_CFG1 (SPM_BASE + 0x504)
#define RC_CENTRAL_CFG2 (SPM_BASE + 0x508)
#define RC_CMD_ARB_CFG (SPM_BASE + 0x50C)
#define RC_PMIC_RCEN_ADDR (SPM_BASE + 0x510)
#define RC_PMIC_RCEN_SET_CLR_ADDR (SPM_BASE + 0x514)
#define RC_DCXO_FPM_CFG (SPM_BASE + 0x518)
#define RC_CENTRAL_CFG3 (SPM_BASE + 0x51C)
#define RC_M00_SRCLKEN_CFG (SPM_BASE + 0x520)
#define RC_M01_SRCLKEN_CFG (SPM_BASE + 0x524)
#define RC_M02_SRCLKEN_CFG (SPM_BASE + 0x528)
#define RC_M03_SRCLKEN_CFG (SPM_BASE + 0x52C)
#define RC_M04_SRCLKEN_CFG (SPM_BASE + 0x530)
#define RC_M05_SRCLKEN_CFG (SPM_BASE + 0x534)
#define RC_M06_SRCLKEN_CFG (SPM_BASE + 0x538)
#define RC_M07_SRCLKEN_CFG (SPM_BASE + 0x53C)
#define RC_M08_SRCLKEN_CFG (SPM_BASE + 0x540)
#define RC_M09_SRCLKEN_CFG (SPM_BASE + 0x544)
#define RC_M10_SRCLKEN_CFG (SPM_BASE + 0x548)
#define RC_M11_SRCLKEN_CFG (SPM_BASE + 0x54C)
#define RC_M12_SRCLKEN_CFG (SPM_BASE + 0x550)
#define RC_SRCLKEN_SW_CON_CFG (SPM_BASE + 0x554)
#define RC_CENTRAL_CFG4 (SPM_BASE + 0x558)
#define RC_PROTOCOL_CHK_CFG (SPM_BASE + 0x560)
#define RC_DEBUG_CFG (SPM_BASE + 0x564)
#define RC_MISC_0 (SPM_BASE + 0x5B4)
#define RC_SPM_CTRL (SPM_BASE + 0x5B8)
#define SUBSYS_INTF_CFG (SPM_BASE + 0x5BC)
#define PCM_WDT_LATCH_25 (SPM_BASE + 0x5C0)
#define PCM_WDT_LATCH_26 (SPM_BASE + 0x5C4)
#define PCM_WDT_LATCH_27 (SPM_BASE + 0x5C8)
#define PCM_WDT_LATCH_28 (SPM_BASE + 0x5CC)
#define PCM_WDT_LATCH_29 (SPM_BASE + 0x5D0)
#define PCM_WDT_LATCH_30 (SPM_BASE + 0x5D4)
#define PCM_WDT_LATCH_31 (SPM_BASE + 0x5D8)
#define PCM_WDT_LATCH_32 (SPM_BASE + 0x5DC)
#define PCM_WDT_LATCH_33 (SPM_BASE + 0x5E0)
#define PCM_WDT_LATCH_34 (SPM_BASE + 0x5E4)
#define PCM_WDT_LATCH_35 (SPM_BASE + 0x5EC)
#define PCM_WDT_LATCH_36 (SPM_BASE + 0x5F0)
#define PCM_WDT_LATCH_37 (SPM_BASE + 0x5F4)
#define PCM_WDT_LATCH_38 (SPM_BASE + 0x5F8)
#define PCM_WDT_LATCH_39 (SPM_BASE + 0x5FC)
#define SPM_SW_FLAG_0 (SPM_BASE + 0x600)
#define SPM_SW_DEBUG_0 (SPM_BASE + 0x604)
#define SPM_SW_FLAG_1 (SPM_BASE + 0x608)
#define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C)
#define SPM_SW_RSV_0 (SPM_BASE + 0x610)
#define SPM_SW_RSV_1 (SPM_BASE + 0x614)
#define SPM_SW_RSV_2 (SPM_BASE + 0x618)
#define SPM_SW_RSV_3 (SPM_BASE + 0x61C)
#define SPM_SW_RSV_4 (SPM_BASE + 0x620)
#define SPM_SW_RSV_5 (SPM_BASE + 0x624)
#define SPM_SW_RSV_6 (SPM_BASE + 0x628)
#define SPM_SW_RSV_7 (SPM_BASE + 0x62C)
#define SPM_SW_RSV_8 (SPM_BASE + 0x630)
#define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634)
#define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638)
#define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C)
#define SPM_BK_PCM_TIMER (SPM_BASE + 0x640)
#define SPM_RSV_CON_0 (SPM_BASE + 0x650)
#define SPM_RSV_CON_1 (SPM_BASE + 0x654)
#define SPM_RSV_STA_0 (SPM_BASE + 0x658)
#define SPM_RSV_STA_1 (SPM_BASE + 0x65C)
#define SPM_SPARE_CON (SPM_BASE + 0x660)
#define SPM_SPARE_CON_SET (SPM_BASE + 0x664)
#define SPM_SPARE_CON_CLR (SPM_BASE + 0x668)
#define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C)
#define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670)
#define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674)
#define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678)
#define SCP_VCORE_LEVEL (SPM_BASE + 0x67C)
#define SC_MM_CK_SEL_CON (SPM_BASE + 0x680)
#define SPARE_ACK_MASK (SPM_BASE + 0x684)
#define SPM_CROSS_WAKE_M04_REQ (SPM_BASE + 0x688)
#define SPM_DV_CON_0 (SPM_BASE + 0x68C)
#define SPM_DV_CON_1 (SPM_BASE + 0x690)
#define SPM_DV_STA (SPM_BASE + 0x694)
#define CONN_XOWCN_DEBUG_EN (SPM_BASE + 0x698)
#define SPM_SEMA_M0 (SPM_BASE + 0x69C)
#define SPM_SEMA_M1 (SPM_BASE + 0x6A0)
#define SPM_SEMA_M2 (SPM_BASE + 0x6A4)
#define SPM_SEMA_M3 (SPM_BASE + 0x6A8)
#define SPM_SEMA_M4 (SPM_BASE + 0x6AC)
#define SPM_SEMA_M5 (SPM_BASE + 0x6B0)
#define SPM_SEMA_M6 (SPM_BASE + 0x6B4)
#define SPM_SEMA_M7 (SPM_BASE + 0x6B8)
#define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC)
#define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0)
#define SPM_ADSP_IRQ (SPM_BASE + 0x6C4)
#define SPM_MD32_IRQ (SPM_BASE + 0x6C8)
#define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC)
#define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0)
#define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4)
#define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8)
#define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC)
#define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0)
#define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4)
#define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8)
#define UFS_PSRI_SW (SPM_BASE + 0x6EC)
#define UFS_PSRI_SW_SET (SPM_BASE + 0x6F0)
#define UFS_PSRI_SW_CLR (SPM_BASE + 0x6F4)
#define SPM_AP_SEMA (SPM_BASE + 0x6F8)
#define SPM_SPM_SEMA (SPM_BASE + 0x6FC)
#define SPM_DVFS_CON (SPM_BASE + 0x700)
#define SPM_DVFS_CON_STA (SPM_BASE + 0x704)
#define SPM_PMIC_SPMI_CON (SPM_BASE + 0x708)
#define SPM_DVFS_CMD0 (SPM_BASE + 0x710)
#define SPM_DVFS_CMD1 (SPM_BASE + 0x714)
#define SPM_DVFS_CMD2 (SPM_BASE + 0x718)
#define SPM_DVFS_CMD3 (SPM_BASE + 0x71C)
#define SPM_DVFS_CMD4 (SPM_BASE + 0x720)
#define SPM_DVFS_CMD5 (SPM_BASE + 0x724)
#define SPM_DVFS_CMD6 (SPM_BASE + 0x728)
#define SPM_DVFS_CMD7 (SPM_BASE + 0x72C)
#define SPM_DVFS_CMD8 (SPM_BASE + 0x730)
#define SPM_DVFS_CMD9 (SPM_BASE + 0x734)
#define SPM_DVFS_CMD10 (SPM_BASE + 0x738)
#define SPM_DVFS_CMD11 (SPM_BASE + 0x73C)
#define SPM_DVFS_CMD12 (SPM_BASE + 0x740)
#define SPM_DVFS_CMD13 (SPM_BASE + 0x744)
#define SPM_DVFS_CMD14 (SPM_BASE + 0x748)
#define SPM_DVFS_CMD15 (SPM_BASE + 0x74C)
#define SPM_DVFS_CMD16 (SPM_BASE + 0x750)
#define SPM_DVFS_CMD17 (SPM_BASE + 0x754)
#define SPM_DVFS_CMD18 (SPM_BASE + 0x758)
#define SPM_DVFS_CMD19 (SPM_BASE + 0x75C)
#define SPM_DVFS_CMD20 (SPM_BASE + 0x760)
#define SPM_DVFS_CMD21 (SPM_BASE + 0x764)
#define SPM_DVFS_CMD22 (SPM_BASE + 0x768)
#define SPM_DVFS_CMD23 (SPM_BASE + 0x76C)
#define SYS_TIMER_VALUE_L (SPM_BASE + 0x770)
#define SYS_TIMER_VALUE_H (SPM_BASE + 0x774)
#define SYS_TIMER_START_L (SPM_BASE + 0x778)
#define SYS_TIMER_START_H (SPM_BASE + 0x77C)
#define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x780)
#define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x784)
#define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x788)
#define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x78C)
#define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x790)
#define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x794)
#define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x798)
#define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x79C)
#define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x7A0)
#define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x7A4)
#define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x7A8)
#define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x7AC)
#define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x7B0)
#define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x7B4)
#define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x7B8)
#define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x7BC)
#define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x7C0)
#define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x7C4)
#define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x7C8)
#define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x7CC)
#define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x7D0)
#define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x7D4)
#define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x7D8)
#define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x7DC)
#define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x7E0)
#define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x7E4)
#define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x7E8)
#define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x7EC)
#define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x7F0)
#define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x7F4)
#define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x7F8)
#define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x7FC)
#define PCM_WDT_LATCH_0 (SPM_BASE + 0x800)
#define PCM_WDT_LATCH_1 (SPM_BASE + 0x804)
#define PCM_WDT_LATCH_2 (SPM_BASE + 0x808)
#define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C)
#define PCM_WDT_LATCH_4 (SPM_BASE + 0x810)
#define PCM_WDT_LATCH_5 (SPM_BASE + 0x814)
#define PCM_WDT_LATCH_6 (SPM_BASE + 0x818)
#define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C)
#define PCM_WDT_LATCH_8 (SPM_BASE + 0x820)
#define PCM_WDT_LATCH_9 (SPM_BASE + 0x824)
#define PCM_WDT_LATCH_10 (SPM_BASE + 0x828)
#define PCM_WDT_LATCH_11 (SPM_BASE + 0x82C)
#define PCM_WDT_LATCH_12 (SPM_BASE + 0x830)
#define PCM_WDT_LATCH_13 (SPM_BASE + 0x834)
#define PCM_WDT_LATCH_14 (SPM_BASE + 0x838)
#define PCM_WDT_LATCH_15 (SPM_BASE + 0x83C)
#define PCM_WDT_LATCH_16 (SPM_BASE + 0x840)
#define PCM_WDT_LATCH_17 (SPM_BASE + 0x844)
#define PCM_WDT_LATCH_18 (SPM_BASE + 0x848)
#define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x84C)
#define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x850)
#define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x854)
#define PCM_WDT_LATCH_CONN_0 (SPM_BASE + 0x870)
#define PCM_WDT_LATCH_CONN_1 (SPM_BASE + 0x874)
#define PCM_WDT_LATCH_CONN_2 (SPM_BASE + 0x878)
#define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x8A0)
#define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x8A4)
#define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x8A8)
#define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x8AC)
#define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x8B0)
#define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x8B4)
#define DRAMC_GATING_ERR_LATCH_CH0_6 (SPM_BASE + 0x8B8)
#define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4)
#define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x900)
#define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x904)
#define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x908)
#define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x90C)
#define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x910)
#define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x914)
#define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x920)
#define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x924)
#define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x928)
#define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x92C)
#define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x930)
#define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x934)
#define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x940)
#define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x944)
#define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x948)
#define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x94C)
#define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x950)
#define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x954)
#define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960)
#define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x964)
#define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x968)
#define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x96C)
#define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x970)
#define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x974)
#define SPM_COUNTER_0 (SPM_BASE + 0x978)
#define SPM_COUNTER_1 (SPM_BASE + 0x97C)
#define SPM_COUNTER_2 (SPM_BASE + 0x980)
#define SYS_TIMER_CON (SPM_BASE + 0x98C)
#define RC_FSM_STA_0 (SPM_BASE + 0xE00)
#define RC_CMD_STA_0 (SPM_BASE + 0xE04)
#define RC_CMD_STA_1 (SPM_BASE + 0xE08)
#define RC_SPI_STA_0 (SPM_BASE + 0xE0C)
#define RC_PI_PO_STA_0 (SPM_BASE + 0xE10)
#define RC_M00_REQ_STA_0 (SPM_BASE + 0xE14)
#define RC_M01_REQ_STA_0 (SPM_BASE + 0xE1C)
#define RC_M02_REQ_STA_0 (SPM_BASE + 0xE20)
#define RC_M03_REQ_STA_0 (SPM_BASE + 0xE24)
#define RC_M04_REQ_STA_0 (SPM_BASE + 0xE28)
#define RC_M05_REQ_STA_0 (SPM_BASE + 0xE2C)
#define RC_M06_REQ_STA_0 (SPM_BASE + 0xE30)
#define RC_M07_REQ_STA_0 (SPM_BASE + 0xE34)
#define RC_M08_REQ_STA_0 (SPM_BASE + 0xE38)
#define RC_M09_REQ_STA_0 (SPM_BASE + 0xE3C)
#define RC_M10_REQ_STA_0 (SPM_BASE + 0xE40)
#define RC_M11_REQ_STA_0 (SPM_BASE + 0xE44)
#define RC_M12_REQ_STA_0 (SPM_BASE + 0xE48)
#define RC_DEBUG_STA_0 (SPM_BASE + 0xE4C)
#define RC_DEBUG_TRACE_0_LSB (SPM_BASE + 0xE50)
#define RC_DEBUG_TRACE_0_MSB (SPM_BASE + 0xE54)
#define RC_DEBUG_TRACE_1_LSB (SPM_BASE + 0xE5C)
#define RC_DEBUG_TRACE_1_MSB (SPM_BASE + 0xE60)
#define RC_DEBUG_TRACE_2_LSB (SPM_BASE + 0xE64)
#define RC_DEBUG_TRACE_2_MSB (SPM_BASE + 0xE6C)
#define RC_DEBUG_TRACE_3_LSB (SPM_BASE + 0xE70)
#define RC_DEBUG_TRACE_3_MSB (SPM_BASE + 0xE74)
#define RC_DEBUG_TRACE_4_LSB (SPM_BASE + 0xE78)
#define RC_DEBUG_TRACE_4_MSB (SPM_BASE + 0xE7C)
#define RC_DEBUG_TRACE_5_LSB (SPM_BASE + 0xE80)
#define RC_DEBUG_TRACE_5_MSB (SPM_BASE + 0xE84)
#define RC_DEBUG_TRACE_6_LSB (SPM_BASE + 0xE88)
#define RC_DEBUG_TRACE_6_MSB (SPM_BASE + 0xE8C)
#define RC_DEBUG_TRACE_7_LSB (SPM_BASE + 0xE90)
#define RC_DEBUG_TRACE_7_MSB (SPM_BASE + 0xE94)
#define RC_SYS_TIMER_LATCH_0_LSB (SPM_BASE + 0xE98)
#define RC_SYS_TIMER_LATCH_0_MSB (SPM_BASE + 0xE9C)
#define RC_SYS_TIMER_LATCH_1_LSB (SPM_BASE + 0xEA0)
#define RC_SYS_TIMER_LATCH_1_MSB (SPM_BASE + 0xEA4)
#define RC_SYS_TIMER_LATCH_2_LSB (SPM_BASE + 0xEA8)
#define RC_SYS_TIMER_LATCH_2_MSB (SPM_BASE + 0xEAC)
#define RC_SYS_TIMER_LATCH_3_LSB (SPM_BASE + 0xEB0)
#define RC_SYS_TIMER_LATCH_3_MSB (SPM_BASE + 0xEB4)
#define RC_SYS_TIMER_LATCH_4_LSB (SPM_BASE + 0xEB8)
#define RC_SYS_TIMER_LATCH_4_MSB (SPM_BASE + 0xEBC)
#define RC_SYS_TIMER_LATCH_5_LSB (SPM_BASE + 0xEC0)
#define RC_SYS_TIMER_LATCH_5_MSB (SPM_BASE + 0xEC4)
#define RC_SYS_TIMER_LATCH_6_LSB (SPM_BASE + 0xEC8)
#define RC_SYS_TIMER_LATCH_6_MSB (SPM_BASE + 0xECC)
#define RC_SYS_TIMER_LATCH_7_LSB (SPM_BASE + 0xED0)
#define RC_SYS_TIMER_LATCH_7_MSB (SPM_BASE + 0xED4)
#define PCM_WDT_LATCH_19 (SPM_BASE + 0xED8)
#define PCM_WDT_LATCH_20 (SPM_BASE + 0xEDC)
#define PCM_WDT_LATCH_21 (SPM_BASE + 0xEE0)
#define PCM_WDT_LATCH_22 (SPM_BASE + 0xEE4)
#define PCM_WDT_LATCH_23 (SPM_BASE + 0xEE8)
#define PCM_WDT_LATCH_24 (SPM_BASE + 0xEEC)
#define PMSR_LAST_DAT (SPM_BASE + 0xF00)
#define PMSR_LAST_CNT (SPM_BASE + 0xF04)
#define PMSR_LAST_ACK (SPM_BASE + 0xF08)
#define SPM_PMSR_SEL_CON0 (SPM_BASE + 0xF10)
#define SPM_PMSR_SEL_CON1 (SPM_BASE + 0xF14)
#define SPM_PMSR_SEL_CON2 (SPM_BASE + 0xF18)
#define SPM_PMSR_SEL_CON3 (SPM_BASE + 0xF1C)
#define SPM_PMSR_SEL_CON4 (SPM_BASE + 0xF20)
#define SPM_PMSR_SEL_CON5 (SPM_BASE + 0xF24)
#define SPM_PMSR_SEL_CON6 (SPM_BASE + 0xF28)
#define SPM_PMSR_SEL_CON7 (SPM_BASE + 0xF2C)
#define SPM_PMSR_SEL_CON8 (SPM_BASE + 0xF30)
#define SPM_PMSR_SEL_CON9 (SPM_BASE + 0xF34)
#define SPM_PMSR_SEL_CON10 (SPM_BASE + 0xF3C)
#define SPM_PMSR_SEL_CON11 (SPM_BASE + 0xF40)
#define SPM_PMSR_TIEMR_STA0 (SPM_BASE + 0xFB8)
#define SPM_PMSR_TIEMR_STA1 (SPM_BASE + 0xFBC)
#define SPM_PMSR_TIEMR_STA2 (SPM_BASE + 0xFC0)
#define SPM_PMSR_GENERAL_CON0 (SPM_BASE + 0xFC4)
#define SPM_PMSR_GENERAL_CON1 (SPM_BASE + 0xFC8)
#define SPM_PMSR_GENERAL_CON2 (SPM_BASE + 0xFCC)
#define SPM_PMSR_GENERAL_CON3 (SPM_BASE + 0xFD0)
#define SPM_PMSR_GENERAL_CON4 (SPM_BASE + 0xFD4)
#define SPM_PMSR_GENERAL_CON5 (SPM_BASE + 0xFD8)
#define SPM_PMSR_SW_RESET (SPM_BASE + 0xFDC)
#define SPM_PMSR_MON_CON0 (SPM_BASE + 0xFE0)
#define SPM_PMSR_MON_CON1 (SPM_BASE + 0xFE4)
#define SPM_PMSR_MON_CON2 (SPM_BASE + 0xFE8)
#define SPM_PMSR_LEN_CON0 (SPM_BASE + 0xFEC)
#define SPM_PMSR_LEN_CON1 (SPM_BASE + 0xFF0)
#define SPM_PMSR_LEN_CON2 (SPM_BASE + 0xFF4)
/* POWERON_CONFIG_EN (0x10006000+0x000) */
#define BCLK_CG_EN_LSB (1U << 0) /* 1b */
#define PROJECT_CODE_LSB (1U << 16) /* 16b */
/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */
#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */
/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */
#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */
/* SPM_CLK_CON (0x10006000+0x00C) */
#define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */
#define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */
#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */
#define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */
#define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */
#define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */
#define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */
#define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */
#define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */
#define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */
#define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */
#define SCP_DCM_EN_LSB (1U << 15) /* 1b */
#define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */
#define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */
/* SPM_CLK_SETTLE (0x10006000+0x010) */
#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */
/* SPM_AP_STANDBY_CON (0x10006000+0x014) */
#define REG_WFI_OP_LSB (1U << 0) /* 1b */
#define REG_WFI_TYPE_LSB (1U << 1) /* 1b */
#define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */
#define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */
#define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */
#define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */
#define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */
#define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */
/* PCM_CON0 (0x10006000+0x018) */
#define PCM_CK_EN_LSB (1U << 2) /* 1b */
#define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */
#define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */
#define PCM_SW_RESET_LSB (1U << 15) /* 1b */
#define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */
/* PCM_CON1 (0x10006000+0x01C) */
#define RG_IM_SLAVE_LSB (1U << 0) /* 1b */
#define RG_IM_SLEEP_LSB (1U << 1) /* 1b */
#define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */
#define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */
#define RG_IM_PDN_LSB (1U << 4) /* 1b */
#define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */
#define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */
#define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */
#define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */
#define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */
#define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */
#define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */
#define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */
#define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */
#define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */
#define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */
#define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */
/* SPM_POWER_ON_VAL2 (0x10006000+0x020) */
#define POWER_ON_VAL2_LSB (1U << 0) /* 32b */
/* SPM_POWER_ON_VAL3 (0x10006000+0x024) */
#define POWER_ON_VAL3_LSB (1U << 0) /* 32b */
/* PCM_REG_DATA_INI (0x10006000+0x028) */
#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */
/* PCM_PWR_IO_EN (0x10006000+0x02C) */
#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */
#define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */
/* PCM_TIMER_VAL (0x10006000+0x030) */
#define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */
/* PCM_WDT_VAL (0x10006000+0x034) */
#define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */
/* SPM_SRC6_MASK (0x10006000+0x038) */
#define REG_DPMAIF_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */
#define REG_DPMAIF_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */
#define REG_DPMAIF_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */
#define REG_DPMAIF_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */
#define REG_DPMAIF_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */
/* SPM_SW_RST_CON (0x10006000+0x040) */
#define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */
#define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */
/* SPM_SW_RST_CON_SET (0x10006000+0x044) */
#define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */
#define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */
/* SPM_SW_RST_CON_CLR (0x10006000+0x048) */
#define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */
#define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */
/* VS1_PSR_MASK_B (0x10006000+0x04C) */
#define VS1_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */
#define VS1_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */
/* VS2_PSR_MASK_B (0x10006000+0x050) */
#define VS2_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */
#define VS2_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */
#define VS2_OPP2_PSR_MASK_B_LSB (1U << 16) /* 8b */
/* MD32_CLK_CON (0x10006000+0x084) */
#define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */
#define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */
/* SPM_SRAM_RSV_CON (0x10006000+0x088) */
#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */
/* SPM_SWINT (0x10006000+0x08C) */
#define SPM_SWINT_LSB (1U << 0) /* 32b */
/* SPM_SWINT_SET (0x10006000+0x090) */
#define SPM_SWINT_SET_LSB (1U << 0) /* 32b */
/* SPM_SWINT_CLR (0x10006000+0x094) */
#define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */
/* SPM_SCP_MAILBOX (0x10006000+0x098) */
#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */
/* SCP_SPM_MAILBOX (0x10006000+0x09C) */
#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */
/* SPM_TWAM_CON (0x10006000+0x0A0) */
#define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */
#define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */
#define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */
#define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */
#define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */
#define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */
#define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */
#define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */
/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */
#define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */
/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */
#define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */
#define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */
#define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */
#define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */
/* SPM_SCP_IRQ (0x10006000+0x0AC) */
#define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */
#define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */
#define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */
/* SPM_IRQ_MASK (0x10006000+0x0B4) */
#define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */
/* SPM_SRC_REQ (0x10006000+0x0B8) */
#define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */
#define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */
#define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */
#define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */
#define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */
#define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */
#define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */
#define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */
#define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */
#define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */
/* SPM_SRC_MASK (0x10006000+0x0BC) */
#define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */
#define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */
#define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */
#define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */
#define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */
#define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */
#define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 6) /* 1b */
#define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7) /* 1b */
#define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */
#define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 9) /* 1b */
#define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 10) /* 1b */
#define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 11) /* 1b */
#define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */
#define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 13) /* 1b */
#define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 14) /* 1b */
#define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */
#define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 16) /* 1b */
#define REG_CONN_DDR_EN_MASK_B_LSB (1U << 17) /* 1b */
#define REG_CONN_VFE28_MASK_B_LSB (1U << 18) /* 1b */
#define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19) /* 1b */
#define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20) /* 1b */
#define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */
#define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */
#define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
#define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
#define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
#define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */
#define REG_MD32_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */
#define REG_MD32_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */
#define REG_MD32_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
#define REG_MD32_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
#define REG_MD32_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
/* SPM_SRC2_MASK (0x10006000+0x0C0) */
#define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */
#define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */
#define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */
#define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */
#define REG_SCP_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */
#define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */
#define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */
#define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */
#define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */
#define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */
#define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */
#define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */
#define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */
#define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */
#define REG_UFS_DDR_EN_MASK_B_LSB (1U << 14) /* 1b */
#define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */
#define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */
#define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */
#define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */
#define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */
#define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */
#define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */
#define REG_GCE_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */
#define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
#define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
#define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
#define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */
#define REG_APU_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */
#define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */
#define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
#define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
#define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
/* SPM_SRC3_MASK (0x10006000+0x0C4) */
#define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */
#define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */
#define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */
#define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */
#define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */
#define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */
#define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */
#define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */
#define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */
#define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */
#define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */
#define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */
#define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */
#define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */
#define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */
#define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */
#define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */
#define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */
#define REG_MCUPM_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */
#define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */
#define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */
#define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */
#define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */
#define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */
#define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */
#define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */
#define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
#define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
#define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
/* SPM_SRC4_MASK (0x10006000+0x0C8) */
#define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */
#define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */
#define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */
#define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */
#define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */
#define REG_BAK_PSRI_DDR_EN_MASK_B_LSB (1U << 20) /* 1b */
#define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 1b */
#define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22) /* 1b */
#define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */
#define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24) /* 1b */
#define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */
#define REG_DRAMC0_MD32_WAKEUP_MASK_LSB (1U << 26) /* 1b */
#define REG_DRAMC1_MD32_WAKEUP_MASK_LSB (1U << 27) /* 1b */
/* SPM_SRC5_MASK (0x10006000+0x0CC) */
#define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */
#define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */
#define REG_MSDC2_SRCCLKENA_MASK_B_LSB (1U << 18) /* 1b */
#define REG_MSDC2_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */
#define REG_MSDC2_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */
#define REG_MSDC2_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */
#define REG_MSDC2_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */
#define REG_PCIE_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
#define REG_PCIE_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
#define REG_PCIE_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
#define REG_PCIE_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */
#define REG_PCIE_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */
/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */
#define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */
#define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */
#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */
/* SCP_CLK_CON (0x10006000+0x0DC) */
#define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */
#define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */
#define SCP_SECURE_V_REQ_MASK_LSB (1U << 2) /* 1b */
#define SCP_SLP_REQ_LSB (1U << 3) /* 1b */
#define SCP_SLP_ACK_LSB (1U << 4) /* 1b */
/* PCM_DEBUG_CON (0x10006000+0x0E0) */
#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */
/* AHB_BUS_CON (0x10006000+0x0E4) */
#define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */
#define REG_AHB_LOCK_LSB (1U << 8) /* 1b */
/* DDR_EN_DBC_CON0 (0x10006000+0x0E8) */
#define REG_ALL_DDR_EN_DBC_LEN_LSB (1U << 0) /* 10b */
#define REG_MD_DDR_EN_0_DBC_LEN_LSB (1U << 10) /* 10b */
#define REG_HW_S1_DBC_LEN_LSB (1U << 20) /* 10b */
/* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */
#define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 0) /* 1b */
#define REG_MD_DDR_EN_0_DBC_EN_LSB (1U << 1) /* 1b */
#define REG_HW_S1_DBC_EN_LSB (1U << 2) /* 1b */
/* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */
#define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */
#define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */
#define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */
#define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */
#define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */
#define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 5) /* 1b */
#define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 6) /* 1b */
#define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 7) /* 1b */
#define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 8) /* 1b */
#define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 9) /* 1b */
#define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */
#define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */
#define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */
#define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */
#define REG_CONN_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */
#define REG_MD32_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */
#define REG_MD32_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */
#define REG_MD32_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */
#define REG_MD32_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */
#define REG_MD32_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */
#define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */
#define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */
#define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */
#define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */
#define REG_SCP_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */
#define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */
#define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */
#define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */
#define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */
#define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB (1U << 29) /* 1b */
#define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */
#define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */
/* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */
#define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */
#define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */
#define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */
#define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */
#define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */
#define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */
#define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */
#define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */
#define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */
#define REG_APU_DDR_EN_ACK_MASK_LSB (1U << 9) /* 1b */
#define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */
#define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */
#define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */
#define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */
#define REG_MCUPM_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */
#define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */
#define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */
#define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */
#define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */
#define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */
#define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */
#define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */
#define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */
#define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */
#define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */
#define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */
#define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */
#define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */
#define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */
#define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */
#define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */
/* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */
#define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */
#define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */
#define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */
#define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */
/* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */
#define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */
#define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */
#define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */
#define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */
#define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */
#define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB (1U << 12) /* 1b */
#define REG_MSDC2_SRCCLKENA_ACK_MASK_LSB (1U << 13) /* 1b */
#define REG_MSDC2_INFRA_ACK_MASK_LSB (1U << 14) /* 1b */
#define REG_MSDC2_APSRC_ACK_MASK_LSB (1U << 15) /* 1b */
#define REG_MSDC2_VRF18_ACK_MASK_LSB (1U << 16) /* 1b */
#define REG_MSDC2_DDR_EN_ACK_MASK_LSB (1U << 17) /* 1b */
#define REG_PCIE_SRCCLKENA_ACK_MASK_LSB (1U << 18) /* 1b */
#define REG_PCIE_INFRA_ACK_MASK_LSB (1U << 19) /* 1b */
#define REG_PCIE_APSRC_ACK_MASK_LSB (1U << 20) /* 1b */
#define REG_PCIE_VRF18_ACK_MASK_LSB (1U << 21) /* 1b */
#define REG_PCIE_DDR_EN_ACK_MASK_LSB (1U << 22) /* 1b */
#define REG_DPMAIF_SRCCLKENA_ACK_MASK_LSB (1U << 23) /* 1b */
#define REG_DPMAIF_INFRA_ACK_MASK_LSB (1U << 24) /* 1b */
#define REG_DPMAIF_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */
#define REG_DPMAIF_VRF18_ACK_MASK_LSB (1U << 26) /* 1b */
#define REG_DPMAIF_DDR_EN_ACK_MASK_LSB (1U << 27) /* 1b */
/* PCM_REG0_DATA (0x10006000+0x100) */
#define PCM_REG0_RF_LSB (1U << 0) /* 32b */
/* PCM_REG2_DATA (0x10006000+0x104) */
#define PCM_REG2_RF_LSB (1U << 0) /* 32b */
/* PCM_REG6_DATA (0x10006000+0x108) */
#define PCM_REG6_RF_LSB (1U << 0) /* 32b */
/* PCM_REG7_DATA (0x10006000+0x10C) */
#define PCM_REG7_RF_LSB (1U << 0) /* 32b */
/* PCM_REG13_DATA (0x10006000+0x110) */
#define PCM_REG13_RF_LSB (1U << 0) /* 32b */
/* SRC_REQ_STA_0 (0x10006000+0x114) */
#define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */
#define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */
#define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */
#define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */
#define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */
#define MD_DDR_EN_0_LSB (1U << 5) /* 1b */
#define MD_SRCCLKENA_1_LSB (1U << 6) /* 1b */
#define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 7) /* 1b */
#define MD_APSRC2INFRA_REQ_1_LSB (1U << 8) /* 1b */
#define MD_APSRC_REQ_1_LSB (1U << 9) /* 1b */
#define MD_VRF18_REQ_1_LSB (1U << 10) /* 1b */
#define MD_DDR_EN_1_LSB (1U << 11) /* 1b */
#define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */
#define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */
#define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */
#define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */
#define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */
#define CONN_DDR_EN_LSB (1U << 17) /* 1b */
#define SRCCLKENI_LSB (1U << 18) /* 3b */
#define MD32_SRCCLKENA_LSB (1U << 21) /* 1b */
#define MD32_INFRA_REQ_LSB (1U << 22) /* 1b */
#define MD32_APSRC_REQ_LSB (1U << 23) /* 1b */
#define MD32_VRF18_REQ_LSB (1U << 24) /* 1b */
#define MD32_DDR_EN_LSB (1U << 25) /* 1b */
#define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */
#define DISP0_DDR_EN_LSB (1U << 27) /* 1b */
#define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */
#define DISP1_DDR_EN_LSB (1U << 29) /* 1b */
#define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */
/* SRC_REQ_STA_1 (0x10006000+0x118) */
#define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */
#define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */
#define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */
#define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */
#define SCP_DDR_EN_LSB (1U << 4) /* 1b */
#define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */
#define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */
#define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */
#define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */
#define AUDIO_DSP_DDR_EN_LSB (1U << 9) /* 1b */
#define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */
#define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */
#define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */
#define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */
#define UFS_DDR_EN_LSB (1U << 14) /* 1b */
#define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */
#define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */
#define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */
#define GCE_DDR_EN_LSB (1U << 18) /* 1b */
#define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */
#define INFRASYS_DDR_EN_LSB (1U << 20) /* 1b */
#define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */
#define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */
#define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */
#define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */
#define MSDC0_DDR_EN_LSB (1U << 25) /* 1b */
#define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */
#define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */
#define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */
#define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */
#define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */
/* SRC_REQ_STA_2 (0x10006000+0x11C) */
#define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */
#define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */
#define SW2SPM_INT_LSB (1U << 11) /* 4b */
#define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */
#define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */
#define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */
#define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */
#define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */
#define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */
#define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */
#define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */
#define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */
#define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */
#define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */
#define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */
#define MCUPM_DDR_EN_LSB (1U << 30) /* 1b */
/* PCM_TIMER_OUT (0x10006000+0x120) */
#define PCM_TIMER_LSB (1U << 0) /* 32b */
/* PCM_WDT_OUT (0x10006000+0x124) */
#define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */
/* SPM_IRQ_STA (0x10006000+0x128) */
#define TWAM_IRQ_LSB (1U << 2) /* 1b */
#define PCM_IRQ_LSB (1U << 3) /* 1b */
/* SRC_REQ_STA_4 (0x10006000+0x12C) */
#define APU_SRCCLKENA_LSB (1U << 0) /* 1b */
#define APU_INFRA_REQ_LSB (1U << 1) /* 1b */
#define APU_APSRC_REQ_LSB (1U << 2) /* 1b */
#define APU_VRF18_REQ_LSB (1U << 3) /* 1b */
#define APU_DDR_EN_LSB (1U << 4) /* 1b */
#define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */
#define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */
#define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */
#define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */
#define BAK_PSRI_DDR_EN_LSB (1U << 9) /* 1b */
#define MSDC2_SRCCLKENA_LSB (1U << 10) /* 1b */
#define MSDC2_INFRA_REQ_LSB (1U << 11) /* 1b */
#define MSDC2_APSRC_REQ_LSB (1U << 12) /* 1b */
#define MSDC2_VRF18_REQ_LSB (1U << 13) /* 1b */
#define MSDC2_DDR_EN_LSB (1U << 14) /* 1b */
#define PCIE_SRCCLKENA_LSB (1U << 15) /* 1b */
#define PCIE_INFRA_REQ_LSB (1U << 16) /* 1b */
#define PCIE_APSRC_REQ_LSB (1U << 17) /* 1b */
#define PCIE_VRF18_REQ_LSB (1U << 18) /* 1b */
#define PCIE_DDR_EN_LSB (1U << 19) /* 1b */
#define DPMAIF_SRCCLKENA_LSB (1U << 20) /* 1b */
#define DPMAIF_INFRA_REQ_LSB (1U << 21) /* 1b */
#define DPMAIF_APSRC_REQ_LSB (1U << 22) /* 1b */
#define DPMAIF_VRF18_REQ_LSB (1U << 23) /* 1b */
#define DPMAIF_DDR_EN_LSB (1U << 24) /* 1b */
/* MD32PCM_WAKEUP_STA (0x10006000+0x130) */
#define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */
/* MD32PCM_EVENT_STA (0x10006000+0x134) */
#define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */
/* SPM_WAKEUP_STA (0x10006000+0x138) */
#define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */
#define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */
/* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */
#define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */
/* SPM_WAKEUP_MISC (0x10006000+0x140) */
#define GIC_WAKEUP_LSB (1U << 0) /* 10b */
#define DVFSRC_IRQ_LSB (1U << 16) /* 1b */
#define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */
#define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */
#define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */
#define TWAM_IRQ_B_LSB (1U << 21) /* 1b */
#define PMSR_IRQ_B_SET0_LSB (1U << 22) /* 1b */
#define PMSR_IRQ_B_SET1_LSB (1U << 23) /* 1b */
#define PMSR_IRQ_B_SET2_LSB (1U << 24) /* 1b */
#define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */
#define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */
#define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */
#define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */
#define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */
#define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */
#define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */
/* MM_DVFS_HALT (0x10006000+0x144) */
#define MM_DVFS_HALT_LSB (1U << 0) /* 5b */
/* BUS_PROTECT_RDY (0x10006000+0x150) */
#define PROTECT_READY_LSB (1U << 0) /* 32b */
/* BUS_PROTECT1_RDY (0x10006000+0x154) */
#define PROTECT1_READY_LSB (1U << 0) /* 32b */
/* BUS_PROTECT2_RDY (0x10006000+0x158) */
#define PROTECT2_READY_LSB (1U << 0) /* 32b */
/* BUS_PROTECT3_RDY (0x10006000+0x15C) */
#define PROTECT3_READY_LSB (1U << 0) /* 32b */
/* SUBSYS_IDLE_STA (0x10006000+0x160) */
#define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */
/* PCM_STA (0x10006000+0x164) */
#define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */
#define EXT_SRC_STA_LSB (1U << 4) /* 3b */
/* SRC_REQ_STA_3 (0x10006000+0x168) */
#define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */
#define F26M_STATE_LSB (1U << 16) /* 1b */
#define INFRA_STATE_LSB (1U << 17) /* 1b */
#define APSRC_STATE_LSB (1U << 18) /* 1b */
#define VRF18_STATE_LSB (1U << 19) /* 1b */
#define DDR_EN_STATE_LSB (1U << 20) /* 1b */
#define DVFS_STATE_LSB (1U << 21) /* 1b */
#define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */
#define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */
#define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */
#define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */
/* PWR_STATUS (0x10006000+0x16C) */
#define PWR_STATUS_LSB (1U << 0) /* 32b */
/* PWR_STATUS_2ND (0x10006000+0x170) */
#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */
/* CPU_PWR_STATUS (0x10006000+0x174) */
#define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */
#define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */
#define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */
#define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */
#define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */
#define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */
#define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */
#define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */
#define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */
#define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */
/* OTHER_PWR_STATUS (0x10006000+0x178) */
#define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */
/* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */
#define SPM_VTCXO_SLEEP_COUNT_LSB (1U << 0) /* 16b */
#define SPM_VTCXO_WAKE_COUNT_LSB (1U << 16) /* 16b */
/* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */
#define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */
#define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */
/* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */
#define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */
#define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */
/* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */
#define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */
#define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */
/* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */
#define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */
#define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */
/* MD32PCM_STA (0x10006000+0x190) */
#define MD32PCM_HALT_LSB (1U << 0) /* 1b */
#define MD32PCM_GATED_LSB (1U << 1) /* 1b */
/* MD32PCM_PC (0x10006000+0x194) */
#define MON_PC_LSB (1U << 0) /* 32b */
/* DVFSRC_EVENT_STA (0x10006000+0x1A4) */
#define DVFSRC_EVENT_LSB (1U << 0) /* 32b */
/* BUS_PROTECT4_RDY (0x10006000+0x1A8) */
#define PROTECT4_READY_LSB (1U << 0) /* 32b */
/* BUS_PROTECT5_RDY (0x10006000+0x1AC) */
#define PROTECT5_READY_LSB (1U << 0) /* 32b */
/* BUS_PROTECT6_RDY (0x10006000+0x1B0) */
#define PROTECT6_READY_LSB (1U << 0) /* 32b */
/* BUS_PROTECT7_RDY (0x10006000+0x1B4) */
#define PROTECT7_READY_LSB (1U << 0) /* 32b */
/* BUS_PROTECT8_RDY (0x10006000+0x1B8) */
#define PROTECT8_READY_LSB (1U << 0) /* 32b */
/* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */
#define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */
/* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */
#define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */
/* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */
#define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */
/* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */
#define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */
/* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */
#define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */
/* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */
#define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */
/* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */
#define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */
/* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */
#define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */
/* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */
#define TWAM_TIMER_LSB (1U << 0) /* 32b */
/* SPM_CG_CHECK_STA (0x10006000+0x1F4) */
#define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */
#define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */
#define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */
/* SPM_DVFS_STA (0x10006000+0x1F8) */
#define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */
/* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */
#define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */
#define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */
#define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */
/* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */
#define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */
#define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */
#define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */
#define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */
#define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */
/* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */
#define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */
#define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */
#define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */
#define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */
#define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */
#define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */
#define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */
#define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */
/* SPM_CPU0_PWR_CON (0x10006000+0x208) */
#define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */
#define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */
#define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */
#define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */
#define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */
/* SPM_CPU1_PWR_CON (0x10006000+0x20C) */
#define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */
#define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */
#define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */
#define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */
#define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */
/* SPM_CPU2_PWR_CON (0x10006000+0x210) */
#define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */
#define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */
#define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */
#define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */
#define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */
/* SPM_CPU3_PWR_CON (0x10006000+0x214) */
#define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */
#define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */
#define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */
#define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */
#define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */
/* SPM_CPU4_PWR_CON (0x10006000+0x218) */
#define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */
#define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */
#define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */
#define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */
#define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */
/* SPM_CPU5_PWR_CON (0x10006000+0x21C) */
#define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */
#define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */
#define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */
#define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */
#define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */
/* SPM_CPU6_PWR_CON (0x10006000+0x220) */
#define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */
#define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */
#define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */
#define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */
#define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */
/* SPM_CPU7_PWR_CON (0x10006000+0x224) */
#define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */
#define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */
#define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */
#define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */
#define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */
/* ARMPLL_CLK_CON (0x10006000+0x22C) */
#define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */
#define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */
#define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */
#define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */
#define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */
#define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */
#define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */
#define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */
#define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */
#define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */
#define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */
#define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */
#define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */
#define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */
#define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */
#define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */
#define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */
#define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */
#define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */
#define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */
/* MCUSYS_IDLE_STA (0x10006000+0x230) */
#define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */
#define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */
#define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */
#define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */
#define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */
#define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */
#define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */
#define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */
#define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */
#define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */
#define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */
#define WFI_AF_SEL_LSB (1U << 24) /* 8b */
/* GIC_WAKEUP_STA (0x10006000+0x234) */
#define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */
/* CPU_SPARE_CON (0x10006000+0x238) */
#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */
/* CPU_SPARE_CON_SET (0x10006000+0x23C) */
#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */
/* CPU_SPARE_CON_CLR (0x10006000+0x240) */
#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
/* ARMPLL_CLK_SEL (0x10006000+0x244) */
#define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */
/* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */
#define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */
/* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */
#define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */
/* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */
#define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */
/* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */
#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */
/* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */
#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */
/* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */
#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */
/* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */
#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */
/* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */
#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */
/* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */
#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */
/* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */
#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */
/* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */
#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */
/* MP0_CPU0_WFI_EN (0x10006000+0x280) */
#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */
/* MP0_CPU1_WFI_EN (0x10006000+0x284) */
#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */
/* MP0_CPU2_WFI_EN (0x10006000+0x288) */
#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */
/* MP0_CPU3_WFI_EN (0x10006000+0x28C) */
#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */
/* MP0_CPU4_WFI_EN (0x10006000+0x290) */
#define MP0_CPU4_WFI_EN_LSB (1U << 0) /* 1b */
/* MP0_CPU5_WFI_EN (0x10006000+0x294) */
#define MP0_CPU5_WFI_EN_LSB (1U << 0) /* 1b */
/* MP0_CPU6_WFI_EN (0x10006000+0x298) */
#define MP0_CPU6_WFI_EN_LSB (1U << 0) /* 1b */
/* MP0_CPU7_WFI_EN (0x10006000+0x29C) */
#define MP0_CPU7_WFI_EN_LSB (1U << 0) /* 1b */
/* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */
#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */
/* ROOT_CORE_ADDR (0x10006000+0x2A4) */
#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */
/* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */
#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */
/* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */
#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */
/* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */
#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */
/* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */
#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */
/* SW2SPM_INT (0x10006000+0x2E0) */
#define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */
/* SW2SPM_INT_SET (0x10006000+0x2E4) */
#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */
/* SW2SPM_INT_CLR (0x10006000+0x2E8) */
#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */
/* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */
#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
/* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */
#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
/* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */
#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
/* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */
#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
/* SW2SPM_CFG (0x10006000+0x2FC) */
#define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */
/* MD1_PWR_CON (0x10006000+0x300) */
#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */
#define MD1_PWR_ON_LSB (1U << 2) /* 1b */
#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* CONN_PWR_CON (0x10006000+0x304) */
#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */
#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */
#define CONN_PWR_ON_LSB (1U << 2) /* 1b */
#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
/* MFG0_PWR_CON (0x10006000+0x308) */
#define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */
#define MFG0_PWR_ON_LSB (1U << 2) /* 1b */
#define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* MFG1_PWR_CON (0x10006000+0x30C) */
#define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */
#define MFG1_PWR_ON_LSB (1U << 2) /* 1b */
#define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* MFG2_PWR_CON (0x10006000+0x310) */
#define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */
#define MFG2_PWR_ON_LSB (1U << 2) /* 1b */
#define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* MFG3_PWR_CON (0x10006000+0x314) */
#define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */
#define MFG3_PWR_ON_LSB (1U << 2) /* 1b */
#define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* MFG4_PWR_CON (0x10006000+0x318) */
#define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */
#define MFG4_PWR_ON_LSB (1U << 2) /* 1b */
#define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* MFG5_PWR_CON (0x10006000+0x31C) */
#define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */
#define MFG5_PWR_ON_LSB (1U << 2) /* 1b */
#define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* MFG6_PWR_CON (0x10006000+0x320) */
#define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */
#define MFG6_PWR_ON_LSB (1U << 2) /* 1b */
#define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* IFR_PWR_CON (0x10006000+0x324) */
#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */
#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */
#define IFR_PWR_ON_LSB (1U << 2) /* 1b */
#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* IFR_SUB_PWR_CON (0x10006000+0x328) */
#define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */
#define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */
#define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */
#define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* DPY_PWR_CON (0x10006000+0x32C) */
#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */
#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */
#define DPY_PWR_ON_LSB (1U << 2) /* 1b */
#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define DPY_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* ISP_PWR_CON (0x10006000+0x330) */
#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */
#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */
#define ISP_PWR_ON_LSB (1U << 2) /* 1b */
#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* ISP2_PWR_CON (0x10006000+0x334) */
#define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */
#define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */
#define ISP2_PWR_ON_LSB (1U << 2) /* 1b */
#define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* IPE_PWR_CON (0x10006000+0x338) */
#define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */
#define IPE_PWR_ISO_LSB (1U << 1) /* 1b */
#define IPE_PWR_ON_LSB (1U << 2) /* 1b */
#define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* VDE_PWR_CON (0x10006000+0x33C) */
#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */
#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */
#define VDE_PWR_ON_LSB (1U << 2) /* 1b */
#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* VDE2_PWR_CON (0x10006000+0x340) */
#define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */
#define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */
#define VDE2_PWR_ON_LSB (1U << 2) /* 1b */
#define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* VEN_PWR_CON (0x10006000+0x344) */
#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */
#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */
#define VEN_PWR_ON_LSB (1U << 2) /* 1b */
#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* VEN_CORE1_PWR_CON (0x10006000+0x348) */
#define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */
#define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */
#define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */
#define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* MDP_PWR_CON (0x10006000+0x34C) */
#define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MDP_PWR_ISO_LSB (1U << 1) /* 1b */
#define MDP_PWR_ON_LSB (1U << 2) /* 1b */
#define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* DIS_PWR_CON (0x10006000+0x350) */
#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */
#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */
#define DIS_PWR_ON_LSB (1U << 2) /* 1b */
#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* AUDIO_PWR_CON (0x10006000+0x354) */
#define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */
#define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */
#define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */
#define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* ADSP_PWR_CON (0x10006000+0x358) */
#define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */
#define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */
#define ADSP_PWR_ON_LSB (1U << 2) /* 1b */
#define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */
#define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
#define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */
#define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */
#define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
#define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */
/* CAM_PWR_CON (0x10006000+0x35C) */
#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */
#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */
#define CAM_PWR_ON_LSB (1U << 2) /* 1b */
#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* CAM_RAWA_PWR_CON (0x10006000+0x360) */
#define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */
#define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */
#define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */
#define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* CAM_RAWB_PWR_CON (0x10006000+0x364) */
#define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */
#define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */
#define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */
#define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* CAM_RAWC_PWR_CON (0x10006000+0x368) */
#define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */
#define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */
#define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */
#define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* SYSRAM_CON (0x10006000+0x36C) */
#define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */
#define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */
/* SYSROM_CON (0x10006000+0x370) */
#define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */
/* SSPM_SRAM_CON (0x10006000+0x374) */
#define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
#define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */
/* SCP_SRAM_CON (0x10006000+0x378) */
#define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
#define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */
/* DPY_SHU_SRAM_CON (0x10006000+0x37C) */
#define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
#define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */
/* UFS_SRAM_CON (0x10006000+0x380) */
#define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */
#define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */
/* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */
#define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
#define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */
/* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */
#define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
#define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 6b */
/* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */
#define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
#define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 6b */
/* USB_SRAM_CON (0x10006000+0x390) */
#define USB_SRAM_PDN_LSB (1U << 0) /* 7b */
/* DUMMY_SRAM_CON (0x10006000+0x394) */
#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */
/* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */
#define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
#define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
/* EXT_BUCK_ISO (0x10006000+0x39C) */
#define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
#define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
#define ADSP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */
#define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */
/* DXCC_SRAM_CON (0x10006000+0x3A0) */
#define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
#define DXCC_SRAM_PDN_LSB (1U << 16) /* 1b */
/* MSDC_SRAM_CON (0x10006000+0x3A4) */
#define MSDC_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MSDC_PWR_ISO_LSB (1U << 1) /* 1b */
#define MSDC_PWR_ON_LSB (1U << 2) /* 1b */
#define MSDC_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define MSDC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MSDC_SRAM_CKISO_LSB (1U << 5) /* 1b */
#define MSDC_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
#define MSDC_SRAM_PDN_LSB (1U << 8) /* 1b */
#define MSDC_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */
#define SC_MSDC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
#define SC_MSDC_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */
/* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */
#define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */
/* DP_TX_PWR_CON (0x10006000+0x3AC) */
#define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */
#define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */
#define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */
#define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* DPMAIF_SRAM_CON (0x10006000+0x3B0) */
#define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
#define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */
/* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */
#define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
#define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 2b */
/* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */
#define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
#define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 1b */
/* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */
#define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */
#define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
#define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
#define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 1b */
/* MCUPM_SRAM_CON (0x10006000+0x3C0) */
#define MCUPM_PWR_RST_B_LSB (1U << 0) /* 1b */
#define MCUPM_PWR_ISO_LSB (1U << 1) /* 1b */
#define MCUPM_PWR_ON_LSB (1U << 2) /* 1b */
#define MCUPM_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define MCUPM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define MCUPM_SRAM_CKISO_LSB (1U << 5) /* 1b */
#define MCUPM_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
#define MCUPM_SRAM_PDN_LSB (1U << 8) /* 1b */
#define MCUPM_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */
#define SC_MCUPM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
#define SC_MCUPM_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */
/* DPY2_PWR_CON (0x10006000+0x3C4) */
#define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */
#define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */
#define DPY2_PWR_ON_LSB (1U << 2) /* 1b */
#define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* PERI_PWR_CON (0x10006000+0x3C8) */
#define PERI_PWR_RST_B_LSB (1U << 0) /* 1b */
#define PERI_PWR_ISO_LSB (1U << 1) /* 1b */
#define PERI_PWR_ON_LSB (1U << 2) /* 1b */
#define PERI_PWR_ON_2ND_LSB (1U << 3) /* 1b */
#define PERI_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
#define PERI_SRAM_PDN_LSB (1U << 8) /* 1b */
#define SC_PERI_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
/* SPM_MEM_CK_SEL (0x10006000+0x400) */
#define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */
#define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */
/* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */
#define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */
#define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */
#define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */
#define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */
#define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_EMI_BW_MODE (0x10006000+0x418) */
#define EMI_BW_MODE_LSB (1U << 0) /* 1b */
#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */
#define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */
#define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */
/* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */
#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */
/* ULPOSC_CON (0x10006000+0x420) */
#define ULPOSC_EN_LSB (1U << 0) /* 1b */
#define ULPOSC_RST_LSB (1U << 1) /* 1b */
#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */
#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */
/* SPM2MM_CON (0x10006000+0x424) */
#define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */
#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */
#define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */
#define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */
#define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */
#define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */
#define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */
#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */
#define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */
#define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */
/* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */
#define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */
/* SPM2MCUPM_CON (0x10006000+0x42C) */
#define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */
#define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */
/* AP_MDSRC_REQ (0x10006000+0x430) */
#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */
#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */
#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */
#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */
#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */
#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */
/* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */
#define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */
/* SPM2MD_DVFS_CON (0x10006000+0x438) */
#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */
/* MD2SPM_DVFS_CON (0x10006000+0x43C) */
#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */
/* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */
#define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */
#define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */
#define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_PLL_CON (0x10006000+0x44C) */
#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */
#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */
#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */
#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */
#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */
#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */
#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */
#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */
#define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */
#define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */
/* CPU_DVFS_REQ (0x10006000+0x450) */
#define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */
/* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */
#define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */
#define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */
/* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */
#define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */
/* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */
#define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */
/* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */
#define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */
/* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */
#define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */
/* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */
#define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */
#define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */
/* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */
#define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */
/* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */
#define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */
/* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */
#define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */
#define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */
#define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */
#define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */
#define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */
#define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */
/* RELAY_DVFS_LEVEL (0x10006000+0x478) */
#define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */
/* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */
#define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */
#define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */
#define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */
#define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */
#define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */
#define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */
#define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */
#define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */
#define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */
#define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */
#define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */
#define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */
#define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */
#define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */
#define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */
/* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */
#define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */
#define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */
#define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */
#define SW_DMYRD_EN_LSB (1U << 6) /* 2b */
#define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */
#define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */
#define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */
#define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */
#define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */
#define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */
#define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */
#define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */
#define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */
#define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */
/* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */
#define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */
#define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */
#define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */
#define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */
#define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */
#define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */
#define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */
#define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */
#define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */
#define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */
#define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */
/* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */
#define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */
#define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */
#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */
#define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */
#define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */
#define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */
#define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */
#define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */
/* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */
#define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */
#define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */
#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */
#define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */
#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */
#define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */
#define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */
#define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */
#define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */
#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */
#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */
#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */
#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */
#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */
#define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */
/* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */
#define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */
#define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */
#define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */
#define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */
#define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */
#define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */
#define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */
#define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */
#define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */
#define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */
#define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */
#define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */
#define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */
/* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */
#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */
#define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */
#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */
#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */
#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */
#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */
#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */
#define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */
#define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */
#define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */
#define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */
/* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */
#define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */
#define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */
#define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */
#define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */
#define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */
#define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */
#define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */
#define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */
/* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */
#define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */
#define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */
#define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */
#define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */
#define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */
#define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */
#define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */
#define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */
#define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */
#define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */
#define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */
#define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */
#define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */
#define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */
#define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */
#define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */
#define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */
#define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */
#define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */
#define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */
#define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */
#define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */
/* SPM_DVFS_LEVEL (0x10006000+0x4A4) */
#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */
/* SPM_CIRQ_CON (0x10006000+0x4A8) */
#define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */
/* SPM_DVFS_MISC (0x10006000+0x4AC) */
#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */
#define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */
#define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */
#define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */
#define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */
#define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */
#define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */
#define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */
#define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */
#define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */
/* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */
#define VS1_INIT_LEVEL_LSB (1U << 0) /* 2b */
#define VS1_INIT_LSB (1U << 2) /* 1b */
#define VS1_CURR_LEVEL_LSB (1U << 3) /* 2b */
#define VS1_NEXT_LEVEL_LSB (1U << 5) /* 2b */
#define VS1_VOTE_LEVEL_LSB (1U << 7) /* 2b */
#define VS1_TRIGGER_LSB (1U << 9) /* 1b */
#define VS2_INIT_LEVEL_LSB (1U << 10) /* 3b */
#define VS2_INIT_LSB (1U << 13) /* 1b */
#define VS2_CURR_LEVEL_LSB (1U << 14) /* 3b */
#define VS2_NEXT_LEVEL_LSB (1U << 17) /* 3b */
#define VS2_VOTE_LEVEL_LSB (1U << 20) /* 3b */
#define VS2_TRIGGER_LSB (1U << 23) /* 1b */
#define VS1_FORCE_LSB (1U << 24) /* 1b */
#define VS2_FORCE_LSB (1U << 25) /* 1b */
#define VS1_VOTE_LEVEL_FORCE_LSB (1U << 26) /* 2b */
#define VS2_VOTE_LEVEL_FORCE_LSB (1U << 28) /* 3b */
/* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */
#define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */
/* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */
#define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */
/* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */
#define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */
/* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */
#define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */
/* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */
#define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */
/* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */
#define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */
/* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */
#define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */
/* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */
#define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */
/* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */
#define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */
/* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */
#define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */
/* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */
#define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */
/* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */
#define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */
/* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */
#define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */
/* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */
#define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */
/* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */
#define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */
/* SPM_CG_CHECK_CON (0x10006000+0x4F0) */
#define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */
#define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */
#define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */
#define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */
#define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */
#define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */
#define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */
#define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */
#define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */
/* SPM_SRC_RDY_STA (0x10006000+0x4F4) */
#define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */
#define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */
/* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */
#define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */
#define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */
/* SPM_FORCE_DVFS (0x10006000+0x4FC) */
#define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */
/* SRCLKEN_RC_CFG (0x10006000+0x500) */
#define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */
/* RC_CENTRAL_CFG1 (0x10006000+0x504) */
#define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */
/* RC_CENTRAL_CFG2 (0x10006000+0x508) */
#define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */
/* RC_CMD_ARB_CFG (0x10006000+0x50C) */
#define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */
/* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */
#define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */
#define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */
/* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */
#define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */
#define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */
/* RC_DCXO_FPM_CFG (0x10006000+0x518) */
#define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */
/* RC_CENTRAL_CFG3 (0x10006000+0x51C) */
#define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */
/* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */
#define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
#define RC_SW_SRCLKEN_RC (1U << 3) /* 1b */
#define RC_SW_SRCLKEN_FPM (1U << 4) /* 1b */
/* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */
#define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */
#define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */
#define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */
#define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */
#define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */
#define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */
#define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */
#define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */
#define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */
#define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */
#define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */
#define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
/* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */
#define RC_SRCLKEN_SW_CON_CFG_LSB (1U << 0) /* 32b */
/* RC_CENTRAL_CFG4 (0x10006000+0x558) */
#define RC_CENTRAL_CFG4_LSB (1U << 0) /* 32b */
/* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */
#define RC_PROTOCOL_CHK_CFG_LSB (1U << 0) /* 32b */
/* RC_DEBUG_CFG (0x10006000+0x564) */
#define RC_DEBUG_CFG_LSB (1U << 0) /* 32b */
/* RC_MISC_0 (0x10006000+0x5B4) */
#define SRCCLKENO_LSB (1U << 0) /* 2b */
#define PCM_SRCCLKENO_LSB (1U << 3) /* 2b */
#define RC_VREQ_LSB (1U << 5) /* 1b */
#define RC_SPM_SRCCLKENO_0_ACK_LSB (1U << 6) /* 1b */
/* RC_SPM_CTRL (0x10006000+0x5B8) */
#define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */
#define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */
#define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */
/* SUBSYS_INTF_CFG (0x10006000+0x5BC) */
#define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */
#define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */
/* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */
#define PCM_WDT_LATCH_25_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */
#define PCM_WDT_LATCH_26_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */
#define PCM_WDT_LATCH_27_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */
#define PCM_WDT_LATCH_28_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */
#define PCM_WDT_LATCH_29_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */
#define PCM_WDT_LATCH_30_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */
#define PCM_WDT_LATCH_31_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */
#define PCM_WDT_LATCH_32_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */
#define PCM_WDT_LATCH_33_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */
#define PCM_WDT_LATCH_34_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */
#define PCM_WDT_LATCH_35_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */
#define PCM_WDT_LATCH_36_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */
#define PCM_WDT_LATCH_37_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */
#define PCM_WDT_LATCH_38_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */
#define PCM_WDT_LATCH_39_LSB (1U << 0) /* 32b */
/* SPM_SW_FLAG_0 (0x10006000+0x600) */
#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */
/* SPM_SW_DEBUG_0 (0x10006000+0x604) */
#define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */
/* SPM_SW_FLAG_1 (0x10006000+0x608) */
#define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */
/* SPM_SW_DEBUG_1 (0x10006000+0x60C) */
#define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */
/* SPM_SW_RSV_0 (0x10006000+0x610) */
#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */
/* SPM_SW_RSV_1 (0x10006000+0x614) */
#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */
/* SPM_SW_RSV_2 (0x10006000+0x618) */
#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */
/* SPM_SW_RSV_3 (0x10006000+0x61C) */
#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */
/* SPM_SW_RSV_4 (0x10006000+0x620) */
#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */
/* SPM_SW_RSV_5 (0x10006000+0x624) */
#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */
/* SPM_SW_RSV_6 (0x10006000+0x628) */
#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */
/* SPM_SW_RSV_7 (0x10006000+0x62C) */
#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */
/* SPM_SW_RSV_8 (0x10006000+0x630) */
#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */
/* SPM_BK_WAKE_EVENT (0x10006000+0x634) */
#define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */
/* SPM_BK_VTCXO_DUR (0x10006000+0x638) */
#define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */
/* SPM_BK_WAKE_MISC (0x10006000+0x63C) */
#define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */
/* SPM_BK_PCM_TIMER (0x10006000+0x640) */
#define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */
/* SPM_RSV_CON_0 (0x10006000+0x650) */
#define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */
/* SPM_RSV_CON_1 (0x10006000+0x654) */
#define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */
/* SPM_RSV_STA_0 (0x10006000+0x658) */
#define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */
/* SPM_RSV_STA_1 (0x10006000+0x65C) */
#define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */
/* SPM_SPARE_CON (0x10006000+0x660) */
#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */
/* SPM_SPARE_CON_SET (0x10006000+0x664) */
#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */
/* SPM_SPARE_CON_CLR (0x10006000+0x668) */
#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
/* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */
#define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 5b */
#define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 8) /* 5b */
/* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */
#define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 5b */
#define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 8) /* 5b */
/* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */
#define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 5b */
#define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 8) /* 5b */
/* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */
#define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 5b */
#define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 8) /* 5b */
/* SCP_VCORE_LEVEL (0x10006000+0x67C) */
#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */
/* SC_MM_CK_SEL_CON (0x10006000+0x680) */
#define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */
#define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */
/* SPARE_ACK_MASK (0x10006000+0x684) */
#define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_CROSS_WAKE_M04_REQ (0x10006000+0x688) */
#define SPM_CROSS_WAKE_M04_REQ_LSB (1U << 0) /* 5b */
#define SPM_CROSS_WAKE_M04_CHK_LSB (1U << 8) /* 5b */
/* SPM_DV_CON_0 (0x10006000+0x68C) */
#define SPM_DV_CON_0_LSB (1U << 0) /* 32b */
/* SPM_DV_CON_1 (0x10006000+0x690) */
#define SPM_DV_CON_1_LSB (1U << 0) /* 32b */
/* SPM_DV_STA (0x10006000+0x694) */
#define SPM_DV_STA_LSB (1U << 0) /* 32b */
/* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */
#define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */
/* SPM_SEMA_M0 (0x10006000+0x69C) */
#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */
/* SPM_SEMA_M1 (0x10006000+0x6A0) */
#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */
/* SPM_SEMA_M2 (0x10006000+0x6A4) */
#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */
/* SPM_SEMA_M3 (0x10006000+0x6A8) */
#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */
/* SPM_SEMA_M4 (0x10006000+0x6AC) */
#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */
/* SPM_SEMA_M5 (0x10006000+0x6B0) */
#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */
/* SPM_SEMA_M6 (0x10006000+0x6B4) */
#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */
/* SPM_SEMA_M7 (0x10006000+0x6B8) */
#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */
/* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */
#define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */
/* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */
#define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */
/* SPM_ADSP_IRQ (0x10006000+0x6C4) */
#define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */
#define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
/* SPM_MD32_IRQ (0x10006000+0x6C8) */
#define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */
#define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */
/* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */
#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */
/* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */
#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */
/* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */
#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */
/* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */
#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */
/* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */
#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
/* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */
#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
/* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */
#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
/* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */
#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
/* UFS_PSRI_SW (0x10006000+0x6EC) */
#define UFS_PSRI_SW_LSB (1U << 0) /* 1b */
/* UFS_PSRI_SW_SET (0x10006000+0x6F0) */
#define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */
/* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */
#define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */
/* SPM_AP_SEMA (0x10006000+0x6F8) */
#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */
/* SPM_SPM_SEMA (0x10006000+0x6FC) */
#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */
/* SPM_DVFS_CON (0x10006000+0x700) */
#define SPM_DVFS_CON_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CON_STA (0x10006000+0x704) */
#define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */
/* SPM_PMIC_SPMI_CON (0x10006000+0x708) */
#define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */
#define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */
#define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */
#define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */
/* SPM_DVFS_CMD0 (0x10006000+0x710) */
#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD1 (0x10006000+0x714) */
#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD2 (0x10006000+0x718) */
#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD3 (0x10006000+0x71C) */
#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD4 (0x10006000+0x720) */
#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD5 (0x10006000+0x724) */
#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD6 (0x10006000+0x728) */
#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD7 (0x10006000+0x72C) */
#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD8 (0x10006000+0x730) */
#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD9 (0x10006000+0x734) */
#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD10 (0x10006000+0x738) */
#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD11 (0x10006000+0x73C) */
#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD12 (0x10006000+0x740) */
#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD13 (0x10006000+0x744) */
#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD14 (0x10006000+0x748) */
#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD15 (0x10006000+0x74C) */
#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD16 (0x10006000+0x750) */
#define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD17 (0x10006000+0x754) */
#define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD18 (0x10006000+0x758) */
#define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD19 (0x10006000+0x75C) */
#define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD20 (0x10006000+0x760) */
#define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD21 (0x10006000+0x764) */
#define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD22 (0x10006000+0x768) */
#define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */
/* SPM_DVFS_CMD23 (0x10006000+0x76C) */
#define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */
/* SYS_TIMER_VALUE_L (0x10006000+0x770) */
#define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */
/* SYS_TIMER_VALUE_H (0x10006000+0x774) */
#define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */
/* SYS_TIMER_START_L (0x10006000+0x778) */
#define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */
/* SYS_TIMER_START_H (0x10006000+0x77C) */
#define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */
#define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */
#define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */
#define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */
#define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */
#define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */
#define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */
#define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */
#define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */
#define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */
#define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */
#define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */
#define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */
#define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */
#define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */
#define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */
#define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */
#define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */
#define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */
#define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */
#define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */
#define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */
#define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */
#define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */
#define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */
#define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */
#define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */
#define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */
#define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */
#define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */
#define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */
#define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */
/* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */
#define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_0 (0x10006000+0x800) */
#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_1 (0x10006000+0x804) */
#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_2 (0x10006000+0x808) */
#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */
#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_4 (0x10006000+0x810) */
#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_5 (0x10006000+0x814) */
#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_6 (0x10006000+0x818) */
#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */
#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_8 (0x10006000+0x820) */
#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_9 (0x10006000+0x824) */
#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_10 (0x10006000+0x828) */
#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_11 (0x10006000+0x82C) */
#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_12 (0x10006000+0x830) */
#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_13 (0x10006000+0x834) */
#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_14 (0x10006000+0x838) */
#define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_15 (0x10006000+0x83C) */
#define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_16 (0x10006000+0x840) */
#define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_17 (0x10006000+0x844) */
#define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_18 (0x10006000+0x848) */
#define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */
#define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */
#define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */
#define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */
#define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */
#define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */
#define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */
/* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */
#define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */
/* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */
#define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */
/* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */
#define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */
/* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */
#define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */
/* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */
#define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */
/* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */
#define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */
/* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */
#define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */
/* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */
#define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
/* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */
#define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */
#define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */
#define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */
#define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */
#define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */
#define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */
#define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */
#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */
#define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */
#define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */
#define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */
/* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */
#define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */
#define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */
/* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */
#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */
#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */
#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */
#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */
/* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */
#define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */
#define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */
/* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */
#define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */
/* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */
#define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */
/* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */
#define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */
#define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */
#define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */
#define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */
#define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */
#define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */
#define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */
#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */
#define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */
#define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */
#define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */
/* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */
#define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */
#define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */
/* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */
#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */
#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */
#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */
#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */
/* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */
#define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */
#define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */
/* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */
#define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */
/* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */
#define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */
/* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */
#define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */
#define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */
#define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */
#define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */
#define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */
#define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */
#define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */
#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */
#define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */
#define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */
#define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */
/* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */
#define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */
#define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */
/* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */
#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */
#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */
#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */
#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */
/* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */
#define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */
#define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */
/* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */
#define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */
/* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */
#define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */
/* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */
#define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */
#define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */
#define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */
#define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */
#define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */
#define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */
#define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */
#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */
#define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */
#define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */
#define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */
/* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */
#define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */
#define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */
/* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */
#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */
#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */
#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */
#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */
/* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */
#define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */
#define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */
/* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */
#define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */
/* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */
#define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */
/* SPM_COUNTER_0 (0x10006000+0x978) */
#define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */
#define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */
#define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */
#define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */
#define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */
#define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */
/* SPM_COUNTER_1 (0x10006000+0x97C) */
#define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */
#define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */
#define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */
#define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */
#define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */
#define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */
/* SPM_COUNTER_2 (0x10006000+0x980) */
#define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */
#define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */
#define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */
#define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */
#define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */
#define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */
/* SYS_TIMER_CON (0x10006000+0x98C) */
#define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */
#define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */
#define SYS_TIMER_ID_LSB (1U << 8) /* 8b */
#define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */
/* RC_FSM_STA_0 (0x10006000+0xE00) */
#define RC_FSM_STA_0_LSB (1U << 0) /* 32b */
/* RC_CMD_STA_0 (0x10006000+0xE04) */
#define RC_CMD_STA_0_LSB (1U << 0) /* 32b */
/* RC_CMD_STA_1 (0x10006000+0xE08) */
#define RC_CMD_STA_1_LSB (1U << 0) /* 32b */
/* RC_SPI_STA_0 (0x10006000+0xE0C) */
#define RC_SPI_STA_0_LSB (1U << 0) /* 32b */
/* RC_PI_PO_STA_0 (0x10006000+0xE10) */
#define RC_PI_PO_STA_0_LSB (1U << 0) /* 32b */
/* RC_M00_REQ_STA_0 (0x10006000+0xE14) */
#define RC_M00_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */
#define RC_M01_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M02_REQ_STA_0 (0x10006000+0xE20) */
#define RC_M02_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M03_REQ_STA_0 (0x10006000+0xE24) */
#define RC_M03_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M04_REQ_STA_0 (0x10006000+0xE28) */
#define RC_M04_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */
#define RC_M05_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M06_REQ_STA_0 (0x10006000+0xE30) */
#define RC_M06_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M07_REQ_STA_0 (0x10006000+0xE34) */
#define RC_M07_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M08_REQ_STA_0 (0x10006000+0xE38) */
#define RC_M08_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */
#define RC_M09_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M10_REQ_STA_0 (0x10006000+0xE40) */
#define RC_M10_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M11_REQ_STA_0 (0x10006000+0xE44) */
#define RC_M11_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_M12_REQ_STA_0 (0x10006000+0xE48) */
#define RC_M12_REQ_STA_0_LSB (1U << 0) /* 32b */
/* RC_DEBUG_STA_0 (0x10006000+0xE4C) */
#define RC_DEBUG_STA_0_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */
#define RO_PMRC_TRACE_00_LSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */
#define RO_PMRC_TRACE_00_MSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */
#define RO_PMRC_TRACE_01_LSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */
#define RO_PMRC_TRACE_01_MSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */
#define RO_PMRC_TRACE_02_LSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */
#define RO_PMRC_TRACE_02_MSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */
#define RO_PMRC_TRACE_03_LSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */
#define RO_PMRC_TRACE_03_MSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */
#define RO_PMRC_TRACE_04_LSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */
#define RO_PMRC_TRACE_04_MSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */
#define RO_PMRC_TRACE_05_LSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */
#define RO_PMRC_TRACE_05_MSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */
#define RO_PMRC_TRACE_06_LSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */
#define RO_PMRC_TRACE_06_MSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */
#define RO_PMRC_TRACE_07_LSB_LSB (1U << 0) /* 32b */
/* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */
#define RO_PMRC_TRACE_07_MSB_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */
#define RC_SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */
#define RC_SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */
#define RC_SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */
#define RC_SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */
#define RC_SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */
#define RC_SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */
#define RC_SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */
#define RC_SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */
#define RC_SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */
#define RC_SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */
#define RC_SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */
#define RC_SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */
#define RC_SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */
#define RC_SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */
#define RC_SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */
/* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */
#define RC_SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_19 (0x10006000+0xED8) */
#define PCM_WDT_LATCH_19_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */
#define PCM_WDT_LATCH_20_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */
#define PCM_WDT_LATCH_21_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */
#define PCM_WDT_LATCH_22_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */
#define PCM_WDT_LATCH_23_LSB (1U << 0) /* 32b */
/* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */
#define PCM_WDT_LATCH_24_LSB (1U << 0) /* 32b */
/* PMSR_LAST_DAT (0x10006000+0xF00) */
#define PMSR_LAST_DAT_LSB (1U << 0) /* 32b */
/* PMSR_LAST_CNT (0x10006000+0xF04) */
#define PMSR_LAST_CMD_LSB (1U << 0) /* 30b */
#define PMSR_LAST_REQ_LSB (1U << 30) /* 1b */
/* PMSR_LAST_ACK (0x10006000+0xF08) */
#define PMSR_LAST_ACK_LSB (1U << 0) /* 1b */
/* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */
#define REG_PMSR_SIG_SEL_0_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_1_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_2_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_3_LSB (1U << 24) /* 8b */
/* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */
#define REG_PMSR_SIG_SEL_4_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_5_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_6_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_7_LSB (1U << 24) /* 8b */
/* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */
#define REG_PMSR_SIG_SEL_8_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_9_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_10_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_11_LSB (1U << 24) /* 8b */
/* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */
#define REG_PMSR_SIG_SEL_12_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_13_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_14_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_15_LSB (1U << 24) /* 8b */
/* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */
#define REG_PMSR_SIG_SEL_16_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_17_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_18_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_19_LSB (1U << 24) /* 8b */
/* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */
#define REG_PMSR_SIG_SEL_20_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_21_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_22_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_23_LSB (1U << 24) /* 8b */
/* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */
#define REG_PMSR_SIG_SEL_24_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_25_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_26_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_27_LSB (1U << 24) /* 8b */
/* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */
#define REG_PMSR_SIG_SEL_28_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_29_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_30_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_31_LSB (1U << 24) /* 8b */
/* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */
#define REG_PMSR_SIG_SEL_32_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_33_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_34_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_35_LSB (1U << 24) /* 8b */
/* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */
#define REG_PMSR_SIG_SEL_36_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_37_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_38_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_39_LSB (1U << 24) /* 8b */
/* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */
#define REG_PMSR_SIG_SEL_40_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_41_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_42_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_43_LSB (1U << 24) /* 8b */
/* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */
#define REG_PMSR_SIG_SEL_44_LSB (1U << 0) /* 8b */
#define REG_PMSR_SIG_SEL_45_LSB (1U << 8) /* 8b */
#define REG_PMSR_SIG_SEL_46_LSB (1U << 16) /* 8b */
#define REG_PMSR_SIG_SEL_47_LSB (1U << 24) /* 8b */
/* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */
#define PMSR_TIMER_SET0_LSB (1U << 0) /* 32b */
/* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */
#define PMSR_TIMER_SET1_LSB (1U << 0) /* 32b */
/* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */
#define PMSR_TIMER_SET2_LSB (1U << 0) /* 32b */
/* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */
#define PMSR_ENABLE_SET0_LSB (1U << 0) /* 1b */
#define PMSR_ENABLE_SET1_LSB (1U << 1) /* 1b */
#define PMSR_ENABLE_SET2_LSB (1U << 2) /* 1b */
#define PMSR_IRQ_CLR_SET0_LSB (1U << 3) /* 1b */
#define PMSR_IRQ_CLR_SET1_LSB (1U << 4) /* 1b */
#define PMSR_IRQ_CLR_SET2_LSB (1U << 5) /* 1b */
#define PMSR_SPEED_MODE_EN_SET0_LSB (1U << 6) /* 1b */
#define PMSR_SPEED_MODE_EN_SET1_LSB (1U << 7) /* 1b */
#define PMSR_SPEED_MODE_EN_SET2_LSB (1U << 8) /* 1b */
#define PMSR_EVENT_CLR_SET0_LSB (1U << 9) /* 1b */
#define PMSR_EVENT_CLR_SET1_LSB (1U << 10) /* 1b */
#define PMSR_EVENT_CLR_SET2_LSB (1U << 11) /* 1b */
#define REG_PMSR_IRQ_MASK_SET0_LSB (1U << 12) /* 1b */
#define REG_PMSR_IRQ_MASK_SET1_LSB (1U << 13) /* 1b */
#define REG_PMSR_IRQ_MASK_SET2_LSB (1U << 14) /* 1b */
#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15) /* 1b */
#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16) /* 1b */
#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17) /* 1b */
#define PMSR_GEN_SW_RST_EN_LSB (1U << 18) /* 1b */
#define PMSR_MODULE_ENABLE_LSB (1U << 19) /* 1b */
#define PMSR_MODE_LSB (1U << 20) /* 2b */
#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29) /* 1b */
#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30) /* 1b */
#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31) /* 1b */
/* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */
#define PMSR_COUNTER_THRES_LSB (1U << 0) /* 32b */
/* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */
#define PMSR_DEBUG_IN_0_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */
#define PMSR_DEBUG_IN_1_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */
#define PMSR_DEBUG_IN_2_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */
#define PMSR_DEBUG_IN_3_MASK_B_LSB (1U << 0) /* 32b */
/* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */
#define PMSR_SW_RST_EN_SET0_LSB (1U << 0) /* 1b */
#define PMSR_SW_RST_EN_SET1_LSB (1U << 1) /* 1b */
#define PMSR_SW_RST_EN_SET2_LSB (1U << 2) /* 1b */
/* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */
#define REG_PMSR_MON_TYPE_0_LSB (1U << 0) /* 2b */
#define REG_PMSR_MON_TYPE_1_LSB (1U << 2) /* 2b */
#define REG_PMSR_MON_TYPE_2_LSB (1U << 4) /* 2b */
#define REG_PMSR_MON_TYPE_3_LSB (1U << 6) /* 2b */
#define REG_PMSR_MON_TYPE_4_LSB (1U << 8) /* 2b */
#define REG_PMSR_MON_TYPE_5_LSB (1U << 10) /* 2b */
#define REG_PMSR_MON_TYPE_6_LSB (1U << 12) /* 2b */
#define REG_PMSR_MON_TYPE_7_LSB (1U << 14) /* 2b */
#define REG_PMSR_MON_TYPE_8_LSB (1U << 16) /* 2b */
#define REG_PMSR_MON_TYPE_9_LSB (1U << 18) /* 2b */
#define REG_PMSR_MON_TYPE_10_LSB (1U << 20) /* 2b */
#define REG_PMSR_MON_TYPE_11_LSB (1U << 22) /* 2b */
#define REG_PMSR_MON_TYPE_12_LSB (1U << 24) /* 2b */
#define REG_PMSR_MON_TYPE_13_LSB (1U << 26) /* 2b */
#define REG_PMSR_MON_TYPE_14_LSB (1U << 28) /* 2b */
#define REG_PMSR_MON_TYPE_15_LSB (1U << 30) /* 2b */
/* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */
#define REG_PMSR_MON_TYPE_16_LSB (1U << 0) /* 2b */
#define REG_PMSR_MON_TYPE_17_LSB (1U << 2) /* 2b */
#define REG_PMSR_MON_TYPE_18_LSB (1U << 4) /* 2b */
#define REG_PMSR_MON_TYPE_19_LSB (1U << 6) /* 2b */
#define REG_PMSR_MON_TYPE_20_LSB (1U << 8) /* 2b */
#define REG_PMSR_MON_TYPE_21_LSB (1U << 10) /* 2b */
#define REG_PMSR_MON_TYPE_22_LSB (1U << 12) /* 2b */
#define REG_PMSR_MON_TYPE_23_LSB (1U << 14) /* 2b */
#define REG_PMSR_MON_TYPE_24_LSB (1U << 16) /* 2b */
#define REG_PMSR_MON_TYPE_25_LSB (1U << 18) /* 2b */
#define REG_PMSR_MON_TYPE_26_LSB (1U << 20) /* 2b */
#define REG_PMSR_MON_TYPE_27_LSB (1U << 22) /* 2b */
#define REG_PMSR_MON_TYPE_28_LSB (1U << 24) /* 2b */
#define REG_PMSR_MON_TYPE_29_LSB (1U << 26) /* 2b */
#define REG_PMSR_MON_TYPE_30_LSB (1U << 28) /* 2b */
#define REG_PMSR_MON_TYPE_31_LSB (1U << 30) /* 2b */
/* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */
#define REG_PMSR_MON_TYPE_32_LSB (1U << 0) /* 2b */
#define REG_PMSR_MON_TYPE_33_LSB (1U << 2) /* 2b */
#define REG_PMSR_MON_TYPE_34_LSB (1U << 4) /* 2b */
#define REG_PMSR_MON_TYPE_35_LSB (1U << 6) /* 2b */
#define REG_PMSR_MON_TYPE_36_LSB (1U << 8) /* 2b */
#define REG_PMSR_MON_TYPE_37_LSB (1U << 10) /* 2b */
#define REG_PMSR_MON_TYPE_38_LSB (1U << 12) /* 2b */
#define REG_PMSR_MON_TYPE_39_LSB (1U << 14) /* 2b */
#define REG_PMSR_MON_TYPE_40_LSB (1U << 16) /* 2b */
#define REG_PMSR_MON_TYPE_41_LSB (1U << 18) /* 2b */
#define REG_PMSR_MON_TYPE_42_LSB (1U << 20) /* 2b */
#define REG_PMSR_MON_TYPE_43_LSB (1U << 22) /* 2b */
#define REG_PMSR_MON_TYPE_44_LSB (1U << 24) /* 2b */
#define REG_PMSR_MON_TYPE_45_LSB (1U << 26) /* 2b */
#define REG_PMSR_MON_TYPE_46_LSB (1U << 28) /* 2b */
#define REG_PMSR_MON_TYPE_47_LSB (1U << 30) /* 2b */
/* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */
#define REG_PMSR_WINDOW_LEN_SET0_LSB (1U << 0) /* 32b */
/* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */
#define REG_PMSR_WINDOW_LEN_SET1_LSB (1U << 0) /* 32b */
/* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */
#define REG_PMSR_WINDOW_LEN_SET2_LSB (1U << 0) /* 32b */
#define SPM_PROJECT_CODE 0xb16
#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
#endif /* MT_SPM_REG */
plat/mediatek/mt8192/drivers/spm/mt_spm_resource_req.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_RESOURCE_REQ_H
#define MT_SPM_RESOURCE_REQ_H
/* SPM resource request internal bit */
#define MT_SPM_BIT_XO_FPM 0
#define MT_SPM_BIT_26M 1
#define MT_SPM_BIT_INFRA 2
#define MT_SPM_BIT_SYSPLL 3
#define MT_SPM_BIT_DRAM_S0 4
#define MT_SPM_BIT_DRAM_S1 5
/* SPM resource request internal bit_mask */
#define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM)
#define MT_SPM_26M BIT(MT_SPM_BIT_26M)
#define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA)
#define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL)
#define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0)
#define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1)
#endif /* MT_SPM_RESOURCE_REQ_H */
plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.c 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_conservation.h>
#include <mt_spm_internal.h>
#include <mt_spm_rc_internal.h>
#include <mt_spm_reg.h>
#include <mt_spm_resource_req.h>
#include <mt_spm_suspend.h>
#include <plat_pm.h>
#include <uart.h>
#define SPM_SUSPEND_SLEEP_PCM_FLAG \
(SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
SPM_FLAG_USE_SRCCLKENO2 | \
SPM_FLAG_ENABLE_MD_MUMTAS | \
SPM_FLAG_SRAM_SLEEP_CTRL)
#define SPM_SUSPEND_SLEEP_PCM_FLAG1 \
(SPM_FLAG1_DISABLE_MD26M_CK_OFF)
#define SPM_SUSPEND_PCM_FLAG \
(SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_ENABLE_TIA_WORKAROUND | \
SPM_FLAG_ENABLE_MD_MUMTAS | \
SPM_FLAG_SRAM_SLEEP_CTRL)
#define SPM_SUSPEND_PCM_FLAG1 \
(SPM_FLAG1_DISABLE_MD26M_CK_OFF)
#define __WAKE_SRC_FOR_SUSPEND_COMMON__ \
(R12_PCM_TIMER | \
R12_KP_IRQ_B | \
R12_APWDT_EVENT_B | \
R12_APXGPT1_EVENT_B | \
R12_CONN2AP_SPM_WAKEUP_B | \
R12_EINT_EVENT_B | \
R12_CONN_WDT_IRQ_B | \
R12_CCIF0_EVENT_B | \
R12_SSPM2SPM_WAKEUP_B | \
R12_SCP2SPM_WAKEUP_B | \
R12_ADSP2SPM_WAKEUP_B | \
R12_USBX_CDSC_B | \
R12_USBX_POWERDWN_B | \
R12_SYS_TIMER_EVENT_B | \
R12_EINT_EVENT_SECURE_B | \
R12_CCIF1_EVENT_B | \
R12_SYS_CIRQ_IRQ_B | \
R12_MD2AP_PEER_EVENT_B | \
R12_MD1_WDT_B | \
R12_CLDMA_EVENT_B | \
R12_REG_CPU_WAKEUP | \
R12_APUSYS_WAKE_HOST_B | \
R12_PCIE_BRIDGE_IRQ | \
R12_PCIE_IRQ)
#if defined(CFG_MICROTRUST_TEE_SUPPORT)
#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
#else
#define WAKE_SRC_FOR_SUSPEND \
(__WAKE_SRC_FOR_SUSPEND_COMMON__ | \
R12_SEJ_EVENT_B)
#endif
static struct pwr_ctrl suspend_ctrl = {
.wake_src = WAKE_SRC_FOR_SUSPEND,
.pcm_flags = SPM_SUSPEND_PCM_FLAG | SPM_FLAG_DISABLE_INFRA_PDN,
.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1,
/* Auto-gen Start */
/* SPM_AP_STANDBY_CON */
.reg_wfi_op = 0,
.reg_wfi_type = 0,
.reg_mp0_cputop_idle_mask = 0,
.reg_mp1_cputop_idle_mask = 0,
.reg_mcusys_idle_mask = 0,
.reg_md_apsrc_1_sel = 0,
.reg_md_apsrc_0_sel = 0,
.reg_conn_apsrc_sel = 0,
/* SPM_SRC6_MASK */
.reg_dpmaif_srcclkena_mask_b = 1,
.reg_dpmaif_infra_req_mask_b = 1,
.reg_dpmaif_apsrc_req_mask_b = 1,
.reg_dpmaif_vrf18_req_mask_b = 1,
.reg_dpmaif_ddr_en_mask_b = 1,
/* SPM_SRC_REQ */
.reg_spm_apsrc_req = 0,
.reg_spm_f26m_req = 0,
.reg_spm_infra_req = 0,
.reg_spm_vrf18_req = 0,
.reg_spm_ddr_en_req = 0,
.reg_spm_dvfs_req = 0,
.reg_spm_sw_mailbox_req = 0,
.reg_spm_sspm_mailbox_req = 0,
.reg_spm_adsp_mailbox_req = 0,
.reg_spm_scp_mailbox_req = 0,
/* SPM_SRC_MASK */
.reg_md_srcclkena_0_mask_b = 1,
.reg_md_srcclkena2infra_req_0_mask_b = 0,
.reg_md_apsrc2infra_req_0_mask_b = 1,
.reg_md_apsrc_req_0_mask_b = 1,
.reg_md_vrf18_req_0_mask_b = 1,
.reg_md_ddr_en_0_mask_b = 1,
.reg_md_srcclkena_1_mask_b = 0,
.reg_md_srcclkena2infra_req_1_mask_b = 0,
.reg_md_apsrc2infra_req_1_mask_b = 0,
.reg_md_apsrc_req_1_mask_b = 0,
.reg_md_vrf18_req_1_mask_b = 0,
.reg_md_ddr_en_1_mask_b = 0,
.reg_conn_srcclkena_mask_b = 1,
.reg_conn_srcclkenb_mask_b = 0,
.reg_conn_infra_req_mask_b = 1,
.reg_conn_apsrc_req_mask_b = 1,
.reg_conn_vrf18_req_mask_b = 1,
.reg_conn_ddr_en_mask_b = 1,
.reg_conn_vfe28_mask_b = 0,
.reg_srcclkeni0_srcclkena_mask_b = 1,
.reg_srcclkeni0_infra_req_mask_b = 1,
.reg_srcclkeni1_srcclkena_mask_b = 0,
.reg_srcclkeni1_infra_req_mask_b = 0,
.reg_srcclkeni2_srcclkena_mask_b = 0,
.reg_srcclkeni2_infra_req_mask_b = 0,
.reg_infrasys_apsrc_req_mask_b = 0,
.reg_infrasys_ddr_en_mask_b = 1,
.reg_md32_srcclkena_mask_b = 1,
.reg_md32_infra_req_mask_b = 1,
.reg_md32_apsrc_req_mask_b = 1,
.reg_md32_vrf18_req_mask_b = 1,
.reg_md32_ddr_en_mask_b = 1,
/* SPM_SRC2_MASK */
.reg_scp_srcclkena_mask_b = 1,
.reg_scp_infra_req_mask_b = 1,
.reg_scp_apsrc_req_mask_b = 1,
.reg_scp_vrf18_req_mask_b = 1,
.reg_scp_ddr_en_mask_b = 1,
.reg_audio_dsp_srcclkena_mask_b = 1,
.reg_audio_dsp_infra_req_mask_b = 1,
.reg_audio_dsp_apsrc_req_mask_b = 1,
.reg_audio_dsp_vrf18_req_mask_b = 1,
.reg_audio_dsp_ddr_en_mask_b = 1,
.reg_ufs_srcclkena_mask_b = 1,
.reg_ufs_infra_req_mask_b = 1,
.reg_ufs_apsrc_req_mask_b = 1,
.reg_ufs_vrf18_req_mask_b = 1,
.reg_ufs_ddr_en_mask_b = 1,
.reg_disp0_apsrc_req_mask_b = 1,
.reg_disp0_ddr_en_mask_b = 1,
.reg_disp1_apsrc_req_mask_b = 1,
.reg_disp1_ddr_en_mask_b = 1,
.reg_gce_infra_req_mask_b = 1,
.reg_gce_apsrc_req_mask_b = 1,
.reg_gce_vrf18_req_mask_b = 1,
.reg_gce_ddr_en_mask_b = 1,
.reg_apu_srcclkena_mask_b = 1,
.reg_apu_infra_req_mask_b = 1,
.reg_apu_apsrc_req_mask_b = 1,
.reg_apu_vrf18_req_mask_b = 1,
.reg_apu_ddr_en_mask_b = 1,
.reg_cg_check_srcclkena_mask_b = 0,
.reg_cg_check_apsrc_req_mask_b = 0,
.reg_cg_check_vrf18_req_mask_b = 0,
.reg_cg_check_ddr_en_mask_b = 0,
/* SPM_SRC3_MASK */
.reg_dvfsrc_event_trigger_mask_b = 1,
.reg_sw2spm_int0_mask_b = 0,
.reg_sw2spm_int1_mask_b = 0,
.reg_sw2spm_int2_mask_b = 0,
.reg_sw2spm_int3_mask_b = 0,
.reg_sc_adsp2spm_wakeup_mask_b = 0,
.reg_sc_sspm2spm_wakeup_mask_b = 0,
.reg_sc_scp2spm_wakeup_mask_b = 0,
.reg_csyspwrreq_mask = 1,
.reg_spm_srcclkena_reserved_mask_b = 0,
.reg_spm_infra_req_reserved_mask_b = 0,
.reg_spm_apsrc_req_reserved_mask_b = 0,
.reg_spm_vrf18_req_reserved_mask_b = 0,
.reg_spm_ddr_en_reserved_mask_b = 0,
.reg_mcupm_srcclkena_mask_b = 1,
.reg_mcupm_infra_req_mask_b = 1,
.reg_mcupm_apsrc_req_mask_b = 1,
.reg_mcupm_vrf18_req_mask_b = 1,
.reg_mcupm_ddr_en_mask_b = 1,
.reg_msdc0_srcclkena_mask_b = 1,
.reg_msdc0_infra_req_mask_b = 1,
.reg_msdc0_apsrc_req_mask_b = 1,
.reg_msdc0_vrf18_req_mask_b = 1,
.reg_msdc0_ddr_en_mask_b = 1,
.reg_msdc1_srcclkena_mask_b = 1,
.reg_msdc1_infra_req_mask_b = 1,
.reg_msdc1_apsrc_req_mask_b = 1,
.reg_msdc1_vrf18_req_mask_b = 1,
.reg_msdc1_ddr_en_mask_b = 1,
/* SPM_SRC4_MASK */
.ccif_event_mask_b = 0xFFF,
.reg_bak_psri_srcclkena_mask_b = 0,
.reg_bak_psri_infra_req_mask_b = 0,
.reg_bak_psri_apsrc_req_mask_b = 0,
.reg_bak_psri_vrf18_req_mask_b = 0,
.reg_bak_psri_ddr_en_mask_b = 0,
.reg_dramc0_md32_infra_req_mask_b = 1,
.reg_dramc0_md32_vrf18_req_mask_b = 0,
.reg_dramc1_md32_infra_req_mask_b = 1,
.reg_dramc1_md32_vrf18_req_mask_b = 0,
.reg_conn_srcclkenb2pwrap_mask_b = 0,
.reg_dramc0_md32_wakeup_mask = 1,
.reg_dramc1_md32_wakeup_mask = 1,
/* SPM_SRC5_MASK */
.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
.reg_mcusys_merge_ddr_en_mask_b = 0x11,
.reg_msdc2_srcclkena_mask_b = 1,
.reg_msdc2_infra_req_mask_b = 1,
.reg_msdc2_apsrc_req_mask_b = 1,
.reg_msdc2_vrf18_req_mask_b = 1,
.reg_msdc2_ddr_en_mask_b = 1,
.reg_pcie_srcclkena_mask_b = 1,
.reg_pcie_infra_req_mask_b = 1,
.reg_pcie_apsrc_req_mask_b = 1,
.reg_pcie_vrf18_req_mask_b = 1,
.reg_pcie_ddr_en_mask_b = 1,
/* SPM_WAKEUP_EVENT_MASK */
.reg_wakeup_event_mask = 0x01382202,
/* SPM_WAKEUP_EVENT_EXT_MASK */
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
/* Auto-gen End */
};
struct spm_lp_scen __spm_suspend = {
.pwrctrl = &suspend_ctrl,
};
int mt_spm_suspend_mode_set(int mode)
{
if (mode == MT_SPM_SUSPEND_SLEEP) {
suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
} else {
suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
}
return 0;
}
int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
unsigned int resource_req)
{
/* If FMAudio / ADSP is active, change to sleep suspend mode */
if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP);
}
/* Notify MCUPM that device is going suspend flow */
mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN);
/* Notify UART to sleep */
mt_uart_save();
return spm_conservation(state_id, ext_opand,
&__spm_suspend, resource_req);
}
void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
struct wake_status **status)
{
spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status);
/* Notify UART to wakeup */
mt_uart_restore();
/* Notify MCUPM that device leave suspend */
mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0);
/* If FMAudio / ADSP is active, change back to suspend mode */
if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN);
}
}
void mt_spm_suspend_init(void)
{
spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl);
}
plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_SUSPEND_H
#define MT_SPM_SUSPEND_H
#include <mt_spm_internal.h>
#define MCUPM_MBOX_OFFSET_PDN 0x0C55FDA8
#define MCUPM_POWER_DOWN 0x4D50444E
enum MT_SPM_SUSPEND_MODE {
MT_SPM_SUSPEND_SYSTEM_PDN,
MT_SPM_SUSPEND_SLEEP,
};
extern int mt_spm_suspend_mode_set(int mode);
extern int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
unsigned int reosuce_req);
extern void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
struct wake_status **status);
extern void mt_spm_suspend_init(void);
#endif /* MT_SPM_SUSPEND_H */
plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.c 0 → 100644
View file @ 258f6a2d
/*
* Copyright(C)2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
#include <stdio.h>
#include <string.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <plat/common/platform.h>
#include <lib/utils_def.h>
#include <mtk_sip_svc.h>
#include <plat_pm.h>
#include <platform_def.h>
#include "mt_spm.h"
#include "mt_spm_internal.h"
#include "mt_spm_reg.h"
#include "mt_spm_vcorefs.h"
#include "mt_spm_pmic_wrap.h"
#define VCORE_CT_ENABLE (1U << 5)
#define SW_REQ5_INIT_VAL (6U << 12)
#define V_VMODE_SHIFT 0
#define VCORE_HV 105
#define VCORE_LV 95
#define PMIC_STEP_UV 6250
static const struct reg_config dvfsrc_init_configs[] = {
/* Setup opp table */
{ DVFSRC_LEVEL_LABEL_0_1, 0x50436053 },
{ DVFSRC_LEVEL_LABEL_2_3, 0x40335042 },
{ DVFSRC_LEVEL_LABEL_4_5, 0x40314032 },
{ DVFSRC_LEVEL_LABEL_6_7, 0x30223023 },
{ DVFSRC_LEVEL_LABEL_8_9, 0x20133021 },
{ DVFSRC_LEVEL_LABEL_10_11, 0x20112012 },
{ DVFSRC_LEVEL_LABEL_12_13, 0x10032010 },
{ DVFSRC_LEVEL_LABEL_14_15, 0x10011002 },
{ DVFSRC_LEVEL_LABEL_16_17, 0x00131000 },
{ DVFSRC_LEVEL_LABEL_18_19, 0x00110012 },
{ DVFSRC_LEVEL_LABEL_20_21, 0x00000010 },
/* Setup hw emi qos policy */
{ DVFSRC_DDR_REQUEST, 0x00004321 },
{ DVFSRC_DDR_REQUEST3, 0x00000065 },
/* Setup up for PCIe */
{ DVFSRC_PCIE_VCORE_REQ, 0x0A298001 },
/* Setup up HRT QOS policy */
{ DVFSRC_HRT_BW_BASE, 0x00000004 },
{ DVFSRC_HRT_REQ_UNIT, 0x0000001E },
{ DVFSRC_HRT_HIGH_3, 0x18A618A6 },
{ DVFSRC_HRT_HIGH_2, 0x18A61183 },
{ DVFSRC_HRT_HIGH_1, 0x0D690B80 },
{ DVFSRC_HRT_HIGH, 0x070804B0 },
{ DVFSRC_HRT_LOW_3, 0x18A518A5 },
{ DVFSRC_HRT_LOW_2, 0x18A51182 },
{ DVFSRC_HRT_LOW_1, 0x0D680B7F },
{ DVFSRC_HRT_LOW, 0x070704AF },
{ DVFSRC_HRT_REQUEST, 0x66654321 },
/* Setup up SRT QOS policy */
{ DVFSRC_QOS_EN, 0x0011007C },
{ DVFSRC_DDR_QOS0, 0x00000019 },
{ DVFSRC_DDR_QOS1, 0x00000026 },
{ DVFSRC_DDR_QOS2, 0x00000033 },
{ DVFSRC_DDR_QOS3, 0x0000003B },
{ DVFSRC_DDR_QOS4, 0x0000004C },
{ DVFSRC_DDR_QOS5, 0x00000066 },
{ DVFSRC_DDR_QOS6, 0x00000066 },
{ DVFSRC_DDR_REQUEST5, 0x54321000 },
{ DVFSRC_DDR_REQUEST7, 0x66000000 },
/* Setup up hifi request policy */
{ DVFSRC_DDR_REQUEST6, 0x66543210 },
/* Setup up hw request vcore policy */
{ DVFSRC_VCORE_USER_REQ, 0x00010A29 },
/* Setup misc*/
{ DVFSRC_TIMEOUT_NEXTREQ, 0x00000015 },
{ DVFSRC_RSRV_5, 0x00000001 },
{ DVFSRC_INT_EN, 0x00000002 },
/* Init opp and enable dvfsrc*/
{ DVFSRC_CURRENT_FORCE, 0x00000001 },
{ DVFSRC_BASIC_CONTROL, 0x0298444B },
{ DVFSRC_BASIC_CONTROL, 0x0298054B },
{ DVFSRC_CURRENT_FORCE, 0x00000000 },
};
static struct pwr_ctrl vcorefs_ctrl = {
.wake_src = R12_REG_CPU_WAKEUP,
/* default VCORE DVFS is disabled */
.pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
SPM_FLAG_DISABLE_VCORE_DVS |
SPM_FLAG_DISABLE_VCORE_DFS),
/* Auto-gen Start */
/* SPM_AP_STANDBY_CON */
.reg_wfi_op = 0,
.reg_wfi_type = 0,
.reg_mp0_cputop_idle_mask = 0,
.reg_mp1_cputop_idle_mask = 0,
.reg_mcusys_idle_mask = 0,
.reg_md_apsrc_1_sel = 0,
.reg_md_apsrc_0_sel = 0,
.reg_conn_apsrc_sel = 0,
/* SPM_SRC_REQ */
.reg_spm_apsrc_req = 0,
.reg_spm_f26m_req = 0,
.reg_spm_infra_req = 0,
.reg_spm_vrf18_req = 0,
.reg_spm_ddr_en_req = 1,
.reg_spm_dvfs_req = 0,
.reg_spm_sw_mailbox_req = 0,
.reg_spm_sspm_mailbox_req = 0,
.reg_spm_adsp_mailbox_req = 0,
.reg_spm_scp_mailbox_req = 0,
/* SPM_SRC6_MASK */
.reg_dpmaif_srcclkena_mask_b = 1,
.reg_dpmaif_infra_req_mask_b = 1,
.reg_dpmaif_apsrc_req_mask_b = 1,
.reg_dpmaif_vrf18_req_mask_b = 1,
.reg_dpmaif_ddr_en_mask_b = 1,
/* SPM_SRC_MASK */
.reg_md_srcclkena_0_mask_b = 1,
.reg_md_srcclkena2infra_req_0_mask_b = 0,
.reg_md_apsrc2infra_req_0_mask_b = 1,
.reg_md_apsrc_req_0_mask_b = 1,
.reg_md_vrf18_req_0_mask_b = 1,
.reg_md_ddr_en_0_mask_b = 1,
.reg_md_srcclkena_1_mask_b = 0,
.reg_md_srcclkena2infra_req_1_mask_b = 0,
.reg_md_apsrc2infra_req_1_mask_b = 0,
.reg_md_apsrc_req_1_mask_b = 0,
.reg_md_vrf18_req_1_mask_b = 0,
.reg_md_ddr_en_1_mask_b = 0,
.reg_conn_srcclkena_mask_b = 1,
.reg_conn_srcclkenb_mask_b = 0,
.reg_conn_infra_req_mask_b = 1,
.reg_conn_apsrc_req_mask_b = 1,
.reg_conn_vrf18_req_mask_b = 1,
.reg_conn_ddr_en_mask_b = 1,
.reg_conn_vfe28_mask_b = 0,
.reg_srcclkeni0_srcclkena_mask_b = 1,
.reg_srcclkeni0_infra_req_mask_b = 1,
.reg_srcclkeni1_srcclkena_mask_b = 0,
.reg_srcclkeni1_infra_req_mask_b = 0,
.reg_srcclkeni2_srcclkena_mask_b = 0,
.reg_srcclkeni2_infra_req_mask_b = 0,
.reg_infrasys_apsrc_req_mask_b = 0,
.reg_infrasys_ddr_en_mask_b = 1,
.reg_md32_srcclkena_mask_b = 1,
.reg_md32_infra_req_mask_b = 1,
.reg_md32_apsrc_req_mask_b = 1,
.reg_md32_vrf18_req_mask_b = 1,
.reg_md32_ddr_en_mask_b = 1,
/* SPM_SRC2_MASK */
.reg_scp_srcclkena_mask_b = 1,
.reg_scp_infra_req_mask_b = 1,
.reg_scp_apsrc_req_mask_b = 1,
.reg_scp_vrf18_req_mask_b = 1,
.reg_scp_ddr_en_mask_b = 1,
.reg_audio_dsp_srcclkena_mask_b = 1,
.reg_audio_dsp_infra_req_mask_b = 1,
.reg_audio_dsp_apsrc_req_mask_b = 1,
.reg_audio_dsp_vrf18_req_mask_b = 1,
.reg_audio_dsp_ddr_en_mask_b = 1,
.reg_ufs_srcclkena_mask_b = 1,
.reg_ufs_infra_req_mask_b = 1,
.reg_ufs_apsrc_req_mask_b = 1,
.reg_ufs_vrf18_req_mask_b = 1,
.reg_ufs_ddr_en_mask_b = 1,
.reg_disp0_apsrc_req_mask_b = 1,
.reg_disp0_ddr_en_mask_b = 1,
.reg_disp1_apsrc_req_mask_b = 1,
.reg_disp1_ddr_en_mask_b = 1,
.reg_gce_infra_req_mask_b = 1,
.reg_gce_apsrc_req_mask_b = 1,
.reg_gce_vrf18_req_mask_b = 1,
.reg_gce_ddr_en_mask_b = 1,
.reg_apu_srcclkena_mask_b = 1,
.reg_apu_infra_req_mask_b = 1,
.reg_apu_apsrc_req_mask_b = 1,
.reg_apu_vrf18_req_mask_b = 1,
.reg_apu_ddr_en_mask_b = 1,
.reg_cg_check_srcclkena_mask_b = 0,
.reg_cg_check_apsrc_req_mask_b = 0,
.reg_cg_check_vrf18_req_mask_b = 0,
.reg_cg_check_ddr_en_mask_b = 0,
/* SPM_SRC3_MASK */
.reg_dvfsrc_event_trigger_mask_b = 1,
.reg_sw2spm_int0_mask_b = 0,
.reg_sw2spm_int1_mask_b = 0,
.reg_sw2spm_int2_mask_b = 0,
.reg_sw2spm_int3_mask_b = 0,
.reg_sc_adsp2spm_wakeup_mask_b = 0,
.reg_sc_sspm2spm_wakeup_mask_b = 0,
.reg_sc_scp2spm_wakeup_mask_b = 0,
.reg_csyspwrreq_mask = 1,
.reg_spm_srcclkena_reserved_mask_b = 0,
.reg_spm_infra_req_reserved_mask_b = 0,
.reg_spm_apsrc_req_reserved_mask_b = 0,
.reg_spm_vrf18_req_reserved_mask_b = 0,
.reg_spm_ddr_en_reserved_mask_b = 0,
.reg_mcupm_srcclkena_mask_b = 1,
.reg_mcupm_infra_req_mask_b = 1,
.reg_mcupm_apsrc_req_mask_b = 1,
.reg_mcupm_vrf18_req_mask_b = 1,
.reg_mcupm_ddr_en_mask_b = 1,
.reg_msdc0_srcclkena_mask_b = 1,
.reg_msdc0_infra_req_mask_b = 1,
.reg_msdc0_apsrc_req_mask_b = 1,
.reg_msdc0_vrf18_req_mask_b = 1,
.reg_msdc0_ddr_en_mask_b = 1,
.reg_msdc1_srcclkena_mask_b = 1,
.reg_msdc1_infra_req_mask_b = 1,
.reg_msdc1_apsrc_req_mask_b = 1,
.reg_msdc1_vrf18_req_mask_b = 1,
.reg_msdc1_ddr_en_mask_b = 1,
/* SPM_SRC4_MASK */
.ccif_event_mask_b = 0xFFF,
.reg_bak_psri_srcclkena_mask_b = 0,
.reg_bak_psri_infra_req_mask_b = 0,
.reg_bak_psri_apsrc_req_mask_b = 0,
.reg_bak_psri_vrf18_req_mask_b = 0,
.reg_bak_psri_ddr_en_mask_b = 0,
.reg_dramc0_md32_infra_req_mask_b = 1,
.reg_dramc0_md32_vrf18_req_mask_b = 0,
.reg_dramc1_md32_infra_req_mask_b = 1,
.reg_dramc1_md32_vrf18_req_mask_b = 0,
.reg_conn_srcclkenb2pwrap_mask_b = 0,
.reg_dramc0_md32_wakeup_mask = 1,
.reg_dramc1_md32_wakeup_mask = 1,
/* SPM_SRC5_MASK */
.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
.reg_mcusys_merge_ddr_en_mask_b = 0x11,
.reg_msdc2_srcclkena_mask_b = 1,
.reg_msdc2_infra_req_mask_b = 1,
.reg_msdc2_apsrc_req_mask_b = 1,
.reg_msdc2_vrf18_req_mask_b = 1,
.reg_msdc2_ddr_en_mask_b = 1,
.reg_pcie_srcclkena_mask_b = 1,
.reg_pcie_infra_req_mask_b = 1,
.reg_pcie_apsrc_req_mask_b = 1,
.reg_pcie_vrf18_req_mask_b = 1,
.reg_pcie_ddr_en_mask_b = 1,
/* SPM_WAKEUP_EVENT_MASK */
.reg_wakeup_event_mask = 0xEFFFFFFF,
/* SPM_WAKEUP_EVENT_EXT_MASK */
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
/* Auto-gen End */
};
struct spm_lp_scen __spm_vcorefs = {
.pwrctrl = &vcorefs_ctrl,
};
static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val)
{
if (cmd < NR_IDX_ALL) {
mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val);
} else {
INFO("cmd out of range!\n");
}
}
void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
{
mmio_clrsetbits_32(SPM_DVFS_MISC, SPM_DVFS_FORCE_ENABLE_LSB,
SPM_DVFSRC_ENABLE_LSB);
mmio_write_32(SPM_DVFS_LEVEL, 0x00000001);
mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001);
}
void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
const struct pwr_ctrl *src_pwr_ctrl)
{
uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
SPM_FLAG_DISABLE_VCORE_DFS |
SPM_FLAG_ENABLE_VOLTAGE_BIN;
dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) |
(src_pwr_ctrl->pcm_flags & dvfs_mask);
if (dest_pwr_ctrl->pcm_flags_cust > 0U) {
dest_pwr_ctrl->pcm_flags_cust =
(dest_pwr_ctrl->pcm_flags_cust & (~dvfs_mask)) |
(src_pwr_ctrl->pcm_flags & dvfs_mask);
}
}
static void spm_go_to_vcorefs(void)
{
__spm_set_power_control(__spm_vcorefs.pwrctrl);
__spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
__spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
__spm_send_cpu_wakeup_event();
}
static void dvfsrc_init(void)
{
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(dvfsrc_init_configs); i++) {
mmio_write_32(dvfsrc_init_configs[i].offset,
dvfsrc_init_configs[i].val);
}
}
static uint32_t spm_vcorefs_get_efuse_data(void)
{
return mmio_read_32(VCORE_VB_EFUSE);
}
static uint32_t is_rising_need(void)
{
return ((spm_vcorefs_get_efuse_data() & 0xF) == 11U) ? 1U : 0U;
}
static void spm_vcorefs_vcore_setting(uint64_t flag)
{
uint32_t dvfs_v_mode, dvfsrc_rsrv, i;
uint32_t opp_uv[] = {725000U, 650000U, 600000U, 575000U};
dvfsrc_rsrv = mmio_read_32(DVFSRC_RSRV_4);
dvfs_v_mode = (dvfsrc_rsrv >> V_VMODE_SHIFT) & 0x3;
if (is_rising_need() != 0U) {
opp_uv[2] = 625000U;
opp_uv[3] = 600000U;
}
for (i = 0; i < ARRAY_SIZE(opp_uv); i++) {
if (dvfs_v_mode == 3U) {
/* LV */
opp_uv[i] = round_down((opp_uv[i] * VCORE_LV) / 100U,
PMIC_STEP_UV);
} else if (dvfs_v_mode == 1U) {
/* HV */
opp_uv[i] = round_up((opp_uv[i] * VCORE_HV) / 100U,
PMIC_STEP_UV);
}
spm_vcorefs_pwarp_cmd(i, __vcore_uv_to_pmic(opp_uv[i]));
}
}
uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4)
{
uint64_t cmd = x1;
uint64_t spm_flags;
switch (cmd) {
case VCOREFS_SMC_CMD_INIT:
/* vcore_dvfs init + kick */
mmio_write_32(DVFSRC_SW_REQ5, SW_REQ5_INIT_VAL);
spm_dvfsfw_init(0ULL, 0ULL);
spm_vcorefs_vcore_setting(x3 & 0xF);
spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
if ((x2 & 0x1) > 0U) {
spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
}
if ((x2 & 0x2) > 0U) {
spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
}
if ((mmio_read_32(DVFSRC_RSRV_4) & VCORE_CT_ENABLE) > 0U) {
spm_flags |= SPM_FLAG_ENABLE_VOLTAGE_BIN;
}
set_pwrctrl_pcm_flags(__spm_vcorefs.pwrctrl, spm_flags);
spm_go_to_vcorefs();
dvfsrc_init();
*x4 = 0U;
case VCOREFS_SMC_CMD_KICK:
mmio_write_32(DVFSRC_SW_REQ5, 0U);
break;
default:
break;
}
return 0ULL;
}
plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright(C)2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_VCOREFS_H
#define MT_SPM_VCOREFS_H
uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4);
enum vcorefs_smc_cmd {
VCOREFS_SMC_CMD_0,
VCOREFS_SMC_CMD_1,
VCOREFS_SMC_CMD_2,
VCOREFS_SMC_CMD_3,
VCOREFS_SMC_CMD_4,
/* check spmfw status */
VCOREFS_SMC_CMD_5,
/* get spmfw type */
VCOREFS_SMC_CMD_6,
/* get spm reg status */
VCOREFS_SMC_CMD_7,
NUM_VCOREFS_SMC_CMD,
};
enum vcorefs_smc_cmd_new {
VCOREFS_SMC_CMD_INIT = 0,
VCOREFS_SMC_CMD_KICK = 1,
};
#define _VCORE_BASE_UV 400000
#define _VCORE_STEP_UV 6250
/* PMIC */
#define __vcore_pmic_to_uv(pmic) \
(((pmic) * _VCORE_STEP_UV) + _VCORE_BASE_UV)
#define __vcore_uv_to_pmic(uv) /* pmic >= uv */ \
((((uv) - _VCORE_BASE_UV) + (_VCORE_STEP_UV - 1)) / _VCORE_STEP_UV)
struct reg_config {
uint32_t offset;
uint32_t val;
};
#define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
#define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
#define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8)
#define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC)
#define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE0)
#define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4)
#define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8)
#define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100)
#define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104)
#define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108)
#define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C)
#define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110)
#define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114)
#define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118)
#define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C)
#define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280)
#define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294)
#define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610)
#define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614)
#define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00)
#define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04)
#define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08)
#define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C)
#define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10)
#define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14)
#define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18)
#define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34)
#define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38)
#define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C)
#define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40)
#define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44)
#define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60)
#define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4)
#define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8)
#define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC)
#define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0)
#define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4)
#define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8)
#define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC)
#define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0)
#define DVFSRC_LAST (DVFSRC_BASE + 0xAE4)
#define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8)
#define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC)
#define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0)
#define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4)
#define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8)
#define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC)
#define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00)
#define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04)
#define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08)
#define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C)
#define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0)
#define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4)
#define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8)
#define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC)
#define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00)
#define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04)
#define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08)
#define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C)
#define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0)
#define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4)
#define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8)
#define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC)
#define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00)
#define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04)
#define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08)
#define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C)
#define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10)
#define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14)
#define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18)
#define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C)
#define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38)
#define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C)
#define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C)
#define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50)
#define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54)
#define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58)
#define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C)
#define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60)
#define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64)
#define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68)
#define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C)
#define VCORE_VB_EFUSE (0x11C105E8)
#endif /* MT_SPM_VCOREFS_H */
plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_notifier.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_SSPM_NOTIFIER_H
#define MT_SPM_SSPM_NOTIFIER_H
enum MT_SPM_SSPM_NOTIFY_ID {
MT_SPM_NOTIFY_LP_ENTER,
MT_SPM_NOTIFY_LP_LEAVE,
};
int mt_spm_sspm_notify(int type, unsigned int lp_mode);
static inline int mt_spm_sspm_notify_u32(int type, unsigned int lp_mode)
{
return mt_spm_sspm_notify(type, lp_mode);
}
#endif /* MT_SPM_SSPM_NOTIFIER_H */
plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_intc.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_SSPM_INTC_H
#define MT_SPM_SSPM_INTC_H
#include <mt_spm_reg.h>
#define MT_SPM_SSPM_INTC_SEL_0 0x10
#define MT_SPM_SSPM_INTC_SEL_1 0x20
#define MT_SPM_SSPM_INTC_SEL_2 0x40
#define MT_SPM_SSPM_INTC_SEL_3 0x80
#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) \
(((0x10 << id) | (sg << id)) & 0xff)
#define MT_SPM_SSPM_INTC0_HIGH MT_SPM_SSPM_INTC_TRIGGER(0, 1)
#define MT_SPM_SSPM_INTC0_LOW MT_SPM_SSPM_INTC_TRIGGER(0, 0)
#define MT_SPM_SSPM_INTC1_HIGH MT_SPM_SSPM_INTC_TRIGGER(1, 1)
#define MT_SPM_SSPM_INTC1_LOW MT_SPM_SSPM_INTC_TRIGGER(1, 0)
#define MT_SPM_SSPM_INTC2_HIGH MT_SPM_SSPM_INTC_TRIGGER(2, 1)
#define MT_SPM_SSPM_INTC2_LOW MT_SPM_SSPM_INTC_TRIGGER(2, 0)
#define MT_SPM_SSPM_INTC3_HIGH MT_SPM_SSPM_INTC_TRIGGER(3, 1)
#define MT_SPM_SSPM_INTC3_LOW MT_SPM_SSPM_INTC_TRIGGER(3, 0)
#define DO_SPM_SSPM_LP_SUSPEND() \
mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_HIGH)
#define DO_SPM_SSPM_LP_RESUME() \
mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_LOW)
#endif /* MT_SPM_SSPM_INTC_H */
plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_notifier.c 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
#include <lib/mmio.h>
#include <mt_spm_notifier.h>
#include <mt_spm_sspm_intc.h>
#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x)
#define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
#define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0)
#define SSPM_MBOX_SPM_LP_LOOKUP2 MT_SPM_MBOX(1)
#define SSPM_MBOX_SPM_LP1 MT_SPM_MBOX(2)
#define SSPM_MBOX_SPM_LP2 MT_SPM_MBOX(3)
#define MCUPM_MBOX_OFFSET_LP 0x0C55FDA4
#define MCUPM_MBOX_ENTER_LP 0x454e0000
#define MCUPM_MBOX_LEAVE_LP 0x4c450000
#define MCUPM_MBOX_SLEEP_MASK 0x0000FFFF
int mt_spm_sspm_notify(int type, unsigned int lp_mode)
{
switch (type) {
case MT_SPM_NOTIFY_LP_ENTER:
mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
mmio_write_32(MCUPM_MBOX_OFFSET_LP, MCUPM_MBOX_ENTER_LP |
(lp_mode & MCUPM_MBOX_SLEEP_MASK));
DO_SPM_SSPM_LP_SUSPEND();
break;
case MT_SPM_NOTIFY_LP_LEAVE:
mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
mmio_write_32(MCUPM_MBOX_OFFSET_LP, MCUPM_MBOX_LEAVE_LP |
(lp_mode & MCUPM_MBOX_SLEEP_MASK));
DO_SPM_SSPM_LP_RESUME();
break;
default:
break;
}
return 0;
}
plat/mediatek/mt8192/drivers/spm/pcm_def.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PCM_DEF_H
#define PCM_DEF_H
/*
* Auto generated by DE, please DO NOT modify this file directly.
*/
/* --- R0 Define --- */
#define R0_SC_26M_CK_OFF (1U << 0)
#define R0_SC_TX_TRACK_RETRY_EN (1U << 1)
#define R0_SC_MEM_CK_OFF (1U << 2)
#define R0_SC_AXI_CK_OFF (1U << 3)
#define R0_SC_DR_SRAM_LOAD (1U << 4)
#define R0_SC_MD26M_CK_OFF (1U << 5)
#define R0_SC_DPY_MODE_SW (1U << 6)
#define R0_SC_DMSUS_OFF (1U << 7)
#define R0_SC_DPY_2ND_DLL_EN (1U << 8)
#define R0_SC_DR_SRAM_RESTORE (1U << 9)
#define R0_SC_MPLLOUT_OFF (1U << 10)
#define R0_SC_TX_TRACKING_DIS (1U << 11)
#define R0_SC_DPY_DLL_EN (1U << 12)
#define R0_SC_DPY_DLL_CK_EN (1U << 13)
#define R0_SC_DPY_VREF_EN (1U << 14)
#define R0_SC_PHYPLL_EN (1U << 15)
#define R0_SC_DDRPHY_FB_CK_EN (1U << 16)
#define R0_SC_DPY_BCLK_ENABLE (1U << 17)
#define R0_SC_MPLL_OFF (1U << 18)
#define R0_SC_SHU_RESTORE (1U << 19)
#define R0_SC_CKSQ0_OFF (1U << 20)
#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH (1U << 21)
#define R0_SC_DR_SHU_EN (1U << 22)
#define R0_SC_DPHY_PRECAL_UP (1U << 23)
#define R0_SC_MPLL_S_OFF (1U << 24)
#define R0_SC_DPHY_RXDLY_TRACKING_EN (1U << 25)
#define R0_SC_PHYPLL_SHU_EN (1U << 26)
#define R0_SC_PHYPLL2_SHU_EN (1U << 27)
#define R0_SC_PHYPLL_MODE_SW (1U << 28)
#define R0_SC_PHYPLL2_MODE_SW (1U << 29)
#define R0_SC_DR_SHU_LEVEL0 (1U << 30)
#define R0_SC_DR_SHU_LEVEL1 (1U << 31)
/* --- R7 Define --- */
#define R7_PWRAP_SLEEP_REQ (1U << 0)
#define R7_EMI_CLK_OFF_REQ (1U << 1)
#define R7_PCM_BUS_PROTECT_REQ (1U << 2)
#define R7_SPM_CK_UPDATE (1U << 3)
#define R7_SPM_CK_SEL0 (1U << 4)
#define R7_SPM_CK_SEL1 (1U << 5)
#define R7_SPM_LEAVE_DEEPIDLE_REQ (1U << 6)
#define R7_SC_FHC_PAUSE_MPLL (1U << 7)
#define R7_SC_26M_CK_SEL (1U << 8)
#define R7_PCM_TIMER_SET (1U << 9)
#define R7_PCM_TIMER_CLR (1U << 10)
#define R7_SPM_LEAVE_SUSPEND_REQ (1U << 11)
#define R7_CSYSPWRUPACK (1U << 12)
#define R7_PCM_IM_SLP_EN (1U << 13)
#define R7_SRCCLKENO0 (1U << 14)
#define R7_FORCE_DDR_EN_WAKE (1U << 15)
#define R7_SPM_APSRC_INTERNAL_ACK (1U << 16)
#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17)
#define R7_SC_AXI_DCM_DIS (1U << 18)
#define R7_SC_FHC_PAUSE_MEM (1U << 19)
#define R7_SC_FHC_PAUSE_MAIN (1U << 20)
#define R7_SRCCLKENO1 (1U << 21)
#define R7_PCM_WDT_KICK_P (1U << 22)
#define R7_SPM2EMI_S1_MODE_ASYNC (1U << 23)
#define R7_SC_DDR_PST_REQ_PCM (1U << 24)
#define R7_SC_DDR_PST_ABORT_REQ_PCM (1U << 25)
#define R7_PMIC_IRQ_REQ_EN (1U << 26)
#define R7_FORCE_F26M_WAKE (1U << 27)
#define R7_FORCE_APSRC_WAKE (1U << 28)
#define R7_FORCE_INFRA_WAKE (1U << 29)
#define R7_FORCE_VRF18_WAKE (1U << 30)
#define R7_SPM_DDR_EN_INTERNAL_ACK (1U << 31)
/* --- R12 Define --- */
#define R12_PCM_TIMER (1U << 0)
#define R12_TWAM_IRQ_B (1U << 1)
#define R12_KP_IRQ_B (1U << 2)
#define R12_APWDT_EVENT_B (1U << 3)
#define R12_APXGPT1_EVENT_B (1U << 4)
#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5)
#define R12_EINT_EVENT_B (1U << 6)
#define R12_CONN_WDT_IRQ_B (1U << 7)
#define R12_CCIF0_EVENT_B (1U << 8)
#define R12_LOWBATTERY_IRQ_B (1U << 9)
#define R12_SSPM2SPM_WAKEUP_B (1U << 10)
#define R12_SCP2SPM_WAKEUP_B (1U << 11)
#define R12_ADSP2SPM_WAKEUP_B (1U << 12)
#define R12_PCM_WDT_WAKEUP_B (1U << 13)
#define R12_USBX_CDSC_B (1U << 14)
#define R12_USBX_POWERDWN_B (1U << 15)
#define R12_SYS_TIMER_EVENT_B (1U << 16)
#define R12_EINT_EVENT_SECURE_B (1U << 17)
#define R12_CCIF1_EVENT_B (1U << 18)
#define R12_UART0_IRQ_B (1U << 19)
#define R12_AFE_IRQ_MCU_B (1U << 20)
#define R12_THERM_CTRL_EVENT_B (1U << 21)
#define R12_SYS_CIRQ_IRQ_B (1U << 22)
#define R12_MD2AP_PEER_EVENT_B (1U << 23)
#define R12_CSYSPWREQ_B (1U << 24)
#define R12_MD1_WDT_B (1U << 25)
#define R12_CLDMA_EVENT_B (1U << 26)
#define R12_SEJ_EVENT_B (1U << 27)
#define R12_REG_CPU_WAKEUP (1U << 28)
#define R12_APUSYS_WAKE_HOST_B (1U << 29)
#define R12_PCIE_BRIDGE_IRQ (1U << 30)
#define R12_PCIE_IRQ (1U << 31)
/* --- R12ext Define --- */
#define R12EXT_26M_WAKE (1U << 0)
#define R12EXT_26M_SLEEP (1U << 1)
#define R12EXT_INFRA_WAKE (1U << 2)
#define R12EXT_INFRA_SLEEP (1U << 3)
#define R12EXT_APSRC_WAKE (1U << 4)
#define R12EXT_APSRC_SLEEP (1U << 5)
#define R12EXT_VRF18_WAKE (1U << 6)
#define R12EXT_VRF18_SLEEP (1U << 7)
#define R12EXT_DVFS_WAKE (1U << 8)
#define R12EXT_DDREN_WAKE (1U << 9)
#define R12EXT_DDREN_SLEEP (1U << 10)
#define R12EXT_MCU_PM_WFI (1U << 11)
#define R12EXT_SSPM_IDLE (1U << 12)
#define R12EXT_CONN_SRCCLKENB (1U << 13)
#define R12EXT_DRAMC_SSPM_WFI_MERGE (1U << 14)
#define R12EXT_SW_MAILBOX_WAKE (1U << 15)
#define R12EXT_SSPM_MAILBOX_WAKE (1U << 16)
#define R12EXT_ADSP_MAILBOX_WAKE (1U << 17)
#define R12EXT_SCP_MAILBOX_WAKE (1U << 18)
#define R12EXT_SPM_LEAVE_SUSPEND_ACK (1U << 19)
#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK (1U << 20)
#define R12EXT_VS1_TRIGGER (1U << 21)
#define R12EXT_VS2_TRIGGER (1U << 22)
#define R12EXT_COROSS_REQ_APU (1U << 23)
#define R12EXT_CROSS_REQ_L3 (1U << 24)
#define R12EXT_DDR_PST_ACK (1U << 25)
#define R12EXT_BIT26 (1U << 26)
#define R12EXT_BIT27 (1U << 27)
#define R12EXT_BIT28 (1U << 28)
#define R12EXT_BIT29 (1U << 29)
#define R12EXT_BIT30 (1U << 30)
#define R12EXT_BIT31 (1U << 31)
/* --- R13 Define --- */
#define R13_SRCCLKENI0 (1U << 0)
#define R13_SRCCLKENI1 (1U << 1)
#define R13_MD_SRCCLKENA_0 (1U << 2)
#define R13_MD_APSRC_REQ_0 (1U << 3)
#define R13_CONN_DDR_EN (1U << 4)
#define R13_MD_SRCCLKENA_1 (1U << 5)
#define R13_SSPM_SRCCLKENA (1U << 6)
#define R13_SSPM_APSRC_REQ (1U << 7)
#define R13_MD1_STATE (1U << 8)
#define R13_BIT9 (1U << 9)
#define R13_MM_STATE (1U << 10)
#define R13_SSPM_STATE (1U << 11)
#define R13_MD_DDR_EN_0 (1U << 12)
#define R13_CONN_STATE (1U << 13)
#define R13_CONN_SRCCLKENA (1U << 14)
#define R13_CONN_APSRC_REQ (1U << 15)
#define R13_SC_DDR_PST_ACK_ALL (1U << 16)
#define R13_SC_DDR_PST_ABORT_ACK_ALL (1U << 17)
#define R13_SCP_STATE (1U << 18)
#define R13_CSYSPWRUPREQ (1U << 19)
#define R13_PWRAP_SLEEP_ACK (1U << 20)
#define R13_SC_EMI_CLK_OFF_ACK_ALL (1U << 21)
#define R13_AUDIO_DSP_STATE (1U << 22)
#define R13_SC_DMDRAMCSHU_ACK_ALL (1U << 23)
#define R13_CONN_SRCCLKENB (1U << 24)
#define R13_SC_DR_SRAM_LOAD_ACK_ALL (1U << 25)
#define R13_SUBSYS_IDLE_SIGNALS0 (1U << 26)
#define R13_DVFS_STATE (1U << 27)
#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL (1U << 28)
#define R13_SC_DR_SRAM_RESTORE_ACK_ALL (1U << 29)
#define R13_MD_VRF18_REQ_0 (1U << 30)
#define R13_DDR_EN_STATE (1U << 31)
#endif /* PCM_DEF_H */
plat/mediatek/mt8192/drivers/spm/sleep_def.h 0 → 100644
View file @ 258f6a2d
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SLEEP_DEF_H
#define SLEEP_DEF_H
/*
* Auto generated by DE, please DO NOT modify this file directly.
*/
/* --- SPM Flag Define --- */
#define SPM_FLAG_DISABLE_CPU_PDN (1U << 0)
#define SPM_FLAG_DISABLE_INFRA_PDN (1U << 1)
#define SPM_FLAG_DISABLE_DDRPHY_PDN (1U << 2)
#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3)
#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4)
#define SPM_FLAG_DISABLE_COMMON_SCENARIO (1U << 5)
#define SPM_FLAG_DISABLE_BUS_CLK_OFF (1U << 6)
#define SPM_FLAG_DISABLE_ARMPLL_OFF (1U << 7)
#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH (1U << 8)
#define SPM_FLAG_ENABLE_LVTS_WORKAROUND (1U << 9)
#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10)
#define SPM_FLAG_RESERVED_BIT11 (1U << 11)
#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP (1U << 12)
#define SPM_FLAG_USE_SRCCLKENO2 (1U << 13)
#define SPM_FLAG_ENABLE_6315_CTRL (1U << 14)
#define SPM_FLAG_ENABLE_TIA_WORKAROUND (1U << 15)
#define SPM_FLAG_DISABLE_SYSRAM_SLEEP (1U << 16)
#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP (1U << 17)
#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP (1U << 18)
#define SPM_FLAG_ENABLE_MD_MUMTAS (1U << 19)
#define SPM_FLAG_ENABLE_VOLTAGE_BIN (1U << 20)
#define SPM_FLAG_RESERVED_BIT21 (1U << 21)
#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22)
#define SPM_FLAG_DISABLE_SRAM_EVENT (1U << 23)
#define SPM_FLAG_RESERVED_BIT24 (1U << 24)
#define SPM_FLAG_RESERVED_BIT25 (1U << 25)
#define SPM_FLAG_RESERVED_BIT26 (1U << 26)
#define SPM_FLAG_VTCXO_STATE (1U << 27)
#define SPM_FLAG_INFRA_STATE (1U << 28)
#define SPM_FLAG_APSRC_STATE (1U << 29)
#define SPM_FLAG_VRF18_STATE (1U << 30)
#define SPM_FLAG_DDREN_STATE (1U << 31)
/* --- SPM Flag1 Define --- */
#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M (1U << 0)
#define SPM_FLAG1_DISABLE_SYSPLL_OFF (1U << 1)
#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 2)
#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 3)
#define SPM_FLAG1_FW_SET_ULPOSC_ON (1U << 4)
#define SPM_FLAG1_RESERVED_BIT5 (1U << 5)
#define SPM_FLAG1_ENABLE_REKICK (1U << 6)
#define SPM_FLAG1_DISABLE_MD26M_CK_OFF (1U << 7)
#define SPM_FLAG1_RESERVED_BIT8 (1U << 8)
#define SPM_FLAG1_RESERVED_BIT9 (1U << 9)
#define SPM_FLAG1_DISABLE_SRCLKEN_LOW (1U << 10)
#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH (1U << 11)
#define SPM_FLAG1_RESERVED_BIT12 (1U << 12)
#define SPM_FLAG1_RESERVED_BIT13 (1U << 13)
#define SPM_FLAG1_RESERVED_BIT14 (1U << 14)
#define SPM_FLAG1_RESERVED_BIT15 (1U << 15)
#define SPM_FLAG1_RESERVED_BIT16 (1U << 16)
#define SPM_FLAG1_RESERVED_BIT17 (1U << 17)
#define SPM_FLAG1_RESERVED_BIT18 (1U << 18)
#define SPM_FLAG1_RESERVED_BIT19 (1U << 19)
#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP (1U << 20)
#define SPM_FLAG1_RESERVED_BIT21 (1U << 21)
#define SPM_FLAG1_ENABLE_VS1_VOTER (1U << 22)
#define SPM_FLAG1_ENABLE_VS2_VOTER (1U << 23)
#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL (1U << 24)
#define SPM_FLAG1_RESERVED_BIT25 (1U << 25)
#define SPM_FLAG1_RESERVED_BIT26 (1U << 26)
#define SPM_FLAG1_RESERVED_BIT27 (1U << 27)
#define SPM_FLAG1_RESERVED_BIT28 (1U << 28)
#define SPM_FLAG1_RESERVED_BIT29 (1U << 29)
#define SPM_FLAG1_RESERVED_BIT30 (1U << 30)
#define SPM_FLAG1_DISABLE_CPUEB_OFF (1U << 31)
/* --- SPM DEBUG Define --- */
#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0)
#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1)
#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2)
#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3)
#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4)
#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5)
#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6)
#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7)
#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8)
#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9)
#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC (1U << 10)
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE (1U << 11)
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE (1U << 12)
#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN (1U << 13)
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE (1U << 14)
#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP (1U << 15)
#define SPM_DBG_DEBUG_IDX_SYSRAM_ON (1U << 16)
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP (1U << 17)
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON (1U << 18)
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 19)
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON (1U << 20)
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP (1U << 21)
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON (1U << 22)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V (1U << 23)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V (1U << 24)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V (1U << 25)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V (1U << 26)
#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW (1U << 27)
#define SPM_DBG_DEBUG_IDX_VTCXO_STATE (1U << 28)
#define SPM_DBG_DEBUG_IDX_INFRA_STATE (1U << 29)
#define SPM_DBG_DEBUG_IDX_VRR18_STATE (1U << 30)
#define SPM_DBG_DEBUG_IDX_APSRC_STATE (1U << 31)
/* --- SPM DEBUG1 Define --- */
#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP (1U << 0)
#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START (1U << 1)
#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF (1U << 2)
#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON (1U << 3)
#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS (1U << 4)
#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF (1U << 5)
#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON (1U << 6)
#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT (1U << 7)
#define SPM_DBG1_RESERVED_BIT8 (1U << 8)
#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF (1U << 9)
#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON (1U << 10)
#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC (1U << 11)
#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M (1U << 12)
#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K (1U << 13)
#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M (1U << 14)
#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF (1U << 15)
#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON (1U << 16)
#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW (1U << 17)
#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH (1U << 18)
#define SPM_DBG1_RESERVED_BIT19 (1U << 19)
#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON (1U << 20)
#define SPM_DBG1_DEBUG_IDX_6315_LOW (1U << 21)
#define SPM_DBG1_DEBUG_IDX_6315_HIGH (1U << 22)
#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT (1U << 23)
#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT (1U << 24)
#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT (1U << 25)
#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT (1U << 26)
#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT (1U << 27)
#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT (1U << 28)
#define SPM_DBG1_RESERVED_BIT29 (1U << 29)
#define SPM_DBG1_RESERVED_BIT30 (1U << 30)
#define SPM_DBG1_DEBUG_DISABLE_CPUEB_OFF (1U << 31)
/* Macro and Inline */
#define is_cpu_pdn(flags) (((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U)
#define is_infra_pdn(flags) (((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U)
#define is_ddrphy_pdn(flags) (((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U)
#endif /* SLEEP_DEF_H */
plat/mediatek/mt8192/include/plat_mtk_lpm.h
View file @ 258f6a2d
......@@ -10,7 +10,7 @@
#include <lib/psci/psci.h>
#include <lib/utils_def.h>
#define MT_IRQ_REMAIN_MAX U(8)
#define MT_IRQ_REMAIN_MAX U(32)
#define MT_IRQ_REMAIN_CAT_LOG BIT(31)
struct mt_irqremain {
......
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