diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index fa5ba6263f21dd3ae42e2b3cece3d1379f3b9c11..9a9113ec23ce9a50aa01e0f6c264cf911904b0b2 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -369,6 +369,52 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 		/* Resume SE, RNG1 and PKA1 */
 		tegra_se_resume();
 
+		/*
+		 * Program XUSB STREAMIDs
+		 * ======================
+		 * T19x XUSB has support for XUSB virtualization. It will
+		 * have one physical function (PF) and four Virtual functions
+		 * (VF)
+		 *
+		 * There were below two SIDs for XUSB until T186.
+		 * 1) #define TEGRA_SID_XUSB_HOST    0x1bU
+		 * 2) #define TEGRA_SID_XUSB_DEV    0x1cU
+		 *
+		 * We have below four new SIDs added for VF(s)
+		 * 3) #define TEGRA_SID_XUSB_VF0    0x5dU
+		 * 4) #define TEGRA_SID_XUSB_VF1    0x5eU
+		 * 5) #define TEGRA_SID_XUSB_VF2    0x5fU
+		 * 6) #define TEGRA_SID_XUSB_VF3    0x60U
+		 *
+		 * When virtualization is enabled then we have to disable SID
+		 * override and program above SIDs in below newly added SID
+		 * registers in XUSB PADCTL MMIO space. These registers are
+		 * TZ protected and so need to be done in ATF.
+		 *
+		 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
+		 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0  (0x139cU)
+		 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
+		 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
+		 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
+		 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
+		 *
+		 * This change disables SID override and programs XUSB SIDs
+		 * in above registers to support both virtualization and
+		 * non-virtualization platforms
+		 */
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
+		mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+			XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
+
 		/*
 		 * Reset power state info for the last core doing SC7
 		 * entry and exit, we set deepest power state as CC7
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index 8c5710557dee41cbd7cbfa4a492480102f6819d0..7dde9dde5b77f7b00aec76ce88aa6f5194b04d57 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -197,12 +197,13 @@ void plat_enable_console(int32_t id)
  ******************************************************************************/
 void plat_early_platform_setup(void)
 {
-
 	/* sanity check MCE firmware compatibility */
 	mce_verify_firmware_version();
 
-	/* Program XUSB STREAMIDs
-	 * Xavier XUSB has support for XUSB virtualization. It will have one
+	/*
+	 * Program XUSB STREAMIDs
+	 * ======================
+	 * T19x XUSB has support for XUSB virtualization. It will have one
 	 * physical function (PF) and four Virtual function (VF)
 	 *
 	 * There were below two SIDs for XUSB until T186.
@@ -227,14 +228,8 @@ void plat_early_platform_setup(void)
 	 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
 	 *
 	 * This change disables SID override and programs XUSB SIDs in
-	 * above registers to support both virtualization and non-virtualization
-	 *
-	 * Known Limitations:
-	 * If xusb interface disables SMMU in XUSB DT in non-virtualization
-	 * setup then there will be SMMU fault. We need to use WAR at
-	 * https:\\git-master.nvidia.com/r/1529227/ to the issue.
-	 *
-	 * More details can be found in the bug 1971161
+	 * above registers to support both virtualization and
+	 * non-virtualization platforms
 	 */
 	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
 		XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);