From 26cf08494b3db526c4b887d27c797da49efb7505 Mon Sep 17 00:00:00 2001
From: Varun Wadekar <vwadekar@nvidia.com>
Date: Tue, 23 Jan 2018 14:38:51 -0800
Subject: [PATCH] Tegra: organize memory/mmio apertures to decrease memmap
latency
This patch organizes the memory and mmio maps linearly, to make the
mmap_add_region process faster. The microsecond timer has been moved
to individual platforms instead of making it a common step, as it
further speeds up the memory map creation process.
Change-Id: I6fdaee392f7ac5d99daa182380ca9116a001f5d6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
---
plat/nvidia/tegra/common/tegra_bl31_setup.c | 34 +++++++++------------
plat/nvidia/tegra/soc/t186/plat_setup.c | 2 ++
2 files changed, 16 insertions(+), 20 deletions(-)
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 908e4f2dd..0d0bc7406 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -404,6 +404,14 @@ void bl31_plat_arch_setup(void)
*/
boot_profiler_add_record("[TF] arch setup entry");
+ /* add MMIO space */
+ plat_mmio_map = plat_get_mmio_map();
+ if (plat_mmio_map != NULL) {
+ mmap_add(plat_mmio_map);
+ } else {
+ WARN("MMIO map not available\n");
+ }
+
/* add memory regions */
mmap_add_region(rw_start, rw_start,
rw_size,
@@ -415,14 +423,6 @@ void bl31_plat_arch_setup(void)
code_size,
MT_CODE | MT_SECURE);
- /* map TZDRAM used by BL31 as coherent memory */
- if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
- mmap_add_region(params_from_bl2->tzdram_base,
- params_from_bl2->tzdram_base,
- BL31_SIZE,
- MT_DEVICE | MT_RW | MT_SECURE);
- }
-
#if USE_COHERENT_MEM
coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
@@ -432,18 +432,12 @@ void bl31_plat_arch_setup(void)
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
#endif
- /* map on-chip free running uS timer */
- mmap_add_region(page_align(TEGRA_TMRUS_BASE, 0),
- page_align(TEGRA_TMRUS_BASE, 0),
- TEGRA_TMRUS_SIZE,
- (uint8_t)MT_DEVICE | (uint8_t)MT_RO | (uint8_t)MT_SECURE);
-
- /* add MMIO space */
- plat_mmio_map = plat_get_mmio_map();
- if (plat_mmio_map != NULL) {
- mmap_add(plat_mmio_map);
- } else {
- WARN("MMIO map not available\n");
+ /* map TZDRAM used by BL31 as coherent memory */
+ if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
+ mmap_add_region(params_from_bl2->tzdram_base,
+ params_from_bl2->tzdram_base,
+ BL31_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE);
}
/* set up translation tables */
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index fd109e563..c56f71ceb 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -91,6 +91,8 @@ static const mmap_region_t tegra_mmap[] = {
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */
+ MT_DEVICE | MT_RO | MT_SECURE),
MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
--
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