diff --git a/include/lib/smccc.h b/include/lib/smccc.h index 470317dd003ec0395ab86ca79afec770cc522ba7..deaeb1d1d18950f0b101d2083d059dd70b7f7fb7 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -50,6 +50,23 @@ #define GET_SMC_OEN(id) (((id) >> FUNCID_OEN_SHIFT) & \ FUNCID_OEN_MASK) +/******************************************************************************* + * SMCCC_ARCH_SOC_ID SoC version & revision bit definition + ******************************************************************************/ +#define SOC_ID_JEP_106_BANK_IDX_MASK GENMASK_32(30, 24) +#define SOC_ID_JEP_106_BANK_IDX_SHIFT U(24) +#define SOC_ID_JEP_106_ID_CODE_MASK GENMASK_32(23, 16) +#define SOC_ID_JEP_106_ID_CODE_SHIFT U(16) +#define SOC_ID_IMPL_DEF_MASK GENMASK_32(15, 0) +#define SOC_ID_IMPL_DEF_SHIFT U(0) +#define SOC_ID_SET_JEP_106(bkid, mfid) ((((bkid) << SOC_ID_JEP_106_BANK_IDX_SHIFT) & \ + SOC_ID_JEP_106_BANK_IDX_MASK) | \ + (((mfid) << SOC_ID_JEP_106_ID_CODE_SHIFT) & \ + SOC_ID_JEP_106_ID_CODE_MASK)) + +#define SOC_ID_REV_MASK GENMASK_32(30, 0) +#define SOC_ID_REV_SHIFT U(0) + /******************************************************************************* * Owning entity number definitions inside the function id as per the SMC * calling convention diff --git a/include/plat/arm/common/smccc_def.h b/include/plat/arm/common/smccc_def.h index 6e698e5d2c898d148f16b029ee170ec3eaa825d3..0f4e57386f46b23eb1fa2c6242b255be4c929dcb 100644 --- a/include/plat/arm/common/smccc_def.h +++ b/include/plat/arm/common/smccc_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,5 @@ /* Defines used to retrieve ARM SOC revision */ #define ARM_SOC_CONTINUATION_CODE U(0x4) #define ARM_SOC_IDENTIFICATION_CODE U(0x3B) -#define ARM_SOC_CONTINUATION_SHIFT U(24) -#define ARM_SOC_IDENTIFICATION_SHIFT U(16) #endif /* SMCCC_DEF_H */ diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index 52686facad702d9e914c31e83ec09f5512850715..fe0903b2a2ee85099bf7d4a1f0d23f9494b00d98 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -483,9 +483,9 @@ int32_t plat_is_smccc_feature_available(u_register_t fid) int32_t plat_get_soc_version(void) { return (int32_t) - ((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT) - | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT) - | FVP_SOC_ID); + (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE, + ARM_SOC_IDENTIFICATION_CODE) | + (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK)); } /* Get SOC revision */ @@ -494,6 +494,6 @@ int32_t plat_get_soc_revision(void) unsigned int sys_id; sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); - return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) & - V2M_SYS_ID_REV_MASK); + return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & + V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK); } diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c index cb183d53942c91c40ea314d21575b18f9d6af020..038f604de4411c0df999f213738fdddb161c0aa4 100644 --- a/plat/arm/board/juno/juno_common.c +++ b/plat/arm/board/juno/juno_common.c @@ -118,9 +118,9 @@ int32_t plat_is_smccc_feature_available(u_register_t fid) int32_t plat_get_soc_version(void) { return (int32_t) - ((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT) - | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT) - | JUNO_SOC_ID); + (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE, + ARM_SOC_IDENTIFICATION_CODE) | + (JUNO_SOC_ID & SOC_ID_IMPL_DEF_MASK)); } /* Get SOC revision */ @@ -129,6 +129,6 @@ int32_t plat_get_soc_revision(void) unsigned int sys_id; sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); - return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) & - V2M_SYS_ID_REV_MASK); + return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & + V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK); } diff --git a/plat/mediatek/common/mtk_plat_common.c b/plat/mediatek/common/mtk_plat_common.c index f57e4357d43c378ecb64515aeae88c1b74b16c96..142b5c999429bce4f22a9f17d55f5d0f5a255440 100644 --- a/plat/mediatek/common/mtk_plat_common.c +++ b/plat/mediatek/common/mtk_plat_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -139,9 +139,9 @@ int32_t plat_is_smccc_feature_available(u_register_t fid) int32_t plat_get_soc_version(void) { - uint32_t manfid = (JEDEC_MTK_BKID << 24U) | (JEDEC_MTK_MFID << 16U); + uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_MTK_BKID, JEDEC_MTK_MFID); - return (int32_t)(manfid | (SOC_CHIP_ID & 0xFFFFU)); + return (int32_t)(manfid | (SOC_CHIP_ID & SOC_ID_IMPL_DEF_MASK)); } int32_t plat_get_soc_revision(void) diff --git a/plat/nvidia/tegra/common/tegra_platform.c b/plat/nvidia/tegra/common/tegra_platform.c index d45d9886f086249718f01bb96f69bf3da982c225..3894b747601b4c4bc66e830b0b45618b3dfd6340 100644 --- a/plat/nvidia/tegra/common/tegra_platform.c +++ b/plat/nvidia/tegra/common/tegra_platform.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -280,9 +280,9 @@ bool tegra_platform_is_virt_dev_kit(void) int32_t plat_get_soc_version(void) { uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK); - uint32_t manfid = (JEDEC_NVIDIA_BKID << 24) | (JEDEC_NVIDIA_MFID << 16); + uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_NVIDIA_BKID, JEDEC_NVIDIA_MFID); - return (int32_t)(manfid | (chip_id & 0xFFFF)); + return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK)); } /* @@ -293,7 +293,8 @@ int32_t plat_get_soc_version(void) */ int32_t plat_get_soc_revision(void) { - return (int32_t)((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor()); + return (int32_t)(((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor()) & + SOC_ID_REV_MASK); } /***************************************************************************** diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index feeb4a790dee7848cbf6139071d7c572ef7d77b2..42d3487024dd6a42a0b5aa238415707a84e90e09 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,9 @@ #include +#define JEDEC_ST_BKID U(0x0) +#define JEDEC_ST_MFID U(0x20) + /* Functions to save and get boot context address given by ROM code */ void stm32mp_save_boot_ctx_address(uintptr_t address); uintptr_t stm32mp_get_boot_ctx_address(void); @@ -64,6 +67,15 @@ uint32_t stm32_get_gpio_bank_offset(unsigned int bank); /* Return node offset for target GPIO bank ID @bank or a FDT error code */ int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank); +/* Get the chip revision */ +uint32_t stm32mp_get_chip_version(void); +/* Get the chip device ID */ +uint32_t stm32mp_get_chip_dev_id(void); + +/* Get SOC name */ +#define STM32_SOC_NAME_SIZE 20 +void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]); + /* Print CPU information */ void stm32mp_print_cpuinfo(void); diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c index 89d80783860cf033e0224d636bcb865202edc3f4..d3de1e14f3ff989ad39a5db85c3a22e46bdf1084 100644 --- a/plat/st/common/stm32mp_common.c +++ b/plat/st/common/stm32mp_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,8 +12,10 @@ #include #include #include +#include #include #include +#include uintptr_t plat_get_ns_image_entrypoint(void) { @@ -111,3 +113,36 @@ int stm32mp_unmap_ddr(void) return mmap_remove_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_MAX_SIZE); } + +/***************************************************************************** + * plat_is_smccc_feature_available() - This function checks whether SMCCC + * feature is availabile for platform. + * @fid: SMCCC function id + * + * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and + * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. + *****************************************************************************/ +int32_t plat_is_smccc_feature_available(u_register_t fid) +{ + switch (fid) { + case SMCCC_ARCH_SOC_ID: + return SMC_ARCH_CALL_SUCCESS; + default: + return SMC_ARCH_CALL_NOT_SUPPORTED; + } +} + +/* Get SOC version */ +int32_t plat_get_soc_version(void) +{ + uint32_t chip_id = stm32mp_get_chip_dev_id(); + uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID); + + return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK)); +} + +/* Get SOC revision */ +int32_t plat_get_soc_revision(void) +{ + return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK); +} diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 9e5bfdcb5d8912605e973af54360241110df3249..155d63db2cf620f3795fe88fcf6869862213a637 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -31,6 +31,8 @@ /******************************************************************************* * CHIP ID ******************************************************************************/ +#define STM32MP1_CHIP_ID U(0x500) + #define STM32MP157C_PART_NB U(0x05000000) #define STM32MP157A_PART_NB U(0x05000001) #define STM32MP153C_PART_NB U(0x05000024) diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index bc77ee33420df06c163963fb844d55557dc5700f..1af0075f249f7367d3239d6b705e82afb8893a76 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -153,63 +153,70 @@ int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) } } -static int get_part_number(uint32_t *part_nb) +uint32_t stm32mp_get_chip_version(void) { - uint32_t part_number; - uint32_t dev_id; + uint32_t version = 0U; + + if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { + INFO("Cannot get CPU version, debug disabled\n"); + return 0U; + } + + return version; +} - assert(part_nb != NULL); +uint32_t stm32mp_get_chip_dev_id(void) +{ + uint32_t dev_id; if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { - return -1; + INFO("Use default chip ID, debug disabled\n"); + dev_id = STM32MP1_CHIP_ID; + } + + return dev_id; +} + +static uint32_t get_part_number(void) +{ + static uint32_t part_number; + + if (part_number != 0U) { + return part_number; } if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) { - ERROR("BSEC: PART_NUMBER_OTP Error\n"); - return -1; + panic(); } part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> PART_NUMBER_OTP_PART_SHIFT; - *part_nb = part_number | (dev_id << 16); + part_number |= stm32mp_get_chip_dev_id() << 16; - return 0; + return part_number; } -static int get_cpu_package(uint32_t *cpu_package) +static uint32_t get_cpu_package(void) { uint32_t package; - assert(cpu_package != NULL); - if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { - ERROR("BSEC: PACKAGE_OTP Error\n"); - return -1; + panic(); } - *cpu_package = (package & PACKAGE_OTP_PKG_MASK) >> + package = (package & PACKAGE_OTP_PKG_MASK) >> PACKAGE_OTP_PKG_SHIFT; - return 0; + return package; } -void stm32mp_print_cpuinfo(void) +void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) { - const char *cpu_s, *cpu_r, *pkg; - uint32_t part_number; - uint32_t cpu_package; - uint32_t chip_dev_id; - int ret; + char *cpu_s, *cpu_r, *pkg; /* MPUs Part Numbers */ - ret = get_part_number(&part_number); - if (ret < 0) { - WARN("Cannot get part number\n"); - return; - } - - switch (part_number) { + switch (get_part_number()) { case STM32MP157C_PART_NB: cpu_s = "157C"; break; @@ -252,13 +259,7 @@ void stm32mp_print_cpuinfo(void) } /* Package */ - ret = get_cpu_package(&cpu_package); - if (ret < 0) { - WARN("Cannot get CPU package\n"); - return; - } - - switch (cpu_package) { + switch (get_cpu_package()) { case PKG_AA_LFBGA448: pkg = "AA"; break; @@ -277,13 +278,7 @@ void stm32mp_print_cpuinfo(void) } /* REVISION */ - ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id); - if (ret < 0) { - WARN("Cannot get CPU version\n"); - return; - } - - switch (chip_dev_id) { + switch (stm32mp_get_chip_version()) { case STM32MP1_REV_B: cpu_r = "B"; break; @@ -295,7 +290,16 @@ void stm32mp_print_cpuinfo(void) break; } - NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r); + snprintf(name, STM32_SOC_NAME_SIZE, + "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); +} + +void stm32mp_print_cpuinfo(void) +{ + char name[STM32_SOC_NAME_SIZE]; + + stm32mp_get_soc_name(name); + NOTICE("CPU: %s\n", name); } void stm32mp_print_boardinfo(void) @@ -349,20 +353,12 @@ void stm32mp_print_boardinfo(void) /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ bool stm32mp_is_single_core(void) { - uint32_t part_number; - - if (get_part_number(&part_number) < 0) { - ERROR("Invalid part number, assume single core chip"); - return true; - } - - switch (part_number) { + switch (get_part_number()) { case STM32MP151A_PART_NB: case STM32MP151C_PART_NB: case STM32MP151D_PART_NB: case STM32MP151F_PART_NB: return true; - default: return false; }