Commit 2c3b76ce authored by Louis Mayencourt's avatar Louis Mayencourt
Browse files

DSU: Small fix and reformat on errata framework



Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
parent cba71b70
...@@ -10,23 +10,29 @@ ...@@ -10,23 +10,29 @@
#include <lib/utils_def.h> #include <lib/utils_def.h>
/******************************************************************** /********************************************************************
* DSU control registers definitions * * DSU Cluster Configuration registers definitions
********************************************************************/ ********************************************************************/
#define CLUSTERCFR_EL1 S3_0_C15_C3_0 #define CLUSTERCFR_EL1 S3_0_C15_C3_0
#define CLUSTERIDR_EL1 S3_0_C15_C3_1
#define CLUSTERACTLR_EL1 S3_0_C15_C3_3 #define CLUSTERCFR_ACP_SHIFT U(11)
/******************************************************************** /********************************************************************
* DSU control registers bit fields * * DSU Cluster Main Revision ID registers definitions
********************************************************************/ ********************************************************************/
#define CLUSTERIDR_EL1 S3_0_C15_C3_1
#define CLUSTERIDR_REV_SHIFT U(0) #define CLUSTERIDR_REV_SHIFT U(0)
#define CLUSTERIDR_REV_BITS U(4) #define CLUSTERIDR_REV_BITS U(4)
#define CLUSTERIDR_VAR_SHIFT U(4) #define CLUSTERIDR_VAR_SHIFT U(4)
#define CLUSTERIDR_VAR_BITS U(4) #define CLUSTERIDR_VAR_BITS U(4)
#define CLUSTERCFR_ACP_SHIFT U(11)
/******************************************************************** /********************************************************************
* Masks applied for DSU errata workarounds * * DSU Cluster Auxiliary Control registers definitions
********************************************************************/
#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
/********************************************************************
* Masks applied for DSU errata workarounds
********************************************************************/ ********************************************************************/
#define DSU_ERRATA_936184_MASK (U(0x3) << 15) #define DSU_ERRATA_936184_MASK (U(0x3) << 15)
......
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
#include <dsu_def.h> #include <dsu_def.h>
#include <lib/cpus/errata_report.h> #include <lib/cpus/errata_report.h>
/* ----------------------------------------------------------------------- /* -----------------------------------------------------------------------
* DSU erratum 936184 check function * DSU erratum 936184 check function
* Checks the DSU variant, revision and configuration to determine if * Checks the DSU variant, revision and configuration to determine if
* the erratum applies. Erratum applies if ACP interface is present * the erratum applies. Erratum applies if ACP interface is present
...@@ -41,14 +41,14 @@ func check_errata_dsu_936184 ...@@ -41,14 +41,14 @@ func check_errata_dsu_936184
/* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */
ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\ ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\
#(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS)
mov x1, #(0x2 << CLUSTERIDR_REV_BITS) mov x1, #(0x2 << CLUSTERIDR_VAR_SHIFT)
cmp x0, x1 cmp x0, x1
csel x0, x2, x3, hs csel x0, x2, x3, hs
1: 1:
ret ret
endfunc check_errata_dsu_936184 endfunc check_errata_dsu_936184
/* -------------------------------------------------- /* --------------------------------------------------
* Errata Workaround for DSU erratum #936184. * Errata Workaround for DSU erratum #936184.
* *
* Can clobber only: x0-x17 * Can clobber only: x0-x17
......
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