diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 300db81358dba19446b8ef73bb82da4e76d92ebf..9b6e18e9d0bf1e831d198869ebcc60e6ba452e43 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -27,20 +27,6 @@
 #define PLAT_MAX_RET_STATE		1
 #define PLAT_MAX_OFF_STATE		8
 
-/*******************************************************************************
- * Implementation defined ACTLR_EL3 bit definitions
- ******************************************************************************/
-#define ACTLR_EL3_L2ACTLR_BIT		(1 << 6)
-#define ACTLR_EL3_L2ECTLR_BIT		(1 << 5)
-#define ACTLR_EL3_L2CTLR_BIT		(1 << 4)
-#define ACTLR_EL3_CPUECTLR_BIT		(1 << 1)
-#define ACTLR_EL3_CPUACTLR_BIT		(1 << 0)
-#define ACTLR_EL3_ENABLE_ALL_ACCESS	(ACTLR_EL3_L2ACTLR_BIT | \
-					 ACTLR_EL3_L2ECTLR_BIT | \
-					 ACTLR_EL3_L2CTLR_BIT | \
-					 ACTLR_EL3_CPUECTLR_BIT | \
-					 ACTLR_EL3_CPUACTLR_BIT)
-
 /*******************************************************************************
  * Secure IRQ definitions
  ******************************************************************************/
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index 12dd6cb09fe31cf2a70c846c025768b3f467a01b..c797a0cf7e8da8a33a92ca87c683d29866f3ab6b 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -13,6 +13,7 @@
 #include <mce_private.h>
 #include <platform_def.h>
 #include <t194_nvg.h>
+#include <tegra_private.h>
 
 extern void nvg_set_request_data(uint64_t req, uint64_t data);
 extern void nvg_set_request(uint64_t req);
@@ -342,6 +343,7 @@ int32_t nvg_roc_clean_cache_trbits(void)
 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
 {
 	int32_t ret = 0;
+	uint64_t val = 0ULL;
 
 	/* check for allowed power state */
 	if ((state != (uint32_t)TEGRA_NVG_CORE_C0) &&
@@ -356,7 +358,8 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
 		nvg_set_wake_time(wake_time);
 
 		/* set the core cstate */
-		write_actlr_el1(state);
+		val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
+		write_actlr_el1(val | (uint64_t)state);
 	}
 
 	return ret;