From 2cd2e399f60b11a3bf1cc6e7988425d0d714a975 Mon Sep 17 00:00:00 2001
From: Steven Kao <skao@nvidia.com>
Date: Thu, 22 Jun 2017 12:54:06 +0800
Subject: [PATCH] Tegra194: read-modify-write ACTLR_ELx registers
This patch changes direct writes to ACTLR_ELx registers to use
read-modify-write instead.
Change-Id: I536dce75c01356ce054dd2edee80875e56164439
Signed-off-by: Steven Kao <skao@nvidia.com>
---
plat/nvidia/tegra/include/t194/tegra_def.h | 14 --------------
plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 5 ++++-
2 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 300db8135..9b6e18e9d 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -27,20 +27,6 @@
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE 8
-/*******************************************************************************
- * Implementation defined ACTLR_EL3 bit definitions
- ******************************************************************************/
-#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
-#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
-#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
-#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
-#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
-#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
- ACTLR_EL3_L2ECTLR_BIT | \
- ACTLR_EL3_L2CTLR_BIT | \
- ACTLR_EL3_CPUECTLR_BIT | \
- ACTLR_EL3_CPUACTLR_BIT)
-
/*******************************************************************************
* Secure IRQ definitions
******************************************************************************/
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index 12dd6cb09..c797a0cf7 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -13,6 +13,7 @@
#include <mce_private.h>
#include <platform_def.h>
#include <t194_nvg.h>
+#include <tegra_private.h>
extern void nvg_set_request_data(uint64_t req, uint64_t data);
extern void nvg_set_request(uint64_t req);
@@ -342,6 +343,7 @@ int32_t nvg_roc_clean_cache_trbits(void)
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
{
int32_t ret = 0;
+ uint64_t val = 0ULL;
/* check for allowed power state */
if ((state != (uint32_t)TEGRA_NVG_CORE_C0) &&
@@ -356,7 +358,8 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
nvg_set_wake_time(wake_time);
/* set the core cstate */
- write_actlr_el1(state);
+ val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
+ write_actlr_el1(val | (uint64_t)state);
}
return ret;
--
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