Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing

On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the flow controller instead, for
power state management. But the flow controller can route the FIQ to the GICD,
as a PPI, which can then get routed to the target CPU.

This patch adds routines to enable/disable routing the legacy FIQ used by
the watchdog timers, to the GICD.

Change-Id: Idd07c88c8d730b5f0e93e3a6e4fdc59bdcb2161b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c

@@ -217,3 +217,25 @@ void tegra_fc_reset_bpmp(void)
 	/* Un-halt BPMP */
 	tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, 0);
 }
+
+/*******************************************************************************
+ * Route legacy FIQ to the GICD
+ ******************************************************************************/
+void tegra_fc_enable_fiq_to_ccplex_routing(void)
+{
+	uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL);
+
+	/* set the bit to pass FIQs to the GICD */
+	tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val | FLOWCTRL_FIQ2CCPLEX_ENABLE);
+}
+
+/*******************************************************************************
+ * Disable routing legacy FIQ to the GICD
+ ******************************************************************************/
+void tegra_fc_disable_fiq_to_ccplex_routing(void)
+{
+	uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL);
+
+	/* clear the bit to pass FIQs to the GICD */
+	tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val & ~FLOWCTRL_FIQ2CCPLEX_ENABLE);
+}

plat/nvidia/tegra/include/drivers/flowctrl.h

 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,6 +29,8 @@
 #define  FLOWCTRL_CSR_ENABLE		(1U << 0)
 #define FLOWCTRL_HALT_CPU1_EVENTS	0x14U
 #define FLOWCTRL_CPU1_CSR		0x18U
+#define FLOW_CTLR_FLOW_DBG_QUAL		0x50U
+#define  FLOWCTRL_FIQ2CCPLEX_ENABLE	(1U << 28)
 #define FLOWCTRL_CC4_CORE0_CTRL		0x6cU
 #define FLOWCTRL_WAIT_WFI_BITMAP	0x100U
 #define FLOWCTRL_L2_FLUSH_CONTROL	0x94U
@@ -53,10 +55,12 @@ static inline void tegra_fc_write_32(uint32_t off, uint32_t val)
 void tegra_fc_cluster_idle(uint32_t midr);
 void tegra_fc_cpu_powerdn(uint32_t mpidr);
 void tegra_fc_cluster_powerdn(uint32_t midr);
-void tegra_fc_soc_powerdn(uint32_t midr);
 void tegra_fc_cpu_on(int cpu);
 void tegra_fc_cpu_off(int cpu);
+void tegra_fc_disable_fiq_to_ccplex_routing(void);
+void tegra_fc_enable_fiq_to_ccplex_routing(void);
 void tegra_fc_lock_active_cluster(void);
 void tegra_fc_reset_bpmp(void);
+void tegra_fc_soc_powerdn(uint32_t midr);
 
 #endif /* FLOWCTRL_H */