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Commit 2edf6482 authored by davidcunado-arm's avatar davidcunado-arm Committed by GitHub
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Merge pull request #906 from antonio-nino-diaz-arm/an/asserts-release 

Add `ENABLE_ASSERTIONS` build option
parents 85aa186b aa61368e
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Makefile
View file @ 2edf6482
...@@ -50,10 +50,14 @@ include ${MAKE_HELPERS_DIRECTORY}build_env.mk ...@@ -50,10 +50,14 @@ include ${MAKE_HELPERS_DIRECTORY}build_env.mk
# Default values for build configurations, and their dependencies # Default values for build configurations, and their dependencies
################################################################################ ################################################################################
ifdef ASM_ASSERTION
$(warning ASM_ASSERTION is removed, use ENABLE_ASSERTIONS instead.)
endif
include ${MAKE_HELPERS_DIRECTORY}defaults.mk include ${MAKE_HELPERS_DIRECTORY}defaults.mk
# ASM_ASSERTION enabled for DEBUG builds only # Assertions enabled for DEBUG builds by default
ASM_ASSERTION := ${DEBUG} ENABLE_ASSERTIONS := ${DEBUG}
ENABLE_PMF := ${ENABLE_RUNTIME_INSTRUMENTATION} ENABLE_PMF := ${ENABLE_RUNTIME_INSTRUMENTATION}
PLAT := ${DEFAULT_PLAT} PLAT := ${DEFAULT_PLAT}
...@@ -439,13 +443,13 @@ endif ...@@ -439,13 +443,13 @@ endif
# Build options checks # Build options checks
################################################################################ ################################################################################
$(eval $(call assert_boolean,ASM_ASSERTION))
$(eval $(call assert_boolean,COLD_BOOT_SINGLE_CPU)) $(eval $(call assert_boolean,COLD_BOOT_SINGLE_CPU))
$(eval $(call assert_boolean,CREATE_KEYS)) $(eval $(call assert_boolean,CREATE_KEYS))
$(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS)) $(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS))
$(eval $(call assert_boolean,CTX_INCLUDE_FPREGS)) $(eval $(call assert_boolean,CTX_INCLUDE_FPREGS))
$(eval $(call assert_boolean,DEBUG)) $(eval $(call assert_boolean,DEBUG))
$(eval $(call assert_boolean,DISABLE_PEDANTIC)) $(eval $(call assert_boolean,DISABLE_PEDANTIC))
$(eval $(call assert_boolean,ENABLE_ASSERTIONS))
$(eval $(call assert_boolean,ENABLE_PLAT_COMPAT)) $(eval $(call assert_boolean,ENABLE_PLAT_COMPAT))
$(eval $(call assert_boolean,ENABLE_PMF)) $(eval $(call assert_boolean,ENABLE_PMF))
$(eval $(call assert_boolean,ENABLE_PSCI_STAT)) $(eval $(call assert_boolean,ENABLE_PSCI_STAT))
...@@ -478,10 +482,10 @@ $(eval $(call add_define,ARM_CCI_PRODUCT_ID)) ...@@ -478,10 +482,10 @@ $(eval $(call add_define,ARM_CCI_PRODUCT_ID))
$(eval $(call add_define,ARM_ARCH_MAJOR)) $(eval $(call add_define,ARM_ARCH_MAJOR))
$(eval $(call add_define,ARM_ARCH_MINOR)) $(eval $(call add_define,ARM_ARCH_MINOR))
$(eval $(call add_define,ARM_GIC_ARCH)) $(eval $(call add_define,ARM_GIC_ARCH))
$(eval $(call add_define,ASM_ASSERTION))
$(eval $(call add_define,COLD_BOOT_SINGLE_CPU)) $(eval $(call add_define,COLD_BOOT_SINGLE_CPU))
$(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS)) $(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS))
$(eval $(call add_define,CTX_INCLUDE_FPREGS)) $(eval $(call add_define,CTX_INCLUDE_FPREGS))
$(eval $(call add_define,ENABLE_ASSERTIONS))
$(eval $(call add_define,ENABLE_PLAT_COMPAT)) $(eval $(call add_define,ENABLE_PLAT_COMPAT))
$(eval $(call add_define,ENABLE_PMF)) $(eval $(call add_define,ENABLE_PMF))
$(eval $(call add_define,ENABLE_PSCI_STAT)) $(eval $(call add_define,ENABLE_PSCI_STAT))
......
bl1/bl1_main.c
View file @ 2edf6482
...@@ -114,7 +114,7 @@ void bl1_main(void) ...@@ -114,7 +114,7 @@ void bl1_main(void)
print_errata_status(); print_errata_status();
#if DEBUG #if ENABLE_ASSERTIONS
u_register_t val; u_register_t val;
/* /*
* Ensure that MMU/Caches and coherency are turned on * Ensure that MMU/Caches and coherency are turned on
...@@ -141,7 +141,7 @@ void bl1_main(void) ...@@ -141,7 +141,7 @@ void bl1_main(void)
assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
else else
assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
#endif #endif /* ENABLE_ASSERTIONS */
/* Perform remaining generic architectural setup from EL3 */ /* Perform remaining generic architectural setup from EL3 */
bl1_arch_setup(); bl1_arch_setup();
......
common/aarch32/debug.S
View file @ 2edf6482
...@@ -90,7 +90,7 @@ func report_exception ...@@ -90,7 +90,7 @@ func report_exception
no_ret plat_panic_handler no_ret plat_panic_handler
endfunc report_exception endfunc report_exception
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
.section .rodata.assert_str, "aS" .section .rodata.assert_str, "aS"
assert_msg1: assert_msg1:
.asciz "ASSERT: File " .asciz "ASSERT: File "
...@@ -107,6 +107,11 @@ assert_msg2: ...@@ -107,6 +107,11 @@ assert_msg2:
* --------------------------------------------------------------------------- * ---------------------------------------------------------------------------
*/ */
func asm_assert func asm_assert
#if LOG_LEVEL >= LOG_LEVEL_INFO
/*
* Only print the output if LOG_LEVEL is higher or equal to
* LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
*/
/* Stash the parameters already in r0 and r1 */ /* Stash the parameters already in r0 and r1 */
mov r5, r0 mov r5, r0
mov r6, r1 mov r6, r1
...@@ -147,9 +152,10 @@ dec_print_loop: ...@@ -147,9 +152,10 @@ dec_print_loop:
bl plat_crash_console_flush bl plat_crash_console_flush
1: 1:
#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
no_ret plat_panic_handler no_ret plat_panic_handler
endfunc asm_assert endfunc asm_assert
#endif #endif /* ENABLE_ASSERTIONS */
/* /*
* This function prints a string from address in r4 * This function prints a string from address in r4
......
common/aarch64/debug.S
View file @ 2edf6482
...@@ -41,7 +41,7 @@ ...@@ -41,7 +41,7 @@
/* The offset to add to get ascii for numerals '0 - 9' */ /* The offset to add to get ascii for numerals '0 - 9' */
#define ASCII_OFFSET_NUM 0x30 #define ASCII_OFFSET_NUM 0x30
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
.section .rodata.assert_str, "aS" .section .rodata.assert_str, "aS"
assert_msg1: assert_msg1:
.asciz "ASSERT: File " .asciz "ASSERT: File "
...@@ -78,6 +78,11 @@ dec_print_loop: ...@@ -78,6 +78,11 @@ dec_print_loop:
* --------------------------------------------------------------------------- * ---------------------------------------------------------------------------
*/ */
func asm_assert func asm_assert
#if LOG_LEVEL >= LOG_LEVEL_INFO
/*
* Only print the output if LOG_LEVEL is higher or equal to
* LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
*/
mov x5, x0 mov x5, x0
mov x6, x1 mov x6, x1
/* Ensure the console is initialized */ /* Ensure the console is initialized */
...@@ -98,9 +103,10 @@ func asm_assert ...@@ -98,9 +103,10 @@ func asm_assert
asm_print_line_dec asm_print_line_dec
bl plat_crash_console_flush bl plat_crash_console_flush
_assert_loop: _assert_loop:
#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
no_ret plat_panic_handler no_ret plat_panic_handler
endfunc asm_assert endfunc asm_assert
#endif #endif /* ENABLE_ASSERTIONS */
/* /*
* This function prints a string from address in x4. * This function prints a string from address in x4.
......
docs/user-guide.md
View file @ 2edf6482
...@@ -203,11 +203,6 @@ performed. ...@@ -203,11 +203,6 @@ performed.
in MPIDR is set and access the bit-fields in MPIDR accordingly. Default in MPIDR is set and access the bit-fields in MPIDR accordingly. Default
value of this flag is 0. value of this flag is 0.
* `ASM_ASSERTION`: This flag determines whether the assertion checks within
assembly source files are enabled or not. This option defaults to the
value of `DEBUG` - that is, by default this is only enabled for a debug
build of the firmware.
* `BL2`: This is an optional build option which specifies the path to BL2 * `BL2`: This is an optional build option which specifies the path to BL2
image for the `fip` target. In this case, the BL2 in the ARM Trusted image for the `fip` target. In this case, the BL2 in the ARM Trusted
Firmware will not be built. Firmware will not be built.
...@@ -286,6 +281,14 @@ performed. ...@@ -286,6 +281,14 @@ performed.
payload. Please refer to the "Booting an EL3 payload" section for more payload. Please refer to the "Booting an EL3 payload" section for more
details. details.
* `ENABLE_ASSERTIONS`: This option controls whether or not calls to `assert()`
are compiled out. For debug builds, this option defaults to 1, and calls to
`assert()` are left in place. For release builds, this option defaults to 0
and calls to `assert()` function are compiled out. This option can be set
independently of `DEBUG`. It can also be used to hide any auxiliary code
that is only required for the assertion and does not fit in the assertion
itself.
* `ENABLE_PMF`: Boolean option to enable support for optional Performance * `ENABLE_PMF`: Boolean option to enable support for optional Performance
Measurement Framework(PMF). Default is 0. Measurement Framework(PMF). Default is 0.
......
drivers/arm/cci/cci.c
View file @ 2edf6482
...@@ -39,7 +39,7 @@ static uintptr_t g_cci_base; ...@@ -39,7 +39,7 @@ static uintptr_t g_cci_base;
static unsigned int g_max_master_id; static unsigned int g_max_master_id;
static const int *g_cci_slave_if_map; static const int *g_cci_slave_if_map;
#if DEBUG #if ENABLE_ASSERTIONS
static int validate_cci_map(const int *map) static int validate_cci_map(const int *map)
{ {
unsigned int valid_cci_map = 0; unsigned int valid_cci_map = 0;
...@@ -72,7 +72,7 @@ static int validate_cci_map(const int *map) ...@@ -72,7 +72,7 @@ static int validate_cci_map(const int *map)
return 1; return 1;
} }
#endif /* DEBUG */ #endif /* ENABLE_ASSERTIONS */
void cci_init(uintptr_t cci_base, void cci_init(uintptr_t cci_base,
const int *map, const int *map,
......
drivers/arm/ccn/ccn.c
View file @ 2edf6482
...@@ -81,7 +81,7 @@ static inline void ccn_reg_write(uintptr_t periphbase, ...@@ -81,7 +81,7 @@ static inline void ccn_reg_write(uintptr_t periphbase,
mmio_write_64(region_base + register_offset, value); mmio_write_64(region_base + register_offset, value);
} }
#if DEBUG #if ENABLE_ASSERTIONS
typedef struct rn_info { typedef struct rn_info {
unsigned char node_desc[MAX_RN_NODES]; unsigned char node_desc[MAX_RN_NODES];
...@@ -224,7 +224,7 @@ static void ccn_validate_plat_params(const ccn_desc_t *plat_desc) ...@@ -224,7 +224,7 @@ static void ccn_validate_plat_params(const ccn_desc_t *plat_desc)
info.node_desc[node_id]--; info.node_desc[node_id]--;
} }
} }
#endif /* DEBUG */ #endif /* ENABLE_ASSERTIONS */
/******************************************************************************* /*******************************************************************************
* This function validates parameters passed by the platform (in a debug build) * This function validates parameters passed by the platform (in a debug build)
...@@ -234,7 +234,7 @@ static void ccn_validate_plat_params(const ccn_desc_t *plat_desc) ...@@ -234,7 +234,7 @@ static void ccn_validate_plat_params(const ccn_desc_t *plat_desc)
******************************************************************************/ ******************************************************************************/
void ccn_init(const ccn_desc_t *plat_desc) void ccn_init(const ccn_desc_t *plat_desc)
{ {
#if DEBUG #if ENABLE_ASSERTIONS
ccn_validate_plat_params(plat_desc); ccn_validate_plat_params(plat_desc);
#endif #endif
......
drivers/arm/tzc/tzc400.c
View file @ 2edf6482
/* /*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
#include <mmio.h> #include <mmio.h>
#include <stddef.h> #include <stddef.h>
#include <tzc400.h> #include <tzc400.h>
#include "tzc_common_private.c" #include "tzc_common_private.h"
/* /*
* Macros which will be used by common core functions. * Macros which will be used by common core functions.
......
drivers/arm/tzc/tzc_common_private.c → drivers/arm/tzc/tzc_common_private.h
View file @ 2edf6482
/* /*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -28,6 +28,9 @@ ...@@ -28,6 +28,9 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef __TZC_COMMON_PRIVATE_H__
#define __TZC_COMMON_PRIVATE_H__
#include <arch.h> #include <arch.h>
#include <arch_helpers.h> #include <arch_helpers.h>
#include <mmio.h> #include <mmio.h>
...@@ -190,8 +193,9 @@ ...@@ -190,8 +193,9 @@
nsaid_permissions); \ nsaid_permissions); \
} }
#if DEBUG #if ENABLE_ASSERTIONS
static unsigned int _tzc_read_peripheral_id(uintptr_t base)
static inline unsigned int _tzc_read_peripheral_id(uintptr_t base)
{ {
unsigned int id; unsigned int id;
...@@ -203,7 +207,7 @@ static unsigned int _tzc_read_peripheral_id(uintptr_t base) ...@@ -203,7 +207,7 @@ static unsigned int _tzc_read_peripheral_id(uintptr_t base)
} }
#ifdef AARCH32 #ifdef AARCH32
static unsigned long long _tzc_get_max_top_addr(int addr_width) static inline unsigned long long _tzc_get_max_top_addr(int addr_width)
{ {
/* /*
* Assume at least 32 bit wide address and initialize the max. * Assume at least 32 bit wide address and initialize the max.
...@@ -232,4 +236,6 @@ static unsigned long long _tzc_get_max_top_addr(int addr_width) ...@@ -232,4 +236,6 @@ static unsigned long long _tzc_get_max_top_addr(int addr_width)
(UINT64_MAX >> (64 - (addr_width))) (UINT64_MAX >> (64 - (addr_width)))
#endif /* AARCH32 */ #endif /* AARCH32 */
#endif #endif /* ENABLE_ASSERTIONS */
#endif /* __TZC_COMMON_PRIVATE_H__ */
drivers/arm/tzc/tzc_dmc500.c
View file @ 2edf6482
/* /*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
#include <mmio.h> #include <mmio.h>
#include <tzc_dmc500.h> #include <tzc_dmc500.h>
#include "tzc_common.h" #include "tzc_common.h"
#include "tzc_common_private.c" #include "tzc_common_private.h"
/* /*
* Macros which will be used by common core functions. * Macros which will be used by common core functions.
...@@ -257,7 +257,7 @@ void tzc_dmc500_set_action(tzc_action_t action) ...@@ -257,7 +257,7 @@ void tzc_dmc500_set_action(tzc_action_t action)
static void validate_plat_driver_data( static void validate_plat_driver_data(
const tzc_dmc500_driver_data_t *plat_driver_data) const tzc_dmc500_driver_data_t *plat_driver_data)
{ {
#if DEBUG #if ENABLE_ASSERTIONS
int i; int i;
unsigned int dmc_id; unsigned int dmc_id;
uintptr_t dmc_base; uintptr_t dmc_base;
...@@ -273,7 +273,7 @@ static void validate_plat_driver_data( ...@@ -273,7 +273,7 @@ static void validate_plat_driver_data(
dmc_id = _tzc_read_peripheral_id(dmc_base); dmc_id = _tzc_read_peripheral_id(dmc_base);
assert(dmc_id == DMC500_PERIPHERAL_ID); assert(dmc_id == DMC500_PERIPHERAL_ID);
} }
#endif /* DEBUG */ #endif /* ENABLE_ASSERTIONS */
} }
......
drivers/io/io_storage.c
View file @ 2edf6482
/* /*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -51,8 +51,8 @@ static const io_dev_info_t *devices[MAX_IO_DEVICES]; ...@@ -51,8 +51,8 @@ static const io_dev_info_t *devices[MAX_IO_DEVICES];
/* Number of currently registered devices */ /* Number of currently registered devices */
static unsigned int dev_count; static unsigned int dev_count;
/* Extra validation functions only used when asserts are enabled */
#if DEBUG /* Extra validation functions only used in debug builds */ #if ENABLE_ASSERTIONS
/* Return a boolean value indicating whether a device connector is valid */ /* Return a boolean value indicating whether a device connector is valid */
static int is_valid_dev_connector(const io_dev_connector_t *dev_con) static int is_valid_dev_connector(const io_dev_connector_t *dev_con)
...@@ -89,7 +89,8 @@ static int is_valid_seek_mode(io_seek_mode_t mode) ...@@ -89,7 +89,8 @@ static int is_valid_seek_mode(io_seek_mode_t mode)
return ((mode != IO_SEEK_INVALID) && (mode < IO_SEEK_MAX)); return ((mode != IO_SEEK_INVALID) && (mode < IO_SEEK_MAX));
} }
#endif /* End of debug-only validation functions */ #endif /* ENABLE_ASSERTIONS */
/* End of extra validation functions only used when asserts are enabled */
/* Open a connection to a specific device */ /* Open a connection to a specific device */
......
include/common/aarch32/el3_common_macros.S
View file @ 2edf6482
...@@ -148,7 +148,7 @@ ...@@ -148,7 +148,7 @@
_init_memory, _init_c_runtime, _exception_vectors _init_memory, _init_c_runtime, _exception_vectors
/* Make sure we are in Secure Mode */ /* Make sure we are in Secure Mode */
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
ldcopr r0, SCR ldcopr r0, SCR
tst r0, #SCR_NS_BIT tst r0, #SCR_NS_BIT
ASM_ASSERT(eq) ASM_ASSERT(eq)
......
include/lib/el3_runtime/context_mgmt.h
View file @ 2edf6482
...@@ -87,7 +87,7 @@ void cm_set_context_by_mpidr(uint64_t mpidr, ...@@ -87,7 +87,7 @@ void cm_set_context_by_mpidr(uint64_t mpidr,
******************************************************************************/ ******************************************************************************/
static inline void cm_set_next_context(void *context) static inline void cm_set_next_context(void *context)
{ {
#if DEBUG #if ENABLE_ASSERTIONS
uint64_t sp_mode; uint64_t sp_mode;
/* /*
...@@ -98,7 +98,7 @@ static inline void cm_set_next_context(void *context) ...@@ -98,7 +98,7 @@ static inline void cm_set_next_context(void *context)
: "=r" (sp_mode)); : "=r" (sp_mode));
assert(sp_mode == MODE_SP_EL0); assert(sp_mode == MODE_SP_EL0);
#endif #endif /* ENABLE_ASSERTIONS */
__asm__ volatile("msr spsel, #1\n" __asm__ volatile("msr spsel, #1\n"
"mov sp, %0\n" "mov sp, %0\n"
......
include/lib/stdlib/assert.h
View file @ 2edf6482
...@@ -34,30 +34,27 @@ ...@@ -34,30 +34,27 @@
* @(#)assert.h 8.2 (Berkeley) 1/21/94 * @(#)assert.h 8.2 (Berkeley) 1/21/94
* $FreeBSD$ * $FreeBSD$
*/ */
#include <sys/cdefs.h>
/* /*
* Unlike other ANSI header files, <assert.h> may usefully be included * Portions copyright (c) 2017, ARM Limited and Contributors.
* multiple times, with and without NDEBUG defined. * All rights reserved.
*/ */
#undef assert #ifndef _ASSERT_H_
#undef _assert #define _ASSERT_H_
#ifdef NDEBUG #include <sys/cdefs.h>
#define assert(e) ((void)0)
#define _assert(e) ((void)0)
#else
#define _assert(e) assert(e)
#if ENABLE_ASSERTIONS
#define _assert(e) assert(e)
#define assert(e) ((e) ? (void)0 : __assert(__func__, __FILE__, \ #define assert(e) ((e) ? (void)0 : __assert(__func__, __FILE__, \
__LINE__, #e)) __LINE__, #e))
#endif /* NDEBUG */ #else
#define assert(e) ((void)0)
#define _assert(e) ((void)0)
#endif /* ENABLE_ASSERTIONS */
#ifndef _ASSERT_H_
#define _ASSERT_H_
__BEGIN_DECLS __BEGIN_DECLS
void __assert(const char *, const char *, int, const char *) __dead2; void __assert(const char *, const char *, int, const char *) __dead2;
__END_DECLS __END_DECLS
#endif /* !_ASSERT_H_ */ #endif /* !_ASSERT_H_ */
lib/aarch32/misc_helpers.S
View file @ 2edf6482
...@@ -162,7 +162,7 @@ endfunc zeromem ...@@ -162,7 +162,7 @@ endfunc zeromem
* -------------------------------------------------------------------------- * --------------------------------------------------------------------------
*/ */
func memcpy4 func memcpy4
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
orr r3, r0, r1 orr r3, r0, r1
tst r3, #0x3 tst r3, #0x3
ASM_ASSERT(eq) ASM_ASSERT(eq)
......
lib/aarch64/misc_helpers.S
View file @ 2edf6482
...@@ -215,7 +215,7 @@ func zeromem_dczva ...@@ -215,7 +215,7 @@ func zeromem_dczva
tmp1 .req x4 tmp1 .req x4
tmp2 .req x5 tmp2 .req x5
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
/* /*
* Check for M bit (MMU enabled) of the current SCTLR_EL(1|3) * Check for M bit (MMU enabled) of the current SCTLR_EL(1|3)
* register value and panic if the MMU is disabled. * register value and panic if the MMU is disabled.
...@@ -228,7 +228,7 @@ func zeromem_dczva ...@@ -228,7 +228,7 @@ func zeromem_dczva
tst tmp1, #SCTLR_M_BIT tst tmp1, #SCTLR_M_BIT
ASM_ASSERT(ne) ASM_ASSERT(ne)
#endif /* ASM_ASSERTION */ #endif /* ENABLE_ASSERTIONS */
/* stop_address is the address past the last to zero */ /* stop_address is the address past the last to zero */
add stop_address, cursor, length add stop_address, cursor, length
...@@ -247,7 +247,7 @@ func zeromem_dczva ...@@ -247,7 +247,7 @@ func zeromem_dczva
mov tmp2, #(1 << 2) mov tmp2, #(1 << 2)
lsl block_size, tmp2, block_size lsl block_size, tmp2, block_size
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
/* /*
* Assumes block size is at least 16 bytes to avoid manual realignment * Assumes block size is at least 16 bytes to avoid manual realignment
* of the cursor at the end of the DCZVA loop. * of the cursor at the end of the DCZVA loop.
...@@ -444,7 +444,7 @@ endfunc zeromem_dczva ...@@ -444,7 +444,7 @@ endfunc zeromem_dczva
* -------------------------------------------------------------------------- * --------------------------------------------------------------------------
*/ */
func memcpy16 func memcpy16
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
orr x3, x0, x1 orr x3, x0, x1
tst x3, #0xf tst x3, #0xf
ASM_ASSERT(eq) ASM_ASSERT(eq)
......
lib/cpus/aarch32/aem_generic.S
View file @ 2edf6482
/* /*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
func aem_generic_core_pwr_dwn func aem_generic_core_pwr_dwn
/* Assert if cache is enabled */ /* Assert if cache is enabled */
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
ldcopr r0, SCTLR ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq) ASM_ASSERT(eq)
...@@ -51,7 +51,7 @@ endfunc aem_generic_core_pwr_dwn ...@@ -51,7 +51,7 @@ endfunc aem_generic_core_pwr_dwn
func aem_generic_cluster_pwr_dwn func aem_generic_cluster_pwr_dwn
/* Assert if cache is enabled */ /* Assert if cache is enabled */
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
ldcopr r0, SCTLR ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq) ASM_ASSERT(eq)
......
lib/cpus/aarch32/cortex_a32.S
View file @ 2edf6482
/* /*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -76,7 +76,7 @@ func cortex_a32_core_pwr_dwn ...@@ -76,7 +76,7 @@ func cortex_a32_core_pwr_dwn
push {r12, lr} push {r12, lr}
/* Assert if cache is enabled */ /* Assert if cache is enabled */
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
ldcopr r0, SCTLR ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq) ASM_ASSERT(eq)
...@@ -107,7 +107,7 @@ func cortex_a32_cluster_pwr_dwn ...@@ -107,7 +107,7 @@ func cortex_a32_cluster_pwr_dwn
push {r12, lr} push {r12, lr}
/* Assert if cache is enabled */ /* Assert if cache is enabled */
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
ldcopr r0, SCTLR ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq) ASM_ASSERT(eq)
......
lib/cpus/aarch32/cpu_helpers.S
View file @ 2edf6482
...@@ -53,7 +53,7 @@ func reset_handler ...@@ -53,7 +53,7 @@ func reset_handler
/* Get the matching cpu_ops pointer (clobbers: r0 - r5) */ /* Get the matching cpu_ops pointer (clobbers: r0 - r5) */
bl get_cpu_ops_ptr bl get_cpu_ops_ptr
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
cmp r0, #0 cmp r0, #0
ASM_ASSERT(ne) ASM_ASSERT(ne)
#endif #endif
...@@ -92,7 +92,7 @@ func prepare_cpu_pwr_dwn ...@@ -92,7 +92,7 @@ func prepare_cpu_pwr_dwn
pop {r2, lr} pop {r2, lr}
ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR] ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR]
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
cmp r0, #0 cmp r0, #0
ASM_ASSERT(ne) ASM_ASSERT(ne)
#endif #endif
...@@ -118,7 +118,7 @@ func init_cpu_ops ...@@ -118,7 +118,7 @@ func init_cpu_ops
cmp r1, #0 cmp r1, #0
bne 1f bne 1f
bl get_cpu_ops_ptr bl get_cpu_ops_ptr
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
cmp r0, #0 cmp r0, #0
ASM_ASSERT(ne) ASM_ASSERT(ne)
#endif #endif
......
lib/cpus/aarch64/cpu_helpers.S
View file @ 2edf6482
...@@ -55,7 +55,7 @@ func reset_handler ...@@ -55,7 +55,7 @@ func reset_handler
/* Get the matching cpu_ops pointer */ /* Get the matching cpu_ops pointer */
bl get_cpu_ops_ptr bl get_cpu_ops_ptr
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
cmp x0, #0 cmp x0, #0
ASM_ASSERT(ne) ASM_ASSERT(ne)
#endif #endif
...@@ -94,7 +94,7 @@ func prepare_cpu_pwr_dwn ...@@ -94,7 +94,7 @@ func prepare_cpu_pwr_dwn
mrs x1, tpidr_el3 mrs x1, tpidr_el3
ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR]
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
cmp x0, #0 cmp x0, #0
ASM_ASSERT(ne) ASM_ASSERT(ne)
#endif #endif
...@@ -120,7 +120,7 @@ func init_cpu_ops ...@@ -120,7 +120,7 @@ func init_cpu_ops
cbnz x0, 1f cbnz x0, 1f
mov x10, x30 mov x10, x30
bl get_cpu_ops_ptr bl get_cpu_ops_ptr
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
cmp x0, #0 cmp x0, #0
ASM_ASSERT(ne) ASM_ASSERT(ne)
#endif #endif
......
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