Merge pull request #745 from rockchip-linux/support-rk3399-dram

Support rk3399 dram

plat/rockchip/rk3399/drivers/dram/dfs.h

+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_DFS_H__
+#define __SOC_ROCKCHIP_RK3399_DFS_H__
+
+struct rk3399_sdram_default_config {
+	unsigned char bl;
+	/* 1:auto precharge, 0:never auto precharge */
+	unsigned char ap;
+	/* dram driver strength */
+	unsigned char dramds;
+	/* dram ODT, if odt=0, this parameter invalid */
+	unsigned char dramodt;
+	/* ca ODT, if odt=0, this parameter invalid
+	 * only used by LPDDR4
+	 */
+	unsigned char caodt;
+	unsigned char burst_ref_cnt;
+	/* zqcs period, unit(s) */
+	unsigned char zqcsi;
+};
+
+struct  ddr_dts_config_timing {
+	unsigned int ddr3_speed_bin;
+	unsigned int pd_idle;
+	unsigned int sr_idle;
+	unsigned int sr_mc_gate_idle;
+	unsigned int srpd_lite_idle;
+	unsigned int standby_idle;
+	unsigned int auto_pd_dis_freq;
+	unsigned int ddr3_dll_dis_freq;
+	unsigned int phy_dll_dis_freq;
+	unsigned int ddr3_odt_dis_freq;
+	unsigned int ddr3_drv;
+	unsigned int ddr3_odt;
+	unsigned int phy_ddr3_ca_drv;
+	unsigned int phy_ddr3_dq_drv;
+	unsigned int phy_ddr3_odt;
+	unsigned int lpddr3_odt_dis_freq;
+	unsigned int lpddr3_drv;
+	unsigned int lpddr3_odt;
+	unsigned int phy_lpddr3_ca_drv;
+	unsigned int phy_lpddr3_dq_drv;
+	unsigned int phy_lpddr3_odt;
+	unsigned int lpddr4_odt_dis_freq;
+	unsigned int lpddr4_drv;
+	unsigned int lpddr4_dq_odt;
+	unsigned int lpddr4_ca_odt;
+	unsigned int phy_lpddr4_ca_drv;
+	unsigned int phy_lpddr4_ck_cs_drv;
+	unsigned int phy_lpddr4_dq_drv;
+	unsigned int phy_lpddr4_odt;
+	uint32_t available;
+};
+
+struct drv_odt_lp_config {
+	uint32_t ddr3_speed_bin;
+	uint32_t pd_idle;
+	uint32_t sr_idle;
+	uint32_t sr_mc_gate_idle;
+	uint32_t srpd_lite_idle;
+	uint32_t standby_idle;
+
+	uint32_t ddr3_dll_dis_freq;/* for ddr3 only */
+	uint32_t phy_dll_dis_freq;
+	uint32_t odt_dis_freq;
+
+	uint32_t dram_side_drv;
+	uint32_t dram_side_dq_odt;
+	uint32_t dram_side_ca_odt;
+
+	uint32_t phy_side_ca_drv;
+	uint32_t phy_side_ck_cs_drv;
+	uint32_t phy_side_dq_drv;
+	uint32_t phy_side_odt;
+};
+
+void ddr_dfs_init(void);
+uint32_t ddr_set_rate(uint32_t hz);
+uint32_t ddr_round_rate(uint32_t hz);
+uint32_t ddr_get_rate(void);
+void clr_dcf_irq(void);
+uint32_t dts_timing_receive(uint32_t timing, uint32_t index);
+#endif

plat/rockchip/rk3399/drivers/dram/dram.h

@@ -28,49 +28,131 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __SOC_ROCKCHIP_RK3399_SDRAM_H__
-#define __SOC_ROCKCHIP_RK3399_SDRAM_H__
-
-struct rk3399_ddr_cic_regs {
-	uint32_t cic_ctrl0;
-	uint32_t cic_ctrl1;
-	uint32_t cic_idle_th;
-	uint32_t cic_cg_wait_th;
-	uint32_t cic_status0;
-	uint32_t cic_status1;
-	uint32_t cic_ctrl2;
-	uint32_t cic_ctrl3;
-	uint32_t cic_ctrl4;
-};
+#ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__
+#define __SOC_ROCKCHIP_RK3399_DRAM_H__
+#include <plat_private.h>
+#include <stdint.h>
+
+#define CTL_BASE(ch)		(0xffa80000 + (ch) * 0x8000)
+#define CTL_REG(ch, n)		(CTL_BASE(ch) + (n) * 0x4)
+
+#define PI_OFFSET		0x800
+#define PI_BASE(ch)		(CTL_BASE(ch) + PI_OFFSET)
+#define PI_REG(ch, n)		(PI_BASE(ch) + (n) * 0x4)
+
+#define PHY_OFFSET		0x2000
+#define PHY_BASE(ch)		(CTL_BASE(ch) + PHY_OFFSET)
+#define PHY_REG(ch, n)		(PHY_BASE(ch) + (n) * 0x4)
+
+#define MSCH_BASE(ch)		(0xffa84000 + (ch) * 0x8000)
+#define MSCH_ID_COREID		0x0
+#define MSCH_ID_REVISIONID	0x4
+#define MSCH_DEVICECONF		0x8
+#define MSCH_DEVICESIZE		0xc
+#define MSCH_DDRTIMINGA0	0x10
+#define MSCH_DDRTIMINGB0	0x14
+#define MSCH_DDRTIMINGC0	0x18
+#define MSCH_DEVTODEV0		0x1c
+#define MSCH_DDRMODE		0x110
+#define MSCH_AGINGX0		0x1000
+
+#define CIC_CTRL0	0x0
+#define CIC_CTRL1	0x4
+#define CIC_IDLE_TH	0x8
+#define CIC_CG_WAIT_TH	0xc
+#define CIC_STATUS0	0x10
+#define CIC_STATUS1	0x14
+#define CIC_CTRL2	0x18
+#define CIC_CTRL3	0x1c
+#define CIC_CTRL4	0x20
 
 /* DENALI_CTL_00 */
-#define START		(1)
+#define START			1
 
 /* DENALI_CTL_68 */
 #define PWRUP_SREFRESH_EXIT	(1 << 16)
 
 /* DENALI_CTL_274 */
-#define MEM_RST_VALID	(1)
+#define MEM_RST_VALID		1
+
+#define PHY_DRV_ODT_Hi_Z	0x0
+#define PHY_DRV_ODT_240		0x1
+#define PHY_DRV_ODT_120		0x8
+#define PHY_DRV_ODT_80		0x9
+#define PHY_DRV_ODT_60		0xc
+#define PHY_DRV_ODT_48		0xd
+#define PHY_DRV_ODT_40		0xe
+#define PHY_DRV_ODT_34_3	0xf
+
+/*
+ * sys_reg bitfield struct
+ * [31] row_3_4_ch1
+ * [30] row_3_4_ch0
+ * [29:28] chinfo
+ * [27] rank_ch1
+ * [26:25] col_ch1
+ * [24] bk_ch1
+ * [23:22] cs0_row_ch1
+ * [21:20] cs1_row_ch1
+ * [19:18] bw_ch1
+ * [17:16] dbw_ch1;
+ * [15:13] ddrtype
+ * [12] channelnum
+ * [11] rank_ch0
+ * [10:9] col_ch0
+ * [8] bk_ch0
+ * [7:6] cs0_row_ch0
+ * [5:4] cs1_row_ch0
+ * [3:2] bw_ch0
+ * [1:0] dbw_ch0
+ */
+#define SYS_REG_ENC_ROW_3_4(n, ch)	((n) << (30 + (ch)))
+#define SYS_REG_DEC_ROW_3_4(n, ch)	(((n) >> (30 + (ch))) & 0x1)
+#define SYS_REG_ENC_CHINFO(ch)		(1 << (28 + (ch)))
+#define SYS_REG_DEC_CHINFO(n, ch)	(((n) >> (28 + (ch))) & 0x1)
+#define SYS_REG_ENC_DDRTYPE(n)		((n) << 13)
+#define SYS_REG_DEC_DDRTYPE(n)		(((n) >> 13) & 0x7)
+#define SYS_REG_ENC_NUM_CH(n)		(((n) - 1) << 12)
+#define SYS_REG_DEC_NUM_CH(n)		(1 + (((n) >> 12) & 0x1))
+#define SYS_REG_ENC_RANK(n, ch)		(((n) - 1) << (11 + (ch) * 16))
+#define SYS_REG_DEC_RANK(n, ch)		(1 + (((n) >> (11 + (ch) * 16)) & 0x1))
+#define SYS_REG_ENC_COL(n, ch)		(((n) - 9) << (9 + (ch) * 16))
+#define SYS_REG_DEC_COL(n, ch)		(9 + (((n) >> (9 + (ch) * 16)) & 0x3))
+#define SYS_REG_ENC_BK(n, ch)		(((n) == 3 ? 0 : 1) << (8 + (ch) * 16))
+#define SYS_REG_DEC_BK(n, ch)		(3 - (((n) >> (8 + (ch) * 16)) & 0x1))
+#define SYS_REG_ENC_CS0_ROW(n, ch)	(((n) - 13) << (6 + (ch) * 16))
+#define SYS_REG_DEC_CS0_ROW(n, ch)	(13 + (((n) >> (6 + (ch) * 16)) & 0x3))
+#define SYS_REG_ENC_CS1_ROW(n, ch)	(((n) - 13) << (4 + (ch) * 16))
+#define SYS_REG_DEC_CS1_ROW(n, ch)	(13 + (((n) >> (4 + (ch) * 16)) & 0x3))
+#define SYS_REG_ENC_BW(n, ch)		((2 >> (n)) << (2 + (ch) * 16))
+#define SYS_REG_DEC_BW(n, ch)		(2 >> (((n) >> (2 + (ch) * 16)) & 0x3))
+#define SYS_REG_ENC_DBW(n, ch)		((2 >> (n)) << (0 + (ch) * 16))
+#define SYS_REG_DEC_DBW(n, ch)		(2 >> (((n) >> (0 + (ch) * 16)) & 0x3))
+#define DDR_STRIDE(n)		mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \
+					      (0x1f<<(10+16))|((n)<<10))
+
+#define CTL_REG_NUM		332
+#define PHY_REG_NUM		959
+#define PI_REG_NUM		200
+
+enum {
+	DDR3 = 3,
+	LPDDR2 = 5,
+	LPDDR3 = 6,
+	LPDDR4 = 7,
+	UNUSED = 0xff
+};
 
 struct rk3399_ddr_pctl_regs {
-	uint32_t denali_ctl[332];
+	uint32_t denali_ctl[CTL_REG_NUM];
 };
 
 struct rk3399_ddr_publ_regs {
-	uint32_t denali_phy[959];
+	uint32_t denali_phy[PHY_REG_NUM];
 };
 
-#define PHY_DRV_ODT_Hi_Z	(0x0)
-#define PHY_DRV_ODT_240		(0x1)
-#define PHY_DRV_ODT_120		(0x8)
-#define PHY_DRV_ODT_80		(0x9)
-#define PHY_DRV_ODT_60		(0xc)
-#define PHY_DRV_ODT_48		(0xd)
-#define PHY_DRV_ODT_40		(0xe)
-#define PHY_DRV_ODT_34_3	(0xf)
-
 struct rk3399_ddr_pi_regs {
-	uint32_t denali_pi[200];
+	uint32_t denali_pi[PI_REG_NUM];
 };
 union noc_ddrtiminga0 {
 	uint32_t d32;
@@ -138,21 +220,6 @@ union noc_ddrmode {
 	} b;
 };
 
-struct rk3399_msch_regs {
-	uint32_t coreid;
-	uint32_t revisionid;
-	uint32_t ddrconf;
-	uint32_t ddrsize;
-	union noc_ddrtiminga0 ddrtiminga0;
-	union noc_ddrtimingb0 ddrtimingb0;
-	union noc_ddrtimingc0 ddrtimingc0;
-	union noc_devtodev0 devtodev0;
-	uint32_t reserved0[(0x110-0x20)/4];
-	union noc_ddrmode ddrmode;
-	uint32_t reserved1[(0x1000-0x114)/4];
-	uint32_t agingx0;
-};
-
 struct rk3399_msch_timings {
 	union noc_ddrtiminga0 ddrtiminga0;
 	union noc_ddrtimingb0 ddrtimingb0;
@@ -161,7 +228,7 @@ struct rk3399_msch_timings {
 	union noc_ddrmode ddrmode;
 	uint32_t agingx0;
 };
-#if 1
+
 struct rk3399_sdram_channel {
 	unsigned char rank;
 	/* col = 0, means this channel is invalid */
@@ -193,137 +260,9 @@ struct rk3399_sdram_params {
 	struct rk3399_ddr_pi_regs pi_regs;
 	struct rk3399_ddr_publ_regs phy_regs;
 };
-#endif
-struct rk3399_sdram_channel_config {
-	uint32_t bus_width;
-	uint32_t cs_cnt;
-	uint32_t cs0_row;
-	uint32_t cs1_row;
-	uint32_t bank;
-	uint32_t col;
-	uint32_t each_die_bus_width;
-	uint32_t each_die_6gb_or_12gb;
-};
-
-struct rk3399_sdram_config {
-	struct rk3399_sdram_channel_config ch[2];
-	uint32_t dramtype;
-	uint32_t channal_num;
-};
-
-struct rk3399_sdram_default_config {
-	unsigned char bl;
-	/* 1:auto precharge, 0:never auto precharge */
-	unsigned char ap;
-	/* dram driver strength */
-	unsigned char dramds;
-	/* dram ODT, if odt=0, this parameter invalid */
-	unsigned char dramodt;
-	/* ca ODT, if odt=0, this parameter invalid
-	 * only used by LPDDR4
-	 */
-	unsigned char caodt;
-	unsigned char burst_ref_cnt;
-	/* zqcs period, unit(s) */
-	unsigned char zqcsi;
-};
-
-struct  ddr_dts_config_timing {
-	unsigned int ddr3_speed_bin;
-	unsigned int pd_idle;
-	unsigned int sr_idle;
-	unsigned int sr_mc_gate_idle;
-	unsigned int srpd_lite_idle;
-	unsigned int standby_idle;
-	unsigned int auto_pd_dis_freq;
-	unsigned int ddr3_dll_dis_freq;
-	unsigned int phy_dll_dis_freq;
-	unsigned int ddr3_odt_dis_freq;
-	unsigned int ddr3_drv;
-	unsigned int ddr3_odt;
-	unsigned int phy_ddr3_ca_drv;
-	unsigned int phy_ddr3_dq_drv;
-	unsigned int phy_ddr3_odt;
-	unsigned int lpddr3_odt_dis_freq;
-	unsigned int lpddr3_drv;
-	unsigned int lpddr3_odt;
-	unsigned int phy_lpddr3_ca_drv;
-	unsigned int phy_lpddr3_dq_drv;
-	unsigned int phy_lpddr3_odt;
-	unsigned int lpddr4_odt_dis_freq;
-	unsigned int lpddr4_drv;
-	unsigned int lpddr4_dq_odt;
-	unsigned int lpddr4_ca_odt;
-	unsigned int phy_lpddr4_ca_drv;
-	unsigned int phy_lpddr4_ck_cs_drv;
-	unsigned int phy_lpddr4_dq_drv;
-	unsigned int phy_lpddr4_odt;
-	uint32_t available;
-};
-
-struct drv_odt_lp_config {
-	uint32_t ddr3_speed_bin;
-	uint32_t pd_idle;
-	uint32_t sr_idle;
-	uint32_t sr_mc_gate_idle;
-	uint32_t srpd_lite_idle;
-	uint32_t standby_idle;
-
-	uint32_t ddr3_dll_dis_freq;/* for ddr3 only */
-	uint32_t phy_dll_dis_freq;
-	uint32_t odt_dis_freq;
-
-	uint32_t dram_side_drv;
-	uint32_t dram_side_dq_odt;
-	uint32_t dram_side_ca_odt;
-
-	uint32_t phy_side_ca_drv;
-	uint32_t phy_side_ck_cs_drv;
-	uint32_t phy_side_dq_drv;
-	uint32_t phy_side_odt;
-};
-
-#define KHz (1000)
-#define MHz (1000*KHz)
-#define GHz (1000*MHz)
-
-#define PI_CA_TRAINING	(1 << 0)
-#define PI_WRITE_LEVELING	(1 << 1)
-#define PI_READ_GATE_TRAINING	(1 << 2)
-#define PI_READ_LEVELING	(1 << 3)
-#define PI_WDQ_LEVELING	(1 << 4)
-#define PI_FULL_TARINING	(0xff)
-
-#define READ_CH_CNT(val)			(1+((val>>12)&0x1))
-#define READ_CH_INFO(val)			((val>>28)&0x3)
-/* row_3_4:0=normal, 1=6Gb or 12Gb */
-#define READ_CH_ROW_INFO(val, ch)	((val>>(30+(ch)))&0x1)
-
-#define READ_DRAMTYPE_INFO(val)		((val>>13)&0x7)
-#define READ_CS_INFO(val, ch)		((((val)>>(11+(ch)*16))&0x1)+1)
-#define READ_BW_INFO(val, ch)		(2>>(((val)>>(2+(ch)*16))&0x3))
-#define READ_COL_INFO(val, ch)		(9+(((val)>>(9+(ch)*16))&0x3))
-#define READ_BK_INFO(val, ch)		(3-(((val)>>(8+(ch)*16))&0x1))
-#define READ_CS0_ROW_INFO(val, ch)	(13+(((val)>>(6+(ch)*16))&0x3))
-#define READ_CS1_ROW_INFO(val, ch)	(13+(((val)>>(4+(ch)*16))&0x3))
-#define READ_DIE_BW_INFO(val, ch)	(2>>((val>>((ch)*16))&0x3))
-
-#define __sramdata __attribute__((section(".sram.data")))
-#define __sramconst __attribute__((section(".sram.rodata")))
-#define __sramlocalfunc __attribute__((section(".sram.text")))
-#define __sramfunc __attribute__((section(".sram.text"))) \
-					__attribute__((noinline))
-
 
-#define DDR_SAVE_SP(save_sp)   (save_sp = ddr_save_sp(((uint32_t)\
-				(SRAM_CODE_BASE + 0x2000) & (~7))))
+extern __sramdata struct rk3399_sdram_params sdram_config;
 
-#define DDR_RESTORE_SP(save_sp)   ddr_save_sp(save_sp)
+void dram_init(void);
 
-void ddr_init(void);
-uint32_t ddr_set_rate(uint32_t hz);
-uint32_t ddr_round_rate(uint32_t hz);
-uint32_t ddr_get_rate(void);
-void clr_dcf_irq(void);
-uint32_t dts_timing_receive(uint32_t timing, uint32_t index);
 #endif

plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c

@@ -30,6 +30,7 @@
 
 #include <string.h>
 #include <stdint.h>
+#include <dram.h>
 #include "dram_spec_timing.h"
 
 static const uint8_t ddr3_cl_cwl[][7] = {

plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h

@@ -32,14 +32,6 @@
 #define _DRAM_SPEC_TIMING_HEAD_
 #include <stdint.h>
 
-enum {
-	DDR3 = 3,
-	LPDDR2 = 5,
-	LPDDR3 = 6,
-	LPDDR4 = 7,
-	UNUSED = 0xFF
-};
-
 enum ddr3_speed_rate {
 	/* 5-5-5 */
 	DDR3_800D = 0,

plat/rockchip/rk3399/drivers/dram/suspend.h

+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_SUSPEND_H__
+#define __SOC_ROCKCHIP_RK3399_SUSPEND_H__
+#include <dram.h>
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define PI_CA_TRAINING		(1 << 0)
+#define PI_WRITE_LEVELING	(1 << 1)
+#define PI_READ_GATE_TRAINING	(1 << 2)
+#define PI_READ_LEVELING	(1 << 3)
+#define PI_WDQ_LEVELING		(1 << 4)
+#define PI_FULL_TRAINING	(0xff)
+
+void dmc_save(void);
+__sramfunc void dmc_restore(void);
+__sramfunc void sram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num);
+
+#endif /* __DRAM_H__ */

plat/rockchip/rk3399/drivers/pmu/plat_pmu_macros.S

@@ -27,9 +27,25 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <platform_def.h>
+#include <pmu_regs.h>
 
 	.globl	clst_warmboot_data
 
+	.macro sram_func _name
+	.section .sram.text, "ax"
+	.type \_name, %function
+	.func \_name
+	\_name:
+	.endm
+
+#define CRU_CLKSEL_CON6	0x118
+
+#define DDRCTL0_C_SYSREQ_CFG 0x0100
+#define DDRCTL1_C_SYSREQ_CFG 0x1000
+
+#define DDRC0_SREF_DONE_EXT 0x01
+#define DDRC1_SREF_DONE_EXT 0x04
+
 #define PLL_MODE_SHIFT	(0x8)
 #define PLL_NORMAL_MODE	((0x3 << (PLL_MODE_SHIFT + 16)) | \
 						 (0x1 << PLL_MODE_SHIFT))
@@ -65,3 +81,75 @@ clst_warmboot_data:
 	.word	0
 	.endr
 .endm
+
+	/* -----------------------------------------------
+	 * void sram_func_set_ddrctl_pll(uint32_t pll_src)
+	 * Function to switch the PLL source for ddrctrl
+	 * In: x0 - The PLL of the clk_ddrc clock source
+	 * out: None
+	 * Clobber list : x0 - x3, x5, x8 - x10
+	 * -----------------------------------------------
+	 */
+
+	.globl	sram_func_set_ddrctl_pll
+
+sram_func sram_func_set_ddrctl_pll
+	/* backup parameter */
+	mov	x8, x0
+
+	/* disable the MMU at EL3 */
+	mrs 	x9, sctlr_el3
+	bic	x10, x9, #(SCTLR_M_BIT)
+	msr 	sctlr_el3, x10
+	isb
+	dsb 	sy
+
+	/* enable ddrctl0_1 idle request */
+	mov	x5, PMU_BASE
+	ldr	w0, [x5, #PMU_SFT_CON]
+	orr	w0, w0, #DDRCTL0_C_SYSREQ_CFG
+	orr	w0, w0, #DDRCTL1_C_SYSREQ_CFG
+	str	w0, [x5, #PMU_SFT_CON]
+
+check_ddrc0_1_sref_enter:
+	ldr	w1, [x5, #PMU_DDR_SREF_ST]
+	and	w2, w1, #DDRC0_SREF_DONE_EXT
+	and	w3, w1, #DDRC1_SREF_DONE_EXT
+	orr	w2, w2, w3
+	cmp	w2, #(DDRC0_SREF_DONE_EXT | DDRC1_SREF_DONE_EXT)
+	b.eq	check_ddrc0_1_sref_enter
+
+	/*
+	 * select a PLL for ddrctrl:
+	 * x0 = 0: ALPLL
+	 * x0 = 1: ABPLL
+	 * x0 = 2: DPLL
+	 * x0 = 3: GPLLL
+	 */
+	mov     x5, CRU_BASE
+	lsl	w0, w8, #4
+	orr	w0, w0, #0x00300000
+	str 	w0, [x5, #CRU_CLKSEL_CON6]
+
+	/* disable ddrctl0_1 idle request */
+	mov	x5, PMU_BASE
+	ldr	w0, [x5, #PMU_SFT_CON]
+	bic	w0, w0, #DDRCTL0_C_SYSREQ_CFG
+	bic	w0, w0, #DDRCTL1_C_SYSREQ_CFG
+	str	w0, [x5, #PMU_SFT_CON]
+
+check_ddrc0_1_sref_exit:
+	ldr	w1, [x5, #PMU_DDR_SREF_ST]
+	and	w2, w1, #DDRC0_SREF_DONE_EXT
+	and	w3, w1, #DDRC1_SREF_DONE_EXT
+	orr	w2, w2, w3
+	cmp	w2, #0x0
+	b.eq	check_ddrc0_1_sref_exit
+
+	/* reenable the MMU at EL3 */
+	msr 	sctlr_el3, x9
+	isb
+	dsb 	sy
+
+	ret
+endfunc sram_func_set_ddrctl_pll

plat/rockchip/rk3399/drivers/pmu/pmu.c

@@ -46,9 +46,9 @@
 #include <pmu.h>
 #include <pmu_com.h>
 #include <pwm.h>
-#include <soc.h>
 #include <bl31.h>
 #include <rk3399m0.h>
+#include <suspend.h>
 
 DEFINE_BAKERY_LOCK(rockchip_pd_lock);
 
@@ -102,7 +102,6 @@ static void pmu_bus_idle_req(uint32_t bus, uint32_t state)
 		     mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK),
 		     bus_ack);
 	}
-
 }
 
 struct pmu_slpdata_s pmu_slpdata;
@@ -818,10 +817,19 @@ static void init_pmu_counts(void)
 	mmio_write_32(PMU_BASE + PMU_GPU_PWRUP_CNT, CYCL_24M_CNT_US(1));
 }
 
+static uint32_t clk_ddrc_save;
+
 static void sys_slp_config(void)
 {
 	uint32_t slp_mode_cfg = 0;
 
+	/* keep enabling clk_ddrc_bpll_src_en gate for DDRC */
+	clk_ddrc_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(3));
+	mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1));
+
+	prepare_abpll_for_ddrctrl();
+	sram_func_set_ddrctl_pll(ABPLL_ID);
+
 	mmio_write_32(GRF_BASE + GRF_SOC_CON4, CCI_FORCE_WAKEUP);
 	mmio_write_32(PMU_BASE + PMU_CCI500_CON,
 		      BIT_WITH_WMSK(PMU_CLR_PREQ_CCI500_HW) |
@@ -849,6 +857,7 @@ static void sys_slp_config(void)
 		       BIT(PMU_DDRIO0_RET_EN) |
 		       BIT(PMU_DDRIO1_RET_EN) |
 		       BIT(PMU_DDRIO_RET_HW_DE_REQ) |
+		       BIT(PMU_CENTER_PD_EN) |
 		       BIT(PMU_PLL_PD_EN) |
 		       BIT(PMU_CLK_CENTER_SRC_GATE_EN) |
 		       BIT(PMU_OSC_DIS) |
@@ -857,7 +866,6 @@ static void sys_slp_config(void)
 	mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN));
 	mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg);
 
-
 	mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW);
 	mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K);
 	mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /* 32k iomux */
@@ -1094,6 +1102,9 @@ static int sys_pwr_domain_suspend(void)
 	uint32_t wait_cnt = 0;
 	uint32_t status = 0;
 
+	dmc_save();
+	pmu_scu_b_pwrdn();
+
 	pmu_power_domains_suspend();
 	set_hw_idle(BIT(PMU_CLR_CENTER1) |
 		    BIT(PMU_CLR_ALIVE) |
@@ -1114,8 +1125,6 @@ static int sys_pwr_domain_suspend(void)
 		      (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) |
 		      CPU_BOOT_ADDR_WMASK);
 
-	pmu_scu_b_pwrdn();
-
 	mmio_write_32(PMU_BASE + PMU_ADB400_CON,
 		      BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) |
 		      BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_SW) |
@@ -1134,6 +1143,7 @@ static int sys_pwr_domain_suspend(void)
 		}
 	}
 	mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
+
 	/*
 	 * Disabling PLLs/PWM/DVFS is approaching WFI which is
 	 * the last steps in suspend.
@@ -1163,6 +1173,10 @@ static int sys_pwr_domain_resume(void)
 	enable_dvfs_plls();
 	plls_resume_finish();
 
+	/* restore clk_ddrc_bpll_src_en gate */
+	mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),
+		      BITS_WITH_WMASK(clk_ddrc_save, 0xff, 0));
+
 	/*
 	 * The wakeup status is not cleared by itself, we need to clear it
 	 * manually. Otherwise we will alway query some interrupt next time.
@@ -1209,8 +1223,12 @@ static int sys_pwr_domain_resume(void)
 
 	pmu_sgrf_rst_hld_release();
 	pmu_scu_b_pwrup();
-
 	pmu_power_domains_resume();
+
+	restore_dpll();
+	sram_func_set_ddrctl_pll(DPLL_ID);
+	restore_abpll();
+
 	clr_hw_idle(BIT(PMU_CLR_CENTER1) |
 				BIT(PMU_CLR_ALIVE) |
 				BIT(PMU_CLR_MSCH0) |
@@ -1301,9 +1319,10 @@ void plat_rockchip_pmu_init(void)
 	for (cpu = 0; cpu < PLATFORM_CLUSTER_COUNT; cpu++)
 		clst_warmboot_data[cpu] = 0;
 
-	psram_sleep_cfg->ddr_func = 0x00;
-	psram_sleep_cfg->ddr_data = 0x00;
-	psram_sleep_cfg->ddr_flag = 0x00;
+	psram_sleep_cfg->ddr_func = (uint64_t)dmc_restore;
+	psram_sleep_cfg->ddr_data = (uint64_t)&sdram_config;
+	psram_sleep_cfg->ddr_flag = 0x01;
+
 	psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff;
 
 	/* config cpu's warm boot address */

plat/rockchip/rk3399/drivers/pmu/pmu.h

@@ -31,6 +31,9 @@
 #ifndef __PMU_H__
 #define __PMU_H__
 
+#include <pmu_regs.h>
+#include <soc.h>
+
 /* Allocate sp reginon in pmusram */
 #define PSRAM_SP_SIZE		0x80
 #define PSRAM_SP_BOTTOM		(PSRAM_SP_TOP - PSRAM_SP_SIZE)
@@ -751,72 +754,7 @@ enum pmu_core_pwr_st {
 	STANDBY_BY_WFIL2_CLUSTER_B,
 };
 
-#define PMU_WKUP_CFG0		0x00
-#define PMU_WKUP_CFG1		0x04
-#define PMU_WKUP_CFG2		0x08
-#define PMU_WKUP_CFG3		0x0c
-#define PMU_WKUP_CFG4		0x10
-#define PMU_PWRDN_CON		0x14
-#define PMU_PWRDN_ST		0x18
-#define PMU_PLL_CON		0x1c
-#define PMU_PWRMODE_CON		0x20
-#define PMU_SFT_CON		0x24
-#define PMU_INT_CON		0x28
-#define PMU_INT_ST		0x2c
-#define PMU_GPIO0_POS_INT_CON	0x30
-#define PMU_GPIO0_NEG_INT_CON	0x34
-#define PMU_GPIO1_POS_INT_CON	0x38
-#define PMU_GPIO1_NEG_INT_CON	0x3c
-#define PMU_GPIO0_POS_INT_ST	0x40
-#define PMU_GPIO0_NEG_INT_ST	0x44
-#define PMU_GPIO1_POS_INT_ST	0x48
-#define PMU_GPIO1_NEG_INT_ST	0x4c
-#define PMU_PWRDN_INTEN		0x50
-#define PMU_PWRDN_STATUS	0x54
-#define PMU_WAKEUP_STATUS	0x58
-#define PMU_BUS_CLR		0x5c
-#define PMU_BUS_IDLE_REQ	0x60
-#define PMU_BUS_IDLE_ST		0x64
-#define PMU_BUS_IDLE_ACK	0x68
-#define PMU_CCI500_CON		0x6c
-#define PMU_ADB400_CON		0x70
-#define PMU_ADB400_ST		0x74
-#define PMU_POWER_ST		0x78
-#define PMU_CORE_PWR_ST		0x7c
-#define PMU_OSC_CNT		0x80
-#define PMU_PLLLOCK_CNT		0x84
-#define PMU_PLLRST_CNT		0x88
-#define PMU_STABLE_CNT		0x8c
-#define PMU_DDRIO_PWRON_CNT	0x90
-#define PMU_WAKEUP_RST_CLR_CNT	0x94
-#define PMU_DDR_SREF_ST		0x98
-#define PMU_SCU_L_PWRDN_CNT	0x9c
-#define PMU_SCU_L_PWRUP_CNT	0xa0
-#define PMU_SCU_B_PWRDN_CNT	0xa4
-#define PMU_SCU_B_PWRUP_CNT	0xa8
-#define PMU_GPU_PWRDN_CNT	0xac
-#define PMU_GPU_PWRUP_CNT	0xb0
-#define PMU_CENTER_PWRDN_CNT	0xb4
-#define PMU_CENTER_PWRUP_CNT	0xb8
-#define PMU_TIMEOUT_CNT		0xbc
-#define PMU_CPU0APM_CON		0xc0
-#define PMU_CPU1APM_CON		0xc4
-#define PMU_CPU2APM_CON		0xc8
-#define PMU_CPU3APM_CON		0xcc
-#define PMU_CPU0BPM_CON		0xd0
-#define PMU_CPU1BPM_CON		0xd4
-#define PMU_NOC_AUTO_ENA	0xd8
-#define PMU_PWRDN_CON1		0xdc
-
-#define PMUGRF_GPIO0A_IOMUX	0x00
-#define PMUGRF_GPIO1A_IOMUX	0x10
-#define PMUGRF_GPIO1C_IOMUX	0x18
-
-#define PMUGRF_GPIO0A6_IOMUX_SHIFT      12
-#define PMUGRF_GPIO0A6_IOMUX_PWM        0x1
-#define PMUGRF_GPIO1C3_IOMUX_SHIFT      6
-#define PMUGRF_GPIO1C3_IOMUX_PWM        0x1
-
+/* Specific features required  */
 #define AP_PWROFF		0x0a
 
 #define GPIO0A0_SMT_ENABLE	BITS_WITH_WMASK(1, 3, 0)
@@ -824,51 +762,6 @@ enum pmu_core_pwr_st {
 
 #define TSADC_INT_PIN		38
 #define CORES_PM_DISABLE	0x0
-#define CPU_AXI_QOS_ID_COREID		0x00
-#define CPU_AXI_QOS_REVISIONID		0x04
-#define CPU_AXI_QOS_PRIORITY		0x08
-#define CPU_AXI_QOS_MODE		0x0c
-#define CPU_AXI_QOS_BANDWIDTH		0x10
-#define CPU_AXI_QOS_SATURATION		0x14
-#define CPU_AXI_QOS_EXTCONTROL		0x18
-#define CPU_AXI_QOS_NUM_REGS		0x07
-
-#define CPU_AXI_CCI_M0_QOS_BASE		0xffa50000
-#define CPU_AXI_CCI_M1_QOS_BASE		0xffad8000
-#define CPU_AXI_DMAC0_QOS_BASE		0xffa64200
-#define CPU_AXI_DMAC1_QOS_BASE		0xffa64280
-#define CPU_AXI_DCF_QOS_BASE		0xffa64180
-#define CPU_AXI_CRYPTO0_QOS_BASE	0xffa64100
-#define CPU_AXI_CRYPTO1_QOS_BASE	0xffa64080
-#define CPU_AXI_PMU_CM0_QOS_BASE	0xffa68000
-#define CPU_AXI_PERI_CM1_QOS_BASE	0xffa64300
-#define CPU_AXI_GIC_QOS_BASE		0xffa78000
-#define CPU_AXI_SDIO_QOS_BASE		0xffa76000
-#define CPU_AXI_SDMMC_QOS_BASE		0xffa74000
-#define CPU_AXI_EMMC_QOS_BASE		0xffa58000
-#define CPU_AXI_GMAC_QOS_BASE		0xffa5c000
-#define CPU_AXI_USB_OTG0_QOS_BASE	0xffa70000
-#define CPU_AXI_USB_OTG1_QOS_BASE	0xffa70080
-#define CPU_AXI_USB_HOST0_QOS_BASE	0xffa60100
-#define CPU_AXI_USB_HOST1_QOS_BASE	0xffa60180
-#define CPU_AXI_GPU_QOS_BASE		0xffae0000
-#define CPU_AXI_VIDEO_M0_QOS_BASE	0xffab8000
-#define CPU_AXI_VIDEO_M1_R_QOS_BASE	0xffac0000
-#define CPU_AXI_VIDEO_M1_W_QOS_BASE	0xffac0080
-#define CPU_AXI_RGA_R_QOS_BASE		0xffab0000
-#define CPU_AXI_RGA_W_QOS_BASE		0xffab0080
-#define CPU_AXI_IEP_QOS_BASE		0xffa98000
-#define CPU_AXI_VOP_BIG_R_QOS_BASE	0xffac8000
-#define CPU_AXI_VOP_BIG_W_QOS_BASE	0xffac8080
-#define CPU_AXI_VOP_LITTLE_QOS_BASE	0xffad0000
-#define CPU_AXI_ISP0_M0_QOS_BASE	0xffaa0000
-#define CPU_AXI_ISP0_M1_QOS_BASE	0xffaa0080
-#define CPU_AXI_ISP1_M0_QOS_BASE	0xffaa8000
-#define CPU_AXI_ISP1_M1_QOS_BASE	0xffaa8080
-#define CPU_AXI_HDCP_QOS_BASE		0xffa90000
-#define CPU_AXI_PERIHP_NSP_QOS_BASE	0xffad8080
-#define CPU_AXI_PERILP_NSP_QOS_BASE	0xffad8180
-#define CPU_AXI_PERILPSLV_NSP_QOS_BASE	0xffad8100
 
 #define PD_CTR_LOOP		500
 #define CHK_CPU_LOOP		500
@@ -876,32 +769,6 @@ enum pmu_core_pwr_st {
 
 #define	GRF_SOC_CON4		0x0e210
 
-#define GRF_GPIO2A_IOMUX	0xe000
-#define GRF_GPIO2B_IOMUX	0xe004
-#define GRF_GPIO2C_IOMUX	0xe008
-#define GRF_GPIO2D_IOMUX	0xe00c
-#define GRF_GPIO3A_IOMUX	0xe010
-#define GRF_GPIO3B_IOMUX	0xe014
-#define GRF_GPIO3C_IOMUX	0xe018
-#define GRF_GPIO3D_IOMUX	0xe01c
-#define GRF_GPIO4A_IOMUX	0xe020
-#define GRF_GPIO4B_IOMUX	0xe024
-#define GRF_GPIO4C_IOMUX	0xe028
-#define GRF_GPIO4D_IOMUX	0xe02c
-
-#define GRF_GPIO2A_P		0xe040
-#define GRF_GPIO2B_P		0xe044
-#define GRF_GPIO2C_P		0xe048
-#define GRF_GPIO2D_P		0xe04C
-#define GRF_GPIO3A_P		0xe050
-#define GRF_GPIO3B_P		0xe054
-#define GRF_GPIO3C_P		0xe058
-#define GRF_GPIO3D_P		0xe05C
-#define GRF_GPIO4A_P		0xe060
-#define GRF_GPIO4B_P		0xe064
-#define GRF_GPIO4C_P		0xe068
-#define GRF_GPIO4D_P		0xe06C
-
 #define PMUGRF_GPIO0A_SMT	0x0120
 #define PMUGRF_SOC_CON0		0x0180
 
@@ -977,4 +844,7 @@ struct pmu_slpdata_s {
 };
 
 extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT];
+
+extern void sram_func_set_ddrctl_pll(uint32_t pll_src);
+
 #endif /* __PMU_H__ */

plat/rockchip/rk3399/drivers/pmu/pmu_regs.h

+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PMU_REGS_H__
+#define __PMU_REGS_H__
+
+#define PMU_WKUP_CFG0		0x00
+#define PMU_WKUP_CFG1		0x04
+#define PMU_WKUP_CFG2		0x08
+#define PMU_WKUP_CFG3		0x0c
+#define PMU_WKUP_CFG4		0x10
+#define PMU_PWRDN_CON		0x14
+#define PMU_PWRDN_ST		0x18
+#define PMU_PLL_CON		0x1c
+#define PMU_PWRMODE_CON		0x20
+#define PMU_SFT_CON		0x24
+#define PMU_INT_CON		0x28
+#define PMU_INT_ST		0x2c
+#define PMU_GPIO0_POS_INT_CON	0x30
+#define PMU_GPIO0_NEG_INT_CON	0x34
+#define PMU_GPIO1_POS_INT_CON	0x38
+#define PMU_GPIO1_NEG_INT_CON	0x3c
+#define PMU_GPIO0_POS_INT_ST	0x40
+#define PMU_GPIO0_NEG_INT_ST	0x44
+#define PMU_GPIO1_POS_INT_ST	0x48
+#define PMU_GPIO1_NEG_INT_ST	0x4c
+#define PMU_PWRDN_INTEN		0x50
+#define PMU_PWRDN_STATUS	0x54
+#define PMU_WAKEUP_STATUS	0x58
+#define PMU_BUS_CLR		0x5c
+#define PMU_BUS_IDLE_REQ	0x60
+#define PMU_BUS_IDLE_ST		0x64
+#define PMU_BUS_IDLE_ACK	0x68
+#define PMU_CCI500_CON		0x6c
+#define PMU_ADB400_CON		0x70
+#define PMU_ADB400_ST		0x74
+#define PMU_POWER_ST		0x78
+#define PMU_CORE_PWR_ST		0x7c
+#define PMU_OSC_CNT		0x80
+#define PMU_PLLLOCK_CNT		0x84
+#define PMU_PLLRST_CNT		0x88
+#define PMU_STABLE_CNT		0x8c
+#define PMU_DDRIO_PWRON_CNT	0x90
+#define PMU_WAKEUP_RST_CLR_CNT	0x94
+#define PMU_DDR_SREF_ST		0x98
+#define PMU_SCU_L_PWRDN_CNT	0x9c
+#define PMU_SCU_L_PWRUP_CNT	0xa0
+#define PMU_SCU_B_PWRDN_CNT	0xa4
+#define PMU_SCU_B_PWRUP_CNT	0xa8
+#define PMU_GPU_PWRDN_CNT	0xac
+#define PMU_GPU_PWRUP_CNT	0xb0
+#define PMU_CENTER_PWRDN_CNT	0xb4
+#define PMU_CENTER_PWRUP_CNT	0xb8
+#define PMU_TIMEOUT_CNT		0xbc
+#define PMU_CPU0APM_CON		0xc0
+#define PMU_CPU1APM_CON		0xc4
+#define PMU_CPU2APM_CON		0xc8
+#define PMU_CPU3APM_CON		0xcc
+#define PMU_CPU0BPM_CON		0xd0
+#define PMU_CPU1BPM_CON		0xd4
+#define PMU_NOC_AUTO_ENA	0xd8
+#define PMU_PWRDN_CON1		0xdc
+
+#define PMUGRF_GPIO0A_IOMUX	0x00
+#define PMUGRF_GPIO1A_IOMUX	0x10
+#define PMUGRF_GPIO1C_IOMUX	0x18
+
+#define PMUGRF_GPIO0A6_IOMUX_SHIFT      12
+#define PMUGRF_GPIO0A6_IOMUX_PWM        0x1
+#define PMUGRF_GPIO1C3_IOMUX_SHIFT      6
+#define PMUGRF_GPIO1C3_IOMUX_PWM        0x1
+
+#define CPU_AXI_QOS_ID_COREID		0x00
+#define CPU_AXI_QOS_REVISIONID		0x04
+#define CPU_AXI_QOS_PRIORITY		0x08
+#define CPU_AXI_QOS_MODE		0x0c
+#define CPU_AXI_QOS_BANDWIDTH		0x10
+#define CPU_AXI_QOS_SATURATION		0x14
+#define CPU_AXI_QOS_EXTCONTROL		0x18
+#define CPU_AXI_QOS_NUM_REGS		0x07
+
+#define CPU_AXI_CCI_M0_QOS_BASE		0xffa50000
+#define CPU_AXI_CCI_M1_QOS_BASE		0xffad8000
+#define CPU_AXI_DMAC0_QOS_BASE		0xffa64200
+#define CPU_AXI_DMAC1_QOS_BASE		0xffa64280
+#define CPU_AXI_DCF_QOS_BASE		0xffa64180
+#define CPU_AXI_CRYPTO0_QOS_BASE	0xffa64100
+#define CPU_AXI_CRYPTO1_QOS_BASE	0xffa64080
+#define CPU_AXI_PMU_CM0_QOS_BASE	0xffa68000
+#define CPU_AXI_PERI_CM1_QOS_BASE	0xffa64300
+#define CPU_AXI_GIC_QOS_BASE		0xffa78000
+#define CPU_AXI_SDIO_QOS_BASE		0xffa76000
+#define CPU_AXI_SDMMC_QOS_BASE		0xffa74000
+#define CPU_AXI_EMMC_QOS_BASE		0xffa58000
+#define CPU_AXI_GMAC_QOS_BASE		0xffa5c000
+#define CPU_AXI_USB_OTG0_QOS_BASE	0xffa70000
+#define CPU_AXI_USB_OTG1_QOS_BASE	0xffa70080
+#define CPU_AXI_USB_HOST0_QOS_BASE	0xffa60100
+#define CPU_AXI_USB_HOST1_QOS_BASE	0xffa60180
+#define CPU_AXI_GPU_QOS_BASE		0xffae0000
+#define CPU_AXI_VIDEO_M0_QOS_BASE	0xffab8000
+#define CPU_AXI_VIDEO_M1_R_QOS_BASE	0xffac0000
+#define CPU_AXI_VIDEO_M1_W_QOS_BASE	0xffac0080
+#define CPU_AXI_RGA_R_QOS_BASE		0xffab0000
+#define CPU_AXI_RGA_W_QOS_BASE		0xffab0080
+#define CPU_AXI_IEP_QOS_BASE		0xffa98000
+#define CPU_AXI_VOP_BIG_R_QOS_BASE	0xffac8000
+#define CPU_AXI_VOP_BIG_W_QOS_BASE	0xffac8080
+#define CPU_AXI_VOP_LITTLE_QOS_BASE	0xffad0000
+#define CPU_AXI_ISP0_M0_QOS_BASE	0xffaa0000
+#define CPU_AXI_ISP0_M1_QOS_BASE	0xffaa0080
+#define CPU_AXI_ISP1_M0_QOS_BASE	0xffaa8000
+#define CPU_AXI_ISP1_M1_QOS_BASE	0xffaa8080
+#define CPU_AXI_HDCP_QOS_BASE		0xffa90000
+#define CPU_AXI_PERIHP_NSP_QOS_BASE	0xffad8080
+#define CPU_AXI_PERILP_NSP_QOS_BASE	0xffad8180
+#define CPU_AXI_PERILPSLV_NSP_QOS_BASE	0xffad8100
+
+#define GRF_GPIO2A_IOMUX	0xe000
+#define GRF_GPIO2B_IOMUX	0xe004
+#define GRF_GPIO2C_IOMUX	0xe008
+#define GRF_GPIO2D_IOMUX	0xe00c
+#define GRF_GPIO3A_IOMUX	0xe010
+#define GRF_GPIO3B_IOMUX	0xe014
+#define GRF_GPIO3C_IOMUX	0xe018
+#define GRF_GPIO3D_IOMUX	0xe01c
+#define GRF_GPIO4A_IOMUX	0xe020
+#define GRF_GPIO4B_IOMUX	0xe024
+#define GRF_GPIO4C_IOMUX	0xe028
+#define GRF_GPIO4D_IOMUX	0xe02c
+
+#define GRF_GPIO2A_P		0xe040
+#define GRF_GPIO2B_P		0xe044
+#define GRF_GPIO2C_P		0xe048
+#define GRF_GPIO2D_P		0xe04C
+#define GRF_GPIO3A_P		0xe050
+#define GRF_GPIO3B_P		0xe054
+#define GRF_GPIO3C_P		0xe058
+#define GRF_GPIO3D_P		0xe05C
+#define GRF_GPIO4A_P		0xe060
+#define GRF_GPIO4B_P		0xe064
+#define GRF_GPIO4C_P		0xe068
+#define GRF_GPIO4D_P		0xe06C
+
+#endif /* __PMU_REGS_H__ */

plat/rockchip/rk3399/drivers/soc/soc.c

@@ -34,6 +34,7 @@
 #include <mmio.h>
 #include <platform_def.h>
 #include <plat_private.h>
+#include <dram.h>
 #include <rk3399_def.h>
 #include <rk3399m0.h>
 #include <soc.h>
@@ -42,6 +43,8 @@
 const mmap_region_t plat_rk_mmap[] = {
 	MAP_REGION_FLAT(RK3399_DEV_RNG0_BASE, RK3399_DEV_RNG0_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
+			MT_MEMORY | MT_RW | MT_SECURE),
 
 	{ 0 }
 };
@@ -237,21 +240,105 @@ static void _pll_suspend(uint32_t pll_id)
 	set_pll_bypass(pll_id);
 }
 
+/**
+ * disable_dvfs_plls - To suspend the specific PLLs
+ *
+ * When we close the center logic, the DPLL will be closed,
+ * so we need to keep the ABPLL and switch to it to supply
+ * clock for DDR during suspend, then we should not close
+ * the ABPLL and exclude ABPLL_ID.
+ */
 void disable_dvfs_plls(void)
 {
 	_pll_suspend(CPLL_ID);
 	_pll_suspend(NPLL_ID);
 	_pll_suspend(VPLL_ID);
 	_pll_suspend(GPLL_ID);
-	_pll_suspend(ABPLL_ID);
 	_pll_suspend(ALPLL_ID);
 }
 
+/**
+ * disable_nodvfs_plls - To suspend the PPLL
+ */
 void disable_nodvfs_plls(void)
 {
 	_pll_suspend(PPLL_ID);
 }
 
+/**
+ * restore_pll - Copy PLL settings from memory to a PLL.
+ *
+ * This will copy PLL settings from an array in memory to the memory mapped
+ * registers for a PLL.
+ *
+ * Note that: above the PLL exclude PPLL.
+ *
+ * pll_id: One of the values from enum plls_id
+ * src: Pointer to the array of values to restore from
+ */
+static void restore_pll(int pll_id, uint32_t *src)
+{
+	/* Nice to have PLL off while configuring */
+	mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
+
+	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK);
+	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK);
+	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]);
+	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK);
+	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK);
+
+	/* Do PLL_CON3 since that will enable things */
+	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK);
+
+	/* Wait for PLL lock done */
+	while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) &
+		0x80000000) == 0x0)
+		;
+}
+
+/**
+ * save_pll - Copy PLL settings a PLL to memory
+ *
+ * This will copy PLL settings from the memory mapped registers for a PLL to
+ * an array in memory.
+ *
+ * Note that: above the PLL exclude PPLL.
+ *
+ * pll_id: One of the values from enum plls_id
+ * src: Pointer to the array of values to save to.
+ */
+static void save_pll(uint32_t *dst, int pll_id)
+{
+	int i;
+
+	for (i = 0; i < PLL_CON_COUNT; i++)
+		dst[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i));
+}
+
+/**
+ * prepare_abpll_for_ddrctrl - Copy DPLL settings to ABPLL
+ *
+ * This will copy DPLL settings from the memory mapped registers for a PLL to
+ * an array in memory.
+ */
+void prepare_abpll_for_ddrctrl(void)
+{
+	save_pll(slp_data.plls_con[ABPLL_ID], ABPLL_ID);
+	save_pll(slp_data.plls_con[DPLL_ID], DPLL_ID);
+
+	restore_pll(ABPLL_ID, slp_data.plls_con[DPLL_ID]);
+}
+
+void restore_abpll(void)
+{
+	restore_pll(ABPLL_ID, slp_data.plls_con[ABPLL_ID]);
+}
+
+void restore_dpll(void)
+{
+	restore_pll(DPLL_ID, slp_data.plls_con[DPLL_ID]);
+}
+
 void plls_suspend_prepare(void)
 {
 	uint32_t i, pll_id;
@@ -342,16 +429,25 @@ void plls_resume_finish(void)
 			      REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]);
 }
 
+/**
+ * enable_dvfs_plls - To resume the specific PLLs
+ *
+ * Please see the comment at the disable_dvfs_plls()
+ * we don't suspend the ABPLL, so don't need resume
+ * it too.
+ */
 void enable_dvfs_plls(void)
 {
 	_pll_resume(ALPLL_ID);
-	_pll_resume(ABPLL_ID);
 	_pll_resume(GPLL_ID);
 	_pll_resume(VPLL_ID);
 	_pll_resume(NPLL_ID);
 	_pll_resume(CPLL_ID);
 }
 
+/**
+ * enable_nodvfs_plls - To resume the PPLL
+ */
 void enable_nodvfs_plls(void)
 {
 	_pll_resume(PPLL_ID);
@@ -410,4 +506,5 @@ void plat_rockchip_soc_init(void)
 	soc_global_soft_reset_init();
 	plat_rockchip_gpio_init();
 	soc_m0_init();
+	dram_init();
 }

plat/rockchip/rk3399/drivers/soc/soc.h

@@ -245,6 +245,8 @@ struct deepsleep_data_s {
 #define SGRF_PMU_SLV_CON1_CFG		(SGRF_SLV_S_WMSK | \
 					SGRF_PMUSRAM_S)
 /* ddr region */
+#define SGRF_DDR_RGN_DPLL_CLK	BIT_WITH_WMSK(15) /* DDR PLL output clock */
+#define SGRF_DDR_RGN_RTC_CLK	BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */
 #define SGRF_DDR_RGN_BYPS	BIT_WITH_WMSK(9) /* All of ddr rgn  is ns */
 
 /* The MST access the ddr rgn n with secure attribution */
@@ -334,7 +336,11 @@ void disable_nodvfs_plls(void);
 void plls_resume_finish(void);
 void enable_dvfs_plls(void);
 void enable_nodvfs_plls(void);
+void prepare_abpll_for_ddrctrl(void);
+void restore_abpll(void);
+void restore_dpll(void);
 void clk_gate_con_save(void);
 void clk_gate_con_disable(void);
 void clk_gate_con_restore(void);
+void sgrf_init(void);
 #endif /* __SOC_H__ */

plat/rockchip/rk3399/plat_sip_calls.c

@@ -29,7 +29,7 @@
 #include <plat_sip_calls.h>
 #include <rockchip_sip_svc.h>
 #include <runtime_svc.h>
-#include <dram.h>
+#include <dfs.h>
 
 #define RK_SIP_DDR_CFG		0x82000008
 #define DRAM_INIT		0x00
@@ -45,7 +45,7 @@ uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id)
 {
 	switch (id) {
 	case DRAM_INIT:
-		ddr_init();
+		ddr_dfs_init();
 		break;
 	case DRAM_SET_RATE:
 		return ddr_set_rate((uint32_t)arg0);

plat/rockchip/rk3399/platform.mk

@@ -79,6 +79,8 @@ BL31_SOURCES            +=      ${RK_GIC_SOURCES}
                                 ${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c             \
 				${RK_PLAT_SOC}/drivers/pwm/pwm.c	\
                                 ${RK_PLAT_SOC}/drivers/soc/soc.c		\
+				${RK_PLAT_SOC}/drivers/dram/dfs.c		\
+                                ${RK_PLAT_SOC}/drivers/dram/suspend.c           \
 				${RK_PLAT_SOC}/drivers/dram/dram.c		\
 				${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c