From 383c80899960cf41bcdd63f200b9cf5c12005b06 Mon Sep 17 00:00:00 2001
From: Dimitris Papastamos <dimitris.papastamos@arm.com>
Date: Wed, 24 Jan 2018 16:41:14 +0000
Subject: [PATCH] Disable workaround for CVE-2017-5715 on unaffected platforms
Change-Id: Ib67b841ab621ca1ace3280e44cf3e1d83052cb73
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
---
plat/hisilicon/hikey/platform.mk | 2 ++
plat/hisilicon/poplar/platform.mk | 2 ++
plat/mediatek/mt6795/platform.mk | 2 ++
plat/rockchip/rk3328/platform.mk | 2 ++
plat/rockchip/rk3368/platform.mk | 2 ++
plat/rpi3/platform.mk | 2 ++
plat/xilinx/zynqmp/platform.mk | 2 ++
7 files changed, 14 insertions(+)
diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk
index c8a29924a..b11d2085e 100644
--- a/plat/hisilicon/hikey/platform.mk
+++ b/plat/hisilicon/hikey/platform.mk
@@ -122,4 +122,6 @@ ERRATA_A53_836870 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+WORKAROUND_CVE_2017_5715 := 0
+
FIP_ALIGN := 512
diff --git a/plat/hisilicon/poplar/platform.mk b/plat/hisilicon/poplar/platform.mk
index 2dbbac6e7..d53e06274 100644
--- a/plat/hisilicon/poplar/platform.mk
+++ b/plat/hisilicon/poplar/platform.mk
@@ -29,6 +29,8 @@ ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ENABLE_SVE_FOR_NS := 0
+WORKAROUND_CVE_2017_5715 := 0
+
ARM_GIC_ARCH := 2
$(eval $(call add_define,ARM_GIC_ARCH))
diff --git a/plat/mediatek/mt6795/platform.mk b/plat/mediatek/mt6795/platform.mk
index 82300674d..1bdf30af3 100644
--- a/plat/mediatek/mt6795/platform.mk
+++ b/plat/mediatek/mt6795/platform.mk
@@ -61,6 +61,8 @@ $(eval $(call add_define,ARM_GIC_ARCH))
ERRATA_A53_826319 := 1
ERRATA_A53_836870 := 1
+WORKAROUND_CVE_2017_5715 := 0
+
# indicate the reset vector address can be programmed
PROGRAMMABLE_RESET_ADDRESS := 1
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index 6e4d5b4dc..f0fd36f9b 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -58,3 +58,5 @@ $(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER))
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
+
+WORKAROUND_CVE_2017_5715 := 0
diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk
index ad204e9eb..7ecb21ad5 100644
--- a/plat/rockchip/rk3368/platform.mk
+++ b/plat/rockchip/rk3368/platform.mk
@@ -57,3 +57,5 @@ $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
+
+WORKAROUND_CVE_2017_5715 := 0
diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk
index 821f80153..e201ceed0 100644
--- a/plat/rpi3/platform.mk
+++ b/plat/rpi3/platform.mk
@@ -64,6 +64,8 @@ ERRATA_A53_836870 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+WORKAROUND_CVE_2017_5715 := 0
+
# Disable the PSCI platform compatibility layer by default
ENABLE_PLAT_COMPAT := 0
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index bdd194bda..bddf30562 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -14,6 +14,8 @@ override RESET_TO_BL31 := 1
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
+WORKAROUND_CVE_2017_5715 := 0
+
ifdef ZYNQMP_ATF_MEM_BASE
$(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
--
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