Commit 394a65aa authored by Tejas Patel's avatar Tejas Patel Committed by Jolly Shah
Browse files

xilinx: versal: Remove no_pmc ops to ON power domain



Add PMC ops for power domain ON and remove no_pmc ops.
Signed-off-by: default avatarTejas Patel <tejas.patel@xilinx.com>
Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Change-Id: Id4308dfe124b60a751765beb3397d1b0071f14fc
parent 42cd77e3
...@@ -5,56 +5,35 @@ ...@@ -5,56 +5,35 @@
*/ */
#include <plat_private.h> #include <plat_private.h>
#include <pm_common.h>
#include <common/debug.h> #include <common/debug.h>
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/psci/psci.h> #include <lib/psci/psci.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include "pm_api_sys.h"
#include "pm_client.h"
static uintptr_t versal_sec_entry; static uintptr_t versal_sec_entry;
static int versal_nopmc_pwr_domain_on(u_register_t mpidr) static int versal_pwr_domain_on(u_register_t mpidr)
{ {
uint32_t r;
unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
const struct pm_proc *proc;
VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
if (cpu_id == -1) if (cpu_id == -1)
return PSCI_E_INTERN_FAIL; return PSCI_E_INTERN_FAIL;
/* proc = pm_get_proc(cpu_id);
* program RVBAR
*/
mmio_write_32(FPD_APU_RVBAR_L_0 + (cpu_id << 3), versal_sec_entry);
mmio_write_32(FPD_APU_RVBAR_H_0 + (cpu_id << 3), versal_sec_entry >> 32);
/* /* Send request to PMC to wake up selected ACPU core */
* clear VINITHI pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFF) | 0x1,
*/ versal_sec_entry >> 32, 0);
r = mmio_read_32(FPD_APU_CONFIG_0);
r &= ~(1 << FPD_APU_CONFIG_0_VINITHI_SHIFT << cpu_id);
mmio_write_32(FPD_APU_CONFIG_0, r);
/*
* FIXME: Add power up sequence, By default it works
* now without the need of it as it was powered up by
* default.
*/
/* /* Clear power down request */
* clear power down request pm_client_wakeup(proc);
*/
r = mmio_read_32(FPD_APU_PWRCTL);
r &= ~(1 << cpu_id);
mmio_write_32(FPD_APU_PWRCTL, r);
/*
* release core reset
*/
r = mmio_read_32(CRF_RST_APU);
r &= ~((CRF_RST_APU_ACPU_PWRON_RESET |
CRF_RST_APU_ACPU_RESET) << cpu_id);
mmio_write_32(CRF_RST_APU, r);
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
} }
...@@ -69,7 +48,7 @@ void versal_pwr_domain_on_finish(const psci_power_state_t *target_state) ...@@ -69,7 +48,7 @@ void versal_pwr_domain_on_finish(const psci_power_state_t *target_state)
} }
static const struct plat_psci_ops versal_nopmc_psci_ops = { static const struct plat_psci_ops versal_nopmc_psci_ops = {
.pwr_domain_on = versal_nopmc_pwr_domain_on, .pwr_domain_on = versal_pwr_domain_on,
.pwr_domain_on_finish = versal_pwr_domain_on_finish, .pwr_domain_on_finish = versal_pwr_domain_on_finish,
}; };
......
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