From 39faa9b291abfdbab98235d38a5a0be908409eaa Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Wed, 9 Dec 2020 14:02:39 +0530 Subject: [PATCH] nxp: adding the smmu driver NXP SMMU driver API for NXP SoC. - Currently it supports by-passing SMMU, called only when NXP CAAM is enabled. - (TBD) AMQ based SMMU access control: Access Management Qualifiers (AMQ) advertised by a bus master for a given transaction. Signed-off-by: Pankaj Gupta Change-Id: I23a12928ddedb1a2cf4b396606e35c67e016e331 --- include/drivers/nxp/smmu/nxp_smmu.h | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/drivers/nxp/smmu/nxp_smmu.h diff --git a/include/drivers/nxp/smmu/nxp_smmu.h b/include/drivers/nxp/smmu/nxp_smmu.h new file mode 100644 index 000000000..d64c33b20 --- /dev/null +++ b/include/drivers/nxp/smmu/nxp_smmu.h @@ -0,0 +1,30 @@ +/* + * Copyright 2018-2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef NXP_SMMU_H +#define NXP_SMMU_H + +#define SMMU_SCR0 (0x0) +#define SMMU_NSCR0 (0x400) + +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SCR0_USFCFG_MASK 0x00000400 + +static inline void bypass_smmu(uintptr_t smmu_base_addr) +{ + uint32_t val; + + val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) & + ~(SCR0_USFCFG_MASK); + mmio_write_32((smmu_base_addr + SMMU_SCR0), val); + + val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & + ~(SCR0_USFCFG_MASK); + mmio_write_32((smmu_base_addr + SMMU_NSCR0), val); +} + +#endif -- GitLab