Unverified Commit 3ba92957 authored by Dimitris Papastamos's avatar Dimitris Papastamos Committed by GitHub
Browse files

Merge pull request #1510 from robertovargas-arm/romlib

Add support for moving libraries to ROM
parents 0983b8b1 1eb735d7
...@@ -71,9 +71,12 @@ ...@@ -71,9 +71,12 @@
#elif defined(IMAGE_BL32) #elif defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES 8 # define PLAT_ARM_MMAP_ENTRIES 8
# define MAX_XLAT_TABLES 5 # define MAX_XLAT_TABLES 5
#else #elif !USE_ROMLIB
# define PLAT_ARM_MMAP_ENTRIES 11 # define PLAT_ARM_MMAP_ENTRIES 11
# define MAX_XLAT_TABLES 5 # define MAX_XLAT_TABLES 5
#else
# define PLAT_ARM_MMAP_ENTRIES 12
# define MAX_XLAT_TABLES 6
#endif #endif
/* /*
...@@ -82,6 +85,18 @@ ...@@ -82,6 +85,18 @@
*/ */
#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
/*
* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
*/
#if USE_ROMLIB
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
#else
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
#endif
/* /*
* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
* little space for growth. * little space for growth.
......
...@@ -268,6 +268,17 @@ ...@@ -268,6 +268,17 @@
- BL_COHERENT_RAM_BASE, \ - BL_COHERENT_RAM_BASE, \
MT_DEVICE | MT_RW | MT_SECURE) MT_DEVICE | MT_RW | MT_SECURE)
#endif #endif
#if USE_ROMLIB
#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \
ROMLIB_RO_BASE, \
ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\
MT_CODE | MT_SECURE)
#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \
ROMLIB_RW_BASE, \
ROMLIB_RW_END - ROMLIB_RW_BASE,\
MT_MEMORY | MT_RW | MT_SECURE)
#endif
/* /*
* The max number of regions like RO(code), coherent and data required by * The max number of regions like RO(code), coherent and data required by
...@@ -346,14 +357,23 @@ ...@@ -346,14 +357,23 @@
******************************************************************************/ ******************************************************************************/
#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
+ PLAT_ARM_TRUSTED_ROM_SIZE) + (PLAT_ARM_TRUSTED_ROM_SIZE - \
PLAT_ARM_MAX_ROMLIB_RO_SIZE))
/* /*
* Put BL1 RW at the top of the Trusted SRAM. * Put BL1 RW at the top of the Trusted SRAM.
*/ */
#define BL1_RW_BASE (ARM_BL_RAM_BASE + \ #define BL1_RW_BASE (ARM_BL_RAM_BASE + \
ARM_BL_RAM_SIZE - \ ARM_BL_RAM_SIZE - \
PLAT_ARM_MAX_BL1_RW_SIZE) (PLAT_ARM_MAX_BL1_RW_SIZE +\
#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) PLAT_ARM_MAX_ROMLIB_RW_SIZE))
#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
(ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE))
#define ROMLIB_RO_BASE BL1_RO_LIMIT
#define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE)
#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
#define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)
/******************************************************************************* /*******************************************************************************
* BL2 specific defines. * BL2 specific defines.
......
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