Merge pull request #1587 from antonio-nino-diaz-arm/an/deprecated

Remove deprecated interfaces for all platforms

drivers/arm/gic/v2/gicv2_private.h

@@ -15,14 +15,6 @@
  * Private function prototypes
  ******************************************************************************/
 void gicv2_spis_configure_defaults(uintptr_t gicd_base);
-#if !ERROR_DEPRECATED
-void gicv2_secure_spis_configure(uintptr_t gicd_base,
-				     unsigned int num_ints,
-				     const unsigned int *sec_intr_list);
-void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base,
-					unsigned int num_ints,
-					const unsigned int *sec_intr_list);
-#endif
 void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
 		const interrupt_prop_t *interrupt_props,
 		unsigned int interrupt_props_num);

drivers/arm/gic/v3/gicv3_helpers.c

@@ -377,56 +377,6 @@ void gicv3_spis_config_defaults(uintptr_t gicd_base)
 		gicd_write_icfgr(gicd_base, index, 0U);
 }
 
-#if !ERROR_DEPRECATED
-/*******************************************************************************
- * Helper function to configure secure G0 and G1S SPIs.
- ******************************************************************************/
-void gicv3_secure_spis_config(uintptr_t gicd_base,
-				     unsigned int num_ints,
-				     const unsigned int *sec_intr_list,
-				     unsigned int int_grp)
-{
-	unsigned int index, irq_num;
-	unsigned long long gic_affinity_val;
-
-	assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
-	/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
-	if (num_ints != 0U)
-		assert(sec_intr_list != NULL);
-
-	for (index = 0U; index < num_ints; index++) {
-		irq_num = sec_intr_list[index];
-		if (irq_num >= MIN_SPI_ID) {
-
-			/* Configure this interrupt as a secure interrupt */
-			gicd_clr_igroupr(gicd_base, irq_num);
-
-			/* Configure this interrupt as G0 or a G1S interrupt */
-			if (int_grp == INTR_GROUP1S)
-				gicd_set_igrpmodr(gicd_base, irq_num);
-			else
-				gicd_clr_igrpmodr(gicd_base, irq_num);
-
-			/* Set the priority of this interrupt */
-			gicd_set_ipriorityr(gicd_base,
-					      irq_num,
-					      GIC_HIGHEST_SEC_PRIORITY);
-
-			/* Target SPIs to the primary CPU */
-			gic_affinity_val =
-				gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
-			gicd_write_irouter(gicd_base,
-					   irq_num,
-					   gic_affinity_val);
-
-			/* Enable this interrupt */
-			gicd_set_isenabler(gicd_base, irq_num);
-		}
-	}
-
-}
-#endif
-
 /*******************************************************************************
  * Helper function to configure properties of secure SPIs
  ******************************************************************************/
@@ -512,47 +462,6 @@ void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)
 	gicr_write_icfgr1(gicr_base, 0U);
 }
 
-#if !ERROR_DEPRECATED
-/*******************************************************************************
- * Helper function to configure secure G0 and G1S SPIs.
- ******************************************************************************/
-void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
-					unsigned int num_ints,
-					const unsigned int *sec_intr_list,
-					unsigned int int_grp)
-{
-	unsigned int index, irq_num;
-
-	assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
-	/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
-	if (num_ints != 0U)
-		assert(sec_intr_list != NULL);
-
-	for (index = 0; index < num_ints; index++) {
-		irq_num = sec_intr_list[index];
-		if (irq_num < MIN_SPI_ID) {
-
-			/* Configure this interrupt as a secure interrupt */
-			gicr_clr_igroupr0(gicr_base, irq_num);
-
-			/* Configure this interrupt as G0 or a G1S interrupt */
-			if (int_grp == INTR_GROUP1S)
-				gicr_set_igrpmodr0(gicr_base, irq_num);
-			else
-				gicr_clr_igrpmodr0(gicr_base, irq_num);
-
-			/* Set the priority of this interrupt */
-			gicr_set_ipriorityr(gicr_base,
-					    irq_num,
-					    GIC_HIGHEST_SEC_PRIORITY);
-
-			/* Enable this interrupt */
-			gicr_set_isenabler0(gicr_base, irq_num);
-		}
-	}
-}
-#endif
-
 /*******************************************************************************
  * Helper function to configure properties of secure G0 and G1S PPIs and SGIs.
  ******************************************************************************/

drivers/arm/gic/v3/gicv3_main.c

@@ -67,45 +67,8 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
 
 	assert(IS_IN_EL3());
 
-#if !ERROR_DEPRECATED
-	if (plat_driver_data->interrupt_props == NULL) {
-		/* Interrupt properties array size must be 0 */
-		assert(plat_driver_data->interrupt_props_num == 0);
-
-		/*
-		 * Suppress deprecated declaration warnings in compatibility
-		 * function
-		 */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
-		/*
-		 * The platform should provide a list of at least one type of
-		 * interrupt.
-		 */
-		assert(plat_driver_data->g0_interrupt_array ||
-				plat_driver_data->g1s_interrupt_array);
-
-		/*
-		 * If there are no interrupts of a particular type, then the
-		 * number of interrupts of that type should be 0 and vice-versa.
-		 */
-		assert(plat_driver_data->g0_interrupt_array ?
-				plat_driver_data->g0_interrupt_num :
-				plat_driver_data->g0_interrupt_num == 0);
-		assert(plat_driver_data->g1s_interrupt_array ?
-				plat_driver_data->g1s_interrupt_num :
-				plat_driver_data->g1s_interrupt_num == 0);
-#pragma GCC diagnostic pop
-
-		WARN("Using deprecated integer interrupt arrays in "
-		     "gicv3_driver_data_t\n");
-		WARN("Please migrate to using interrupt_prop_t arrays\n");
-	}
-#else
 	assert(plat_driver_data->interrupt_props_num > 0 ?
 	       plat_driver_data->interrupt_props != NULL : 1);
-#endif
 
 	/* Check for system register support */
 #ifdef AARCH32
@@ -193,45 +156,10 @@ void gicv3_distif_init(void)
 	/* Set the default attribute of all SPIs */
 	gicv3_spis_config_defaults(gicv3_driver_data->gicd_base);
 
-#if !ERROR_DEPRECATED
-	if (gicv3_driver_data->interrupt_props != NULL) {
-#endif
-		bitmap = gicv3_secure_spis_config_props(
-				gicv3_driver_data->gicd_base,
-				gicv3_driver_data->interrupt_props,
-				gicv3_driver_data->interrupt_props_num);
-#if !ERROR_DEPRECATED
-	} else {
-		/*
-		 * Suppress deprecated declaration warnings in compatibility
-		 * function
-		 */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
-		assert(gicv3_driver_data->g1s_interrupt_array ||
-				gicv3_driver_data->g0_interrupt_array);
-
-		/* Configure the G1S SPIs */
-		if (gicv3_driver_data->g1s_interrupt_array) {
-			gicv3_secure_spis_config(gicv3_driver_data->gicd_base,
-					gicv3_driver_data->g1s_interrupt_num,
-					gicv3_driver_data->g1s_interrupt_array,
-					INTR_GROUP1S);
-			bitmap |= CTLR_ENABLE_G1S_BIT;
-		}
-
-		/* Configure the G0 SPIs */
-		if (gicv3_driver_data->g0_interrupt_array) {
-			gicv3_secure_spis_config(gicv3_driver_data->gicd_base,
-					gicv3_driver_data->g0_interrupt_num,
-					gicv3_driver_data->g0_interrupt_array,
-					INTR_GROUP0);
-			bitmap |= CTLR_ENABLE_G0_BIT;
-		}
-#pragma GCC diagnostic pop
-	}
-#endif
+	bitmap = gicv3_secure_spis_config_props(
+			gicv3_driver_data->gicd_base,
+			gicv3_driver_data->interrupt_props,
+			gicv3_driver_data->interrupt_props_num);
 
 	/* Enable the secure SPIs now that they have been configured */
 	gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
@@ -266,44 +194,9 @@ void gicv3_rdistif_init(unsigned int proc_num)
 	/* Set the default attribute of all SGIs and PPIs */
 	gicv3_ppi_sgi_config_defaults(gicr_base);
 
-#if !ERROR_DEPRECATED
-	if (gicv3_driver_data->interrupt_props != NULL) {
-#endif
-		bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
-				gicv3_driver_data->interrupt_props,
-				gicv3_driver_data->interrupt_props_num);
-#if !ERROR_DEPRECATED
-	} else {
-		/*
-		 * Suppress deprecated declaration warnings in compatibility
-		 * function
-		 */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
-		assert(gicv3_driver_data->g1s_interrupt_array ||
-		       gicv3_driver_data->g0_interrupt_array);
-
-		/* Configure the G1S SGIs/PPIs */
-		if (gicv3_driver_data->g1s_interrupt_array) {
-			gicv3_secure_ppi_sgi_config(gicr_base,
-					gicv3_driver_data->g1s_interrupt_num,
-					gicv3_driver_data->g1s_interrupt_array,
-					INTR_GROUP1S);
-			bitmap |= CTLR_ENABLE_G1S_BIT;
-		}
-
-		/* Configure the G0 SGIs/PPIs */
-		if (gicv3_driver_data->g0_interrupt_array) {
-			gicv3_secure_ppi_sgi_config(gicr_base,
-					gicv3_driver_data->g0_interrupt_num,
-					gicv3_driver_data->g0_interrupt_array,
-					INTR_GROUP0);
-			bitmap |= CTLR_ENABLE_G0_BIT;
-		}
-#pragma GCC diagnostic pop
-	}
-#endif
+	bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
+			gicv3_driver_data->interrupt_props,
+			gicv3_driver_data->interrupt_props_num);
 
 	/* Enable interrupt groups as required, if not already */
 	if ((ctlr & bitmap) != bitmap)

drivers/arm/gic/v3/gicv3_private.h

@@ -95,16 +95,6 @@ void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg);
  ******************************************************************************/
 void gicv3_spis_config_defaults(uintptr_t gicd_base);
 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
-#if !ERROR_DEPRECATED
-void gicv3_secure_spis_config(uintptr_t gicd_base,
-				     unsigned int num_ints,
-				     const unsigned int *sec_intr_list,
-				     unsigned int int_grp);
-void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
-					unsigned int num_ints,
-					const unsigned int *sec_intr_list,
-					unsigned int int_grp);
-#endif
 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
 		const interrupt_prop_t *interrupt_props,
 		unsigned int interrupt_props_num);

drivers/arm/pl011/pl011_console.S

-/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/pl011_console.S"
-#endif

drivers/arm/tzc400/tzc400.c

-/*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if ERROR_DEPRECATED
-#error "Using deprecated TZC-400 source file"
-#else
-#include "../tzc/tzc400.c"
-#endif /* ERROR_DEPRECATED */

drivers/auth/mbedtls/mbedtls_common.mk

@@ -60,16 +60,6 @@ ifeq (${TF_MBEDTLS_KEY_ALG},)
     endif
 endif
 
-# If MBEDTLS_KEY_ALG build flag is defined use it to set TF_MBEDTLS_KEY_ALG for
-# backward compatibility
-ifdef MBEDTLS_KEY_ALG
-    ifeq (${ERROR_DEPRECATED},1)
-        $(error "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
-    endif
-    $(warning "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
-    TF_MBEDTLS_KEY_ALG	:= ${MBEDTLS_KEY_ALG}
-endif
-
 ifeq (${HASH_ALG}, sha384)
     TF_MBEDTLS_HASH_ALG_ID	:=	TF_MBEDTLS_SHA384
 else ifeq (${HASH_ALG}, sha512)

drivers/cadence/uart/aarch64/cdns_console.S

@@ -15,9 +15,11 @@
 	.globl console_cdns_core_init
 	.globl console_cdns_core_putc
 	.globl console_cdns_core_getc
+	.globl console_cdns_core_flush
 
 	.globl  console_cdns_putc
 	.globl  console_cdns_getc
+	.globl  console_cdns_flush
 
 	/* -----------------------------------------------
 	 * int console_cdns_core_init(uintptr_t base_addr)
@@ -87,6 +89,7 @@ endfunc console_cdns_register
 	.equ console_core_init,console_cdns_core_init
 	.equ console_core_putc,console_cdns_core_putc
 	.equ console_core_getc,console_cdns_core_getc
+	.equ console_core_flush,console_cdns_core_flush
 #endif
 
 	/* --------------------------------------------------------
@@ -188,8 +191,7 @@ func console_cdns_getc
 endfunc console_cdns_getc
 
 	/* ---------------------------------------------
-	 * int console_core_flush(uintptr_t base_addr)
-	 * DEPRECATED: Not used with MULTI_CONSOLE_API!
+	 * int console_cdns_core_flush(uintptr_t base_addr)
 	 * Function to force a write of all buffered
 	 * data that hasn't been output.
 	 * In : x0 - console base address
@@ -197,8 +199,30 @@ endfunc console_cdns_getc
 	 * Clobber list : x0, x1
 	 * ---------------------------------------------
 	 */
-func console_core_flush
+func console_cdns_core_flush
+#if ENABLE_ASSERTIONS
+	cmp	x0, #0
+	ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
 	/* Placeholder */
 	mov	w0, #0
 	ret
-endfunc console_core_flush
+endfunc console_cdns_core_flush
+
+	/* ---------------------------------------------
+	 * int console_cdns_flush(console_pl011_t *console)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * In : x0 - pointer to console_t structure
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_cdns_flush
+#if ENABLE_ASSERTIONS
+	cmp	x0, #0
+	ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+	ldr	x0, [x0, #CONSOLE_T_CDNS_BASE]
+	b	console_cdns_core_flush
+endfunc console_cdns_flush

drivers/cadence/uart/cdns_console.S

-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/cdns_console.S"
-#endif

drivers/console/console.S

-/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/console.S"
-#endif

drivers/console/skeleton_console.S

-/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/skeleton_console.S"
-#endif

drivers/ti/uart/16550_console.S

-/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/16550_console.S"
-#endif

include/bl32/sp_min/platform_sp_min.h

@@ -10,10 +10,6 @@
 /*******************************************************************************
  * Mandatory SP_MIN functions
  ******************************************************************************/
-#if !ERROR_DEPRECATED
-void sp_min_early_platform_setup(void *from_bl2,
-		void *plat_params_from_bl2);
-#endif
 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		u_register_t arg2, u_register_t arg3);
 void sp_min_platform_setup(void);

include/common/aarch64/asm_macros.S

@@ -97,36 +97,6 @@
 	.fill	\label + (32 * 4) - .
 	.endm
 
-	/*
-	 * This macro verifies that the given vector doesn't exceed the
-	 * architectural limit of 32 instructions. This is meant to be placed
-	 * immediately after the last instruction in the vector. It takes the
-	 * vector entry as the parameter
-	 */
-	.macro check_vector_size since
-#if ERROR_DEPRECATED
-      .error "check_vector_size must not be used. Use end_vector_entry instead"
-#endif
-	end_vector_entry \since
-	.endm
-
-#if ENABLE_PLAT_COMPAT
-	/*
-	 * This macro calculates the base address of an MP stack using the
-	 * platform_get_core_pos() index, the name of the stack storage and
-	 * the size of each stack
-	 * In: X0 = MPIDR of CPU whose stack is wanted
-	 * Out: X0 = physical address of stack base
-	 * Clobber: X30, X1, X2
-	 */
-	.macro get_mp_stack _name, _size
-	bl  platform_get_core_pos
-	ldr x2, =(\_name + \_size)
-	mov x1, #\_size
-	madd x0, x0, x1, x2
-	.endm
-#endif
-
 	/*
 	 * This macro calculates the base address of the current CPU's MP stack
 	 * using the plat_my_core_pos() index, the name of the stack storage

include/common/bl_common.h

@@ -107,10 +107,6 @@ IMPORT_SYM(unsigned long, __COHERENT_RAM_END__,		BL_COHERENT_RAM_END);
 typedef struct meminfo {
 	uintptr_t total_base;
 	size_t total_size;
-#if !LOAD_IMAGE_V2
-	uintptr_t free_base;
-	size_t free_size;
-#endif
 } meminfo_t;
 
 /*****************************************************************************
@@ -124,9 +120,7 @@ typedef struct image_info {
 	param_header_t h;
 	uintptr_t image_base;   /* physical address of base of image */
 	uint32_t image_size;    /* bytes read from image file */
-#if LOAD_IMAGE_V2
 	uint32_t image_max_size;
-#endif
 } image_info_t;
 
 /*****************************************************************************
@@ -145,7 +139,6 @@ typedef struct image_desc {
 	entry_point_info_t ep_info;
 } image_desc_t;
 
-#if LOAD_IMAGE_V2
 /* BL image node in the BL image loading sequence */
 typedef struct bl_load_info_node {
 	unsigned int image_id;
@@ -176,33 +169,6 @@ typedef struct bl_params {
 	bl_params_node_t *head;
 } bl_params_t;
 
-#else /* LOAD_IMAGE_V2 */
-
-/*******************************************************************************
- * This structure represents the superset of information that can be passed to
- * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
- * populated only if BL2 detects its presence. A pointer to a structure of this
- * type should be passed in X0 to BL31's cold boot entrypoint.
- *
- * Use of this structure and the X0 parameter is not mandatory: the BL31
- * platform code can use other mechanisms to provide the necessary information
- * about BL32 and BL33 to the common and SPD code.
- *
- * BL31 image information is mandatory if this structure is used. If either of
- * the optional BL32 and BL33 image information is not provided, this is
- * indicated by the respective image_info pointers being zero.
- ******************************************************************************/
-typedef struct bl31_params {
-	param_header_t h;
-	image_info_t *bl31_image_info;
-	entry_point_info_t *bl32_ep_info;
-	image_info_t *bl32_image_info;
-	entry_point_info_t *bl33_ep_info;
-	image_info_t *bl33_image_info;
-} bl31_params_t;
-
-#endif /* LOAD_IMAGE_V2 */
-
 /*******************************************************************************
  * Function & variable prototypes
  ******************************************************************************/
@@ -211,27 +177,8 @@ size_t get_image_size(unsigned int image_id);
 int is_mem_free(uintptr_t free_base, size_t free_size,
 		uintptr_t addr, size_t size);
 
-#if LOAD_IMAGE_V2
-
 int load_auth_image(unsigned int image_id, image_info_t *image_data);
 
-#else
-
-int load_image(meminfo_t *mem_layout,
-	       unsigned int image_id,
-	       uintptr_t image_base,
-	       image_info_t *image_data,
-	       entry_point_info_t *entry_point_info);
-int load_auth_image(meminfo_t *mem_layout,
-		    unsigned int image_id,
-		    uintptr_t image_base,
-		    image_info_t *image_data,
-		    entry_point_info_t *entry_point_info);
-void reserve_mem(uintptr_t *free_base, size_t *free_size,
-		uintptr_t addr, size_t size);
-
-#endif /* LOAD_IMAGE_V2 */
-
 #if TRUSTED_BOARD_BOOT && defined(DYN_DISABLE_AUTH)
 /*
  * API to dynamically disable authentication. Only meant for development

include/common/desc_image_load.h

@@ -8,7 +8,6 @@
 
 #include <bl_common.h>
 
-#if LOAD_IMAGE_V2
 /* Following structure is used to store BL ep/image info. */
 typedef struct bl_mem_params_node {
 	unsigned int image_id;
@@ -38,5 +37,4 @@ bl_load_info_t *get_bl_load_info_from_mem_params_desc(void);
 bl_params_t *get_next_bl_params_from_mem_params_desc(void);
 void populate_next_bl_params_config(bl_params_t *bl2_to_next_bl_params);
 
-#endif /* LOAD_IMAGE_V2 */
 #endif /* __DESC_IMAGE_LOAD_H__ */

include/drivers/arm/arm_gic.h

-/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __ARM_GIC_H__
-#define __ARM_GIC_H__
-
-#include <cdefs.h>
-#include <stdint.h>
-
-/*******************************************************************************
- * Function declarations
- ******************************************************************************/
-void arm_gic_init(uintptr_t gicc_base,
-		  uintptr_t gicd_base,
-		  uintptr_t gicr_base,
-		  const unsigned int *irq_sec_ptr,
-		  unsigned int num_irqs) __deprecated;
-void arm_gic_setup(void) __deprecated;
-void arm_gic_cpuif_deactivate(void) __deprecated;
-void arm_gic_cpuif_setup(void) __deprecated;
-void arm_gic_pcpu_distif_setup(void) __deprecated;
-
-uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
-				uint32_t security_state) __deprecated;
-uint32_t arm_gic_get_pending_interrupt_type(void) __deprecated;
-uint32_t arm_gic_get_pending_interrupt_id(void) __deprecated;
-uint32_t arm_gic_acknowledge_interrupt(void) __deprecated;
-void arm_gic_end_of_interrupt(uint32_t id) __deprecated;
-uint32_t arm_gic_get_interrupt_type(uint32_t id) __deprecated;
-
-#endif /* __GIC_H__ */

include/drivers/arm/cci400.h

-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __CCI_400_H__
-#define __CCI_400_H__
-
-/**************************************************************
- * THIS DRIVER IS DEPRECATED. Please use the driver in cci.h
- **************************************************************/
-#if ERROR_DEPRECATED
-#error " The CCI-400 specific driver is deprecated."
-#endif
-
-
-/* Slave interface offsets from PERIPHBASE */
-#define SLAVE_IFACE4_OFFSET		0x5000
-#define SLAVE_IFACE3_OFFSET		0x4000
-#define SLAVE_IFACE2_OFFSET		0x3000
-#define SLAVE_IFACE1_OFFSET		0x2000
-#define SLAVE_IFACE0_OFFSET		0x1000
-#define SLAVE_IFACE_OFFSET(index)	SLAVE_IFACE0_OFFSET +	\
-					(0x1000 * (index))
-
-/* Control and ID register offsets */
-#define CTRL_OVERRIDE_REG		0x0
-#define SPEC_CTRL_REG			0x4
-#define SECURE_ACCESS_REG		0x8
-#define STATUS_REG			0xc
-#define IMPRECISE_ERR_REG		0x10
-#define PERFMON_CTRL_REG		0x100
-
-/* Slave interface register offsets */
-#define SNOOP_CTRL_REG			0x0
-#define SH_OVERRIDE_REG			0x4
-#define READ_CHNL_QOS_VAL_OVERRIDE_REG	0x100
-#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG	0x104
-#define QOS_CTRL_REG			0x10c
-#define MAX_OT_REG			0x110
-#define TARGET_LATENCY_REG		0x130
-#define LATENCY_REGULATION_REG		0x134
-#define QOS_RANGE_REG			0x138
-
-/* Snoop Control register bit definitions */
-#define DVM_EN_BIT			(1 << 1)
-#define SNOOP_EN_BIT			(1 << 0)
-
-/* Status register bit definitions */
-#define CHANGE_PENDING_BIT		(1 << 0)
-
-#ifndef __ASSEMBLY__
-
-#include <stdint.h>
-
-/* Function declarations */
-
-/*
- * The CCI-400 driver must be initialized with the base address of the
- * CCI-400 device in the platform memory map, and the cluster indices for
- * the CCI-400 slave interfaces 3 and 4 respectively. These are the fully
- * coherent ACE slave interfaces of CCI-400.
- * The cluster indices must either be 0 or 1, corresponding to the level 1
- * affinity instance of the mpidr representing the cluster. A negative cluster
- * index indicates that no cluster is present on that slave interface.
- */
-void cci_init(uintptr_t cci_base,
-		int slave_iface3_cluster_ix,
-		int slave_iface4_cluster_ix) __deprecated;
-
-void cci_enable_cluster_coherency(unsigned long mpidr) __deprecated;
-void cci_disable_cluster_coherency(unsigned long mpidr) __deprecated;
-
-#endif /* __ASSEMBLY__ */
-#endif /* __CCI_400_H__ */

include/drivers/arm/gic_v2.h

-/*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __GIC_V2_H__
-#define __GIC_V2_H__
-
-/* The macros required here are additional to those in gic_common.h. */
-#include <gic_common.h>
-
-/******************************************************************************
- * THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h
- * and for GICv3 systems, use the driver in gicv3.h.
- *****************************************************************************/
-#if ERROR_DEPRECATED
-#error " The legacy ARM GIC driver is deprecated."
-#endif
-
-#define GIC400_NUM_SPIS		U(480)
-#define MAX_PPIS		U(14)
-#define MAX_SGIS		U(16)
-
-
-#define GRP0			U(0)
-#define GRP1			U(1)
-#define GIC_TARGET_CPU_MASK	U(0xff)
-
-#define ENABLE_GRP0		(U(1) << 0)
-#define ENABLE_GRP1		(U(1) << 1)
-
-/* Distributor interface definitions */
-#define GICD_ITARGETSR		U(0x800)
-#define GICD_SGIR		U(0xF00)
-#define GICD_CPENDSGIR		U(0xF10)
-#define GICD_SPENDSGIR		U(0xF20)
-
-#define CPENDSGIR_SHIFT		U(2)
-#define SPENDSGIR_SHIFT		CPENDSGIR_SHIFT
-
-/* GICD_TYPER bit definitions */
-#define IT_LINES_NO_MASK	U(0x1f)
-
-/* Physical CPU Interface registers */
-#define GICC_CTLR		U(0x0)
-#define GICC_PMR		U(0x4)
-#define GICC_BPR		U(0x8)
-#define GICC_IAR		U(0xC)
-#define GICC_EOIR		U(0x10)
-#define GICC_RPR		U(0x14)
-#define GICC_HPPIR		U(0x18)
-#define GICC_AHPPIR		U(0x28)
-#define GICC_IIDR		U(0xFC)
-#define GICC_DIR		U(0x1000)
-#define GICC_PRIODROP           GICC_EOIR
-
-/* Common CPU Interface definitions */
-#define INT_ID_MASK		U(0x3ff)
-
-/* GICC_CTLR bit definitions */
-#define EOI_MODE_NS		(U(1) << 10)
-#define EOI_MODE_S		(U(1) << 9)
-#define IRQ_BYP_DIS_GRP1	(U(1) << 8)
-#define FIQ_BYP_DIS_GRP1	(U(1) << 7)
-#define IRQ_BYP_DIS_GRP0	(U(1) << 6)
-#define FIQ_BYP_DIS_GRP0	(U(1) << 5)
-#define CBPR			(U(1) << 4)
-#define FIQ_EN			(U(1) << 3)
-#define ACK_CTL			(U(1) << 2)
-
-/* GICC_IIDR bit masks and shifts */
-#define GICC_IIDR_PID_SHIFT	U(20)
-#define GICC_IIDR_ARCH_SHIFT	U(16)
-#define GICC_IIDR_REV_SHIFT	U(12)
-#define GICC_IIDR_IMP_SHIFT	U(0)
-
-#define GICC_IIDR_PID_MASK	U(0xfff)
-#define GICC_IIDR_ARCH_MASK	U(0xf)
-#define GICC_IIDR_REV_MASK	U(0xf)
-#define GICC_IIDR_IMP_MASK	U(0xfff)
-
-/* HYP view virtual CPU Interface registers */
-#define GICH_CTL		U(0x0)
-#define GICH_VTR		U(0x4)
-#define GICH_ELRSR0		U(0x30)
-#define GICH_ELRSR1		U(0x34)
-#define GICH_APR0		U(0xF0)
-#define GICH_LR_BASE		U(0x100)
-
-/* Virtual CPU Interface registers */
-#define GICV_CTL		U(0x0)
-#define GICV_PRIMASK		U(0x4)
-#define GICV_BP			U(0x8)
-#define GICV_INTACK		U(0xC)
-#define GICV_EOI		U(0x10)
-#define GICV_RUNNINGPRI		U(0x14)
-#define GICV_HIGHESTPEND	U(0x18)
-#define GICV_DEACTIVATE		U(0x1000)
-
-#ifndef __ASSEMBLY__
-
-#include <mmio.h>
-#include <stdint.h>
-
-/*******************************************************************************
- * GIC Distributor function prototypes
- ******************************************************************************/
-
-unsigned int gicd_read_igroupr(uintptr_t, unsigned int);
-unsigned int gicd_read_isenabler(uintptr_t, unsigned int);
-unsigned int gicd_read_icenabler(uintptr_t, unsigned int);
-unsigned int gicd_read_ispendr(uintptr_t, unsigned int);
-unsigned int gicd_read_icpendr(uintptr_t, unsigned int);
-unsigned int gicd_read_isactiver(uintptr_t, unsigned int);
-unsigned int gicd_read_icactiver(uintptr_t, unsigned int);
-unsigned int gicd_read_ipriorityr(uintptr_t, unsigned int);
-unsigned int gicd_read_itargetsr(uintptr_t, unsigned int);
-unsigned int gicd_read_icfgr(uintptr_t, unsigned int);
-unsigned int gicd_read_cpendsgir(uintptr_t, unsigned int);
-unsigned int gicd_read_spendsgir(uintptr_t, unsigned int);
-void gicd_write_igroupr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_isenabler(uintptr_t, unsigned int, unsigned int);
-void gicd_write_icenabler(uintptr_t, unsigned int, unsigned int);
-void gicd_write_ispendr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_icpendr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_isactiver(uintptr_t, unsigned int, unsigned int);
-void gicd_write_icactiver(uintptr_t, unsigned int, unsigned int);
-void gicd_write_ipriorityr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_itargetsr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_icfgr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_cpendsgir(uintptr_t, unsigned int, unsigned int);
-void gicd_write_spendsgir(uintptr_t, unsigned int, unsigned int);
-unsigned int gicd_get_igroupr(uintptr_t, unsigned int);
-void gicd_set_igroupr(uintptr_t, unsigned int);
-void gicd_clr_igroupr(uintptr_t, unsigned int);
-void gicd_set_isenabler(uintptr_t, unsigned int);
-void gicd_set_icenabler(uintptr_t, unsigned int);
-void gicd_set_ispendr(uintptr_t, unsigned int);
-void gicd_set_icpendr(uintptr_t, unsigned int);
-void gicd_set_isactiver(uintptr_t, unsigned int);
-void gicd_set_icactiver(uintptr_t, unsigned int);
-void gicd_set_ipriorityr(uintptr_t, unsigned int, unsigned int);
-void gicd_set_itargetsr(uintptr_t, unsigned int, unsigned int);
-
-
-/*******************************************************************************
- * GIC Distributor interface accessors for reading entire registers
- ******************************************************************************/
-
-static inline unsigned int gicd_read_ctlr(uintptr_t base)
-{
-	return mmio_read_32(base + GICD_CTLR);
-}
-
-static inline unsigned int gicd_read_typer(uintptr_t base)
-{
-	return mmio_read_32(base + GICD_TYPER);
-}
-
-static inline unsigned int gicd_read_sgir(uintptr_t base)
-{
-	return mmio_read_32(base + GICD_SGIR);
-}
-
-
-/*******************************************************************************
- * GIC Distributor interface accessors for writing entire registers
- ******************************************************************************/
-
-static inline void gicd_write_ctlr(uintptr_t base, unsigned int val)
-{
-	mmio_write_32(base + GICD_CTLR, val);
-}
-
-static inline void gicd_write_sgir(uintptr_t base, unsigned int val)
-{
-	mmio_write_32(base + GICD_SGIR, val);
-}
-
-
-/*******************************************************************************
- * GIC CPU interface accessors for reading entire registers
- ******************************************************************************/
-
-static inline unsigned int gicc_read_ctlr(uintptr_t base)
-{
-	return mmio_read_32(base + GICC_CTLR);
-}
-
-static inline unsigned int gicc_read_pmr(uintptr_t base)
-{
-	return mmio_read_32(base + GICC_PMR);
-}
-
-static inline unsigned int gicc_read_BPR(uintptr_t base)
-{
-	return mmio_read_32(base + GICC_BPR);
-}
-
-static inline unsigned int gicc_read_IAR(uintptr_t base)
-{
-	return mmio_read_32(base + GICC_IAR);
-}
-
-static inline unsigned int gicc_read_EOIR(uintptr_t base)
-{
-	return mmio_read_32(base + GICC_EOIR);
-}
-
-static inline unsigned int gicc_read_hppir(uintptr_t base)
-{
-	return mmio_read_32(base + GICC_HPPIR);
-}
-
-static inline unsigned int gicc_read_ahppir(uintptr_t base)
-{
-	return mmio_read_32(base + GICC_AHPPIR);
-}
-
-static inline unsigned int gicc_read_dir(uintptr_t base)
-{
-	return mmio_read_32(base + GICC_DIR);
-}
-
-static inline unsigned int gicc_read_iidr(uintptr_t base)
-{
-	return mmio_read_32(base + GICC_IIDR);
-}
-
-
-/*******************************************************************************
- * GIC CPU interface accessors for writing entire registers
- ******************************************************************************/
-
-static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
-{
-	mmio_write_32(base + GICC_CTLR, val);
-}
-
-static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
-{
-	mmio_write_32(base + GICC_PMR, val);
-}
-
-static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
-{
-	mmio_write_32(base + GICC_BPR, val);
-}
-
-
-static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
-{
-	mmio_write_32(base + GICC_IAR, val);
-}
-
-static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
-{
-	mmio_write_32(base + GICC_EOIR, val);
-}
-
-static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
-{
-	mmio_write_32(base + GICC_HPPIR, val);
-}
-
-static inline void gicc_write_dir(uintptr_t base, unsigned int val)
-{
-	mmio_write_32(base + GICC_DIR, val);
-}
-
-/*******************************************************************************
- * Prototype of function to map an interrupt type to the interrupt line used to
- * signal it.
- ******************************************************************************/
-uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type);
-
-#endif /*__ASSEMBLY__*/
-
-#endif /* __GIC_V2_H__ */

include/drivers/arm/gic_v3.h

-/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __GIC_V3_H__
-#define __GIC_V3_H__
-
-/******************************************************************************
- * THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h
- * and for GICv3 systems, use the driver in gicv3.h.
- *****************************************************************************/
-#if ERROR_DEPRECATED
-#error " The legacy ARM GIC driver is deprecated."
-#endif
-
-#include <mmio.h>
-#include <stdint.h>
-
-/* GICv3 Re-distributor interface registers & shifts */
-#define GICR_PCPUBASE_SHIFT	0x11
-#define GICR_TYPER		0x08
-#define GICR_WAKER		0x14
-
-/* GICR_WAKER bit definitions */
-#define WAKER_CA		(U(1) << 2)
-#define WAKER_PS		(U(1) << 1)
-
-/* GICR_TYPER bit definitions */
-#define GICR_TYPER_AFF_SHIFT	32
-#define GICR_TYPER_AFF_MASK	0xffffffff
-#define GICR_TYPER_LAST		(U(1) << 4)
-
-/* GICv3 ICC_SRE register bit definitions*/
-#define ICC_SRE_EN		(U(1) << 3)
-#define ICC_SRE_SRE		(U(1) << 0)
-
-/*******************************************************************************
- * GICv3 defintions
- ******************************************************************************/
-#define GICV3_AFFLVL_MASK	0xff
-#define GICV3_AFF0_SHIFT	0
-#define GICV3_AFF1_SHIFT	8
-#define GICV3_AFF2_SHIFT	16
-#define GICV3_AFF3_SHIFT	24
-#define GICV3_AFFINITY_MASK	0xffffffff
-
-/*******************************************************************************
- * Function prototypes
- ******************************************************************************/
-uintptr_t gicv3_get_rdist(uintptr_t gicr_base, u_register_t mpidr);
-
-/*******************************************************************************
- * GIC Redistributor interface accessors
- ******************************************************************************/
-static inline uint32_t gicr_read_waker(uintptr_t base)
-{
-	return mmio_read_32(base + GICR_WAKER);
-}
-
-static inline void gicr_write_waker(uintptr_t base, uint32_t val)
-{
-	mmio_write_32(base + GICR_WAKER, val);
-}
-
-static inline uint64_t gicr_read_typer(uintptr_t base)
-{
-	return mmio_read_64(base + GICR_TYPER);
-}
-
-
-#endif /* __GIC_V3_H__ */