Merge pull request #1587 from antonio-nino-diaz-arm/an/deprecated

Remove deprecated interfaces for all platforms

include/drivers/arm/gicv2.h

@@ -7,6 +7,8 @@
 #ifndef __GICV2_H__
 #define __GICV2_H__
 
+#include <gic_common.h>
+
 /*******************************************************************************
  * GICv2 miscellaneous definitions
  ******************************************************************************/
@@ -132,14 +134,6 @@
  * The 'gicc_base' field contains the base address of the CPU Interface
  * programmer's view.
  *
- * The 'g0_interrupt_array' field is a pointer to an array in which each entry
- * corresponds to an ID of a Group 0 interrupt. This field is ignored when
- * 'interrupt_props' field is used. This field is deprecated.
- *
- * The 'g0_interrupt_num' field contains the number of entries in the
- * 'g0_interrupt_array'. This field is ignored when 'interrupt_props' field is
- * used. This field is deprecated.
- *
  * The 'target_masks' is a pointer to an array containing 'target_masks_num'
  * elements. The GIC driver will populate the array with per-PE target mask to
  * use to when targeting interrupts.
@@ -155,10 +149,6 @@
 typedef struct gicv2_driver_data {
 	uintptr_t gicd_base;
 	uintptr_t gicc_base;
-#if !ERROR_DEPRECATED
-	unsigned int g0_interrupt_num __deprecated;
-	const unsigned int *g0_interrupt_array __deprecated;
-#endif
 	unsigned int *target_masks;
 	unsigned int target_masks_num;
 	const interrupt_prop_t *interrupt_props;

include/drivers/arm/gicv3.h

@@ -276,23 +276,6 @@ static inline void gicv3_end_of_interrupt(unsigned int id)
  * The 'gicr_base' field contains the base address of the Re-distributor
  * interface programmer's view.
  *
- * The 'g0_interrupt_array' field is a pointer to an array in which each entry
- * corresponds to an ID of a Group 0 interrupt. This field is ignored when
- * 'interrupt_props' field is used. This field is deprecated.
- *
- * The 'g0_interrupt_num' field contains the number of entries in the
- * 'g0_interrupt_array'. This field is ignored when 'interrupt_props' field is
- * used. This field is deprecated.
- *
- * The 'g1s_interrupt_array' field is a pointer to an array in which each entry
- * corresponds to an ID of a Group 1 interrupt. This field is ignored when
- * 'interrupt_props' field is used. This field is deprecated.
- *
- * The 'g1s_interrupt_num' field contains the number of entries in the
- * 'g1s_interrupt_array'. This field must be 0 if 'interrupt_props' field is
- * used. This field is ignored when 'interrupt_props' field is used. This field
- * is deprecated.
- *
  * The 'interrupt_props' field is a pointer to an array that enumerates secure
  * interrupts and their properties. If this field is not NULL, both
  * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
@@ -326,12 +309,6 @@ typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
 typedef struct gicv3_driver_data {
 	uintptr_t gicd_base;
 	uintptr_t gicr_base;
-#if !ERROR_DEPRECATED
-	unsigned int g0_interrupt_num __deprecated;
-	unsigned int g1s_interrupt_num __deprecated;
-	const unsigned int *g0_interrupt_array __deprecated;
-	const unsigned int *g1s_interrupt_array __deprecated;
-#endif
 	const interrupt_prop_t *interrupt_props;
 	unsigned int interrupt_props_num;
 	unsigned int rdistif_num;

include/drivers/arm/tzc400.h

@@ -85,16 +85,6 @@
 				(TZC_400_REGION_ATTR_F_EN_MASK <<	\
 				TZC_REGION_ATTR_F_EN_SHIFT)
 
-/*
- * Define some macros for backward compatibility with existing tzc400 clients.
- */
-#if !ERROR_DEPRECATED
-#define REG_ATTR_FILTER_BIT(x)			((1 << x)		\
-					<< TZC_REGION_ATTR_F_EN_SHIFT)
-#define REG_ATTR_FILTER_BIT_ALL	(TZC_400_REGION_ATTR_F_EN_MASK <<	\
-					TZC_REGION_ATTR_F_EN_SHIFT)
-#endif /* __ERROR_DEPRECATED__ */
-
 /*
  * All TZC region configuration registers are placed one after another. It
  * depicts size of block of registers for programming each region.
@@ -123,24 +113,6 @@ void tzc400_set_action(tzc_action_t action);
 void tzc400_enable_filters(void);
 void tzc400_disable_filters(void);
 
-/*
- * Deprecated APIs
- */
-static inline void tzc_init(uintptr_t base) __deprecated;
-static inline void tzc_configure_region0(
-			tzc_region_attributes_t sec_attr,
-			unsigned int ns_device_access) __deprecated;
-static inline void tzc_configure_region(
-			  unsigned int filters,
-			  int region,
-			  unsigned long long region_base,
-			  unsigned long long region_top,
-			  tzc_region_attributes_t sec_attr,
-			  unsigned int ns_device_access) __deprecated;
-static inline void tzc_set_action(tzc_action_t action) __deprecated;
-static inline void tzc_enable_filters(void) __deprecated;
-static inline void tzc_disable_filters(void) __deprecated;
-
 static inline void tzc_init(uintptr_t base)
 {
 	tzc400_init(base);

include/drivers/auth/mbedtls/mbedtls_config.h

@@ -30,9 +30,6 @@
 /* Prevent mbed TLS from using snprintf so that it can use tf_snprintf. */
 #define MBEDTLS_PLATFORM_SNPRINTF_ALT
 
-#if !ERROR_DEPRECATED
-#define MBEDTLS_PKCS1_V15
-#endif
 #define MBEDTLS_PKCS1_V21
 
 #define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION

include/lib/aarch32/arch.h

@@ -126,10 +126,6 @@
 #define SDCR_SPD_ENABLE		U(0x3)
 #define SDCR_RESET_VAL		U(0x0)
 
-#if !ERROR_DEPRECATED
-#define SDCR_DEF_VAL		SDCR_SPD(SDCR_SPD_DISABLE)
-#endif
-
 /* HSCTLR definitions */
 #define HSCTLR_RES1 	((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
 			 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
@@ -220,10 +216,6 @@
 #define NSASEDIS_BIT		(U(1) << 15)
 #define NSTRCDIS_BIT		(U(1) << 20)
 /* NOTE: correct typo in the definitions */
-#if !ERROR_DEPRECATED
-#define NASCR_CP11_BIT		(U(1) << 11)
-#define NASCR_CP10_BIT		(U(1) << 10)
-#endif
 #define NSACR_CP11_BIT		(U(1) << 11)
 #define NSACR_CP10_BIT		(U(1) << 10)
 #define NSACR_IMP_DEF_MASK	(U(0x7) << 16)

include/lib/aarch32/smcc_helpers.h

-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SMCC_HELPERS_H__
-#define __SMCC_HELPERS_H__
-
-#if !ERROR_DEPRECATED
-#include <smccc_helpers.h>
-#endif
-
-#endif /* __SMCC_HELPERS_H__ */

include/lib/aarch32/smcc_macros.S

-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef __SMCC_MACROS_S__
-#define __SMCC_MACROS_S__
-
-#if !ERROR_DEPRECATED
-#include <smccc_macros.S>
-
-#define smcc_save_gp_mode_regs smccc_save_gp_mode_regs
-#endif
-
-#endif /* __SMCC_MACROS_S__ */

include/lib/aarch64/arch.h

@@ -245,10 +245,6 @@
 #define MDCR_TPM_BIT		(U(1) << 6)
 #define MDCR_EL3_RESET_VAL	U(0x0)
 
-#if !ERROR_DEPRECATED
-#define MDCR_DEF_VAL		(MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
-#endif
-
 /* MDCR_EL2 definitions */
 #define MDCR_EL2_TPMS		(U(1) << 14)
 #define MDCR_EL2_E2PB(x)	((x) << 12)

include/lib/aarch64/smcc_helpers.h

-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SMCC_HELPERS_H__
-#define __SMCC_HELPERS_H__
-
-#if !ERROR_DEPRECATED
-#include <smccc_helpers.h>
-#endif
-
-#endif /* __SMCC_HELPERS_H__ */

include/lib/cpus/aarch32/cortex_a53.h

@@ -67,16 +67,4 @@
  ******************************************************************************/
 #define CORTEX_A53_L2MERRSR			p15, 3, c15
 
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A53_ACTLR			CORTEX_A53_CPUACTLR
-
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT	CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT
-#define CORTEX_A53_ACTLR_ENDCCASCI		CORTEX_A53_CPUACTLR_ENDCCASCI
-#define CORTEX_A53_ACTLR_DTAH			CORTEX_A53_CPUACTLR_DTAH
-#endif /* !ERROR_DEPRECATED */
-
 #endif /* __CORTEX_A53_H__ */

include/lib/cpus/aarch32/cortex_a57.h

@@ -79,22 +79,4 @@
  ******************************************************************************/
 #define CORTEX_A57_L2MERRSR			p15, 3, c15
 
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A57_ACTLR			CORTEX_A57_CPUACTLR
-
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB	CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE	CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
-#define CORTEX_A57_ACTLR_DIS_OVERREAD		CORTEX_A57_CPUACTLR_DIS_OVERREAD
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA		CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI		CORTEX_A57_CPUACTLR_DCC_AS_DCCI
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH	CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
-#define CORTEX_A57_ACTLR_DIS_STREAMING		CORTEX_A57_CPUACTLR_DIS_STREAMING
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING	CORTEX_A57_CPUACTLR_DIS_L1_STREAMING
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR	CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
-#endif /* !ERROR_DEPRECATED */
-
 #endif /* __CORTEX_A57_H__ */

include/lib/cpus/aarch32/cortex_a72.h

@@ -54,16 +54,4 @@
  ******************************************************************************/
 #define CORTEX_A72_L2MERRSR				p15, 3, c15
 
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A72_ACTLR				CORTEX_A72_CPUACTLR
-
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI			CORTEX_A72_CPUACTLR_DCC_AS_DCCI
-#endif /* !ERROR_DEPRECATED */
-
 #endif /* __CORTEX_A72_H__ */

include/lib/cpus/aarch64/cortex_a53.h

@@ -71,21 +71,4 @@
  ******************************************************************************/
 #define CORTEX_A53_L2MERRSR_EL1				S3_1_C15_C2_3
 
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions
- * so as not to break platforms that continue using them.
- */
-#define CORTEX_A53_ACTLR_EL1			CORTEX_A53_CPUACTLR_EL1
-
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT	CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT
-#define CORTEX_A53_ACTLR_ENDCCASCI		CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
-#define CORTEX_A53_ACTLR_RADIS_SHIFT		CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT
-#define CORTEX_A53_ACTLR_RADIS			CORTEX_A53_CPUACTLR_EL1_RADIS
-#define CORTEX_A53_ACTLR_L1RADIS_SHIFT		CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT
-#define CORTEX_A53_ACTLR_L1RADIS		CORTEX_A53_CPUACTLR_EL1_L1RADIS
-#define CORTEX_A53_ACTLR_DTAH_SHIFT		CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT
-#define CORTEX_A53_ACTLR_DTAH			CORTEX_A53_CPUACTLR_EL1_DTAH
-#endif /* !ERROR_DEPRECATED */
-
 #endif /* __CORTEX_A53_H__ */

include/lib/cpus/aarch64/cortex_a57.h

@@ -81,22 +81,4 @@
  ******************************************************************************/
 #define CORTEX_A57_L2MERRSR_EL1			S3_1_C15_C2_3
 
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A57_ACTLR_EL1			CORTEX_A57_CPUACTLR_EL1
-
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB	CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE	CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
-#define CORTEX_A57_ACTLR_DIS_OVERREAD		CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA		CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI		CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH	CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
-#define CORTEX_A57_ACTLR_DIS_STREAMING		CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING	CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR	CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
-#endif /* !ERROR_DEPRECATED */
-
 #endif /* __CORTEX_A57_H__ */

include/lib/cpus/aarch64/cortex_a72.h

@@ -61,16 +61,4 @@
  ******************************************************************************/
 #define CORTEX_A72_L2MERRSR_EL1				S3_1_C15_C2_3
 
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A72_ACTLR				CORTEX_A72_CPUACTLR_EL1
-
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI			CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI
-#endif /* !ERROR_DEPRECATED */
-
 #endif /* __CORTEX_A72_H__ */

include/lib/el3_runtime/context_mgmt.h

@@ -47,16 +47,6 @@ void cm_write_scr_el3_bit(uint32_t security_state,
 void cm_set_next_eret_context(uint32_t security_state);
 uint32_t cm_get_scr_el3(uint32_t security_state);
 
-
-void cm_init_context(uint64_t mpidr,
-		     const struct entry_point_info *ep) __deprecated;
-
-void *cm_get_context_by_mpidr(uint64_t mpidr,
-			      uint32_t security_state) __deprecated;
-void cm_set_context_by_mpidr(uint64_t mpidr,
-			     void *context,
-			     uint32_t security_state) __deprecated;
-
 /* Inline definitions */
 
 /*******************************************************************************

include/lib/psci/psci.h

@@ -10,9 +10,6 @@
 #include <bakery_lock.h>
 #include <bl_common.h>
 #include <platform_def.h>	/* for PLAT_NUM_PWR_DOMAINS */
-#if ENABLE_PLAT_COMPAT
-#include <psci_compat.h>
-#endif
 #include <psci_lib.h>		/* To maintain compatibility for SPDs */
 #include <utils_def.h>
 
@@ -350,12 +347,6 @@ int psci_features(unsigned int psci_fid);
 void __dead2 psci_power_down_wfi(void);
 void psci_arch_setup(void);
 
-/*
- * The below API is deprecated. This is now replaced by bl31_warmboot_entry in
- * AArch64.
- */
-void psci_entrypoint(void) __deprecated;
-
 #endif /*__ASSEMBLY__*/
 
 #endif /* PSCI_H */

include/lib/psci/psci_compat.h

-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PSCI_COMPAT_H
-#define PSCI_COMPAT_H
-
-#include <arch.h>
-#include <platform_def.h>
-#include <utils_def.h>
-
-#ifndef __ASSEMBLY__
-/*
- * The below declarations are to enable compatibility for the platform ports
- * using the old platform interface and psci helpers.
- */
-#define PLAT_MAX_PWR_LVL	PLATFORM_MAX_AFFLVL
-#define PLAT_NUM_PWR_DOMAINS	PLATFORM_NUM_AFFS
-
-/*******************************************************************************
- * PSCI affinity related constants. An affinity instance could
- * be present or absent physically to cater for asymmetric topologies.
- ******************************************************************************/
-#define PSCI_AFF_ABSENT		0x0
-#define PSCI_AFF_PRESENT	0x1
-
-#define PSCI_STATE_ON		U(0x0)
-#define PSCI_STATE_OFF		U(0x1)
-#define PSCI_STATE_ON_PENDING	U(0x2)
-#define PSCI_STATE_SUSPEND	U(0x3)
-
-/*
- * Using the compatibility platform interfaces means that the local states
- * used in psci_power_state_t need to only convey whether its power down
- * or standby state. The onus is on the platform port to do the right thing
- * including the state coordination in case multiple power down states are
- * involved. Hence if we assume 3 generic states viz, run, standby and
- * power down, we can assign 1 and 2 to standby and power down respectively.
- */
-#define PLAT_MAX_RET_STATE	U(1)
-#define PLAT_MAX_OFF_STATE	U(2)
-
-/*
- * Macro to represent invalid affinity level within PSCI.
- */
-#define PSCI_INVALID_DATA -1
-
-#define psci_get_pstate_afflvl(pstate)		psci_get_pstate_pwrlvl(pstate)
-
-/*
- * This array stores the 'power_state' requests of each CPU during
- * CPU_SUSPEND and SYSTEM_SUSPEND which will be populated by the
- * compatibility layer when appropriate platform hooks are invoked.
- */
-extern unsigned int psci_power_state_compat[PLATFORM_CORE_COUNT];
-
-/*******************************************************************************
- * Structure populated by platform specific code to export routines which
- * perform common low level pm functions
- ******************************************************************************/
-typedef struct plat_pm_ops {
-	void (*affinst_standby)(unsigned int power_state);
-	int (*affinst_on)(unsigned long mpidr,
-			  unsigned long sec_entrypoint,
-			  unsigned int afflvl,
-			  unsigned int state);
-	void (*affinst_off)(unsigned int afflvl, unsigned int state);
-	void (*affinst_suspend)(unsigned long sec_entrypoint,
-			       unsigned int afflvl,
-			       unsigned int state);
-	void (*affinst_on_finish)(unsigned int afflvl, unsigned int state);
-	void (*affinst_suspend_finish)(unsigned int afflvl,
-				      unsigned int state);
-	void (*system_off)(void) __dead2;
-	void (*system_reset)(void) __dead2;
-	int (*validate_power_state)(unsigned int power_state);
-	int (*validate_ns_entrypoint)(unsigned long ns_entrypoint);
-	unsigned int (*get_sys_suspend_power_state)(void);
-} plat_pm_ops_t;
-
-/*******************************************************************************
- * Function & Data prototypes to enable compatibility for older platform ports
- ******************************************************************************/
-int psci_get_suspend_stateid_by_mpidr(unsigned long);
-int psci_get_suspend_stateid(void);
-int psci_get_suspend_powerstate(void);
-unsigned int psci_get_max_phys_off_afflvl(void);
-int psci_get_suspend_afflvl(void);
-
-#endif /* ____ASSEMBLY__ */
-#endif /* PSCI_COMPAT_H */

include/lib/smcc.h

-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SMCC_H__
-#define __SMCC_H__
-
-#if !ERROR_DEPRECATED
-#include <smccc.h>
-#endif
-
-#endif /* __SMCC_H__ */

include/lib/smccc.h

@@ -57,17 +57,6 @@
  * does not equal SMC_UNK. This is to ensure that the caller won't mistake the
  * returned UUID in x0 for an invalid SMC error return
  */
-#if !ERROR_DEPRECATED
-#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \
-		_n0, _n1, _n2, _n3, _n4, _n5) \
-	CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
-	static const uuid_t _name = { \
-		_tl, _tm, _th, _cl, _ch, \
-		{ _n0, _n1, _n2, _n3, _n4, _n5 } \
-	}
-#endif
-
-
 #define DEFINE_SVC_UUID2(_name, _tl, _tm, _th, _cl, _ch,		\
 		_n0, _n1, _n2, _n3, _n4, _n5)				\
 	CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\