Merge pull request #1587 from antonio-nino-diaz-arm/an/deprecated

Remove deprecated interfaces for all platforms

plat/allwinner/sun50i_a64/platform.mk

@@ -42,14 +42,8 @@ ERRATA_A53_835769		:=	1
 ERRATA_A53_843419		:=	1
 ERRATA_A53_855873		:=	1
 
-# Disable the PSCI platform compatibility layer.
-ENABLE_PLAT_COMPAT		:= 	0
-
 MULTI_CONSOLE_API		:=	1
 
-# Prohibit using deprecated interfaces. We rely on this for this platform.
-ERROR_DEPRECATED		:=	1
-
 # The reset vector can be changed for each CPU.
 PROGRAMMABLE_RESET_ADDRESS	:=	1
 

plat/allwinner/sun50i_h6/platform.mk

@@ -44,14 +44,8 @@ ERRATA_A53_835769		:=	1
 ERRATA_A53_843419		:=	1
 ERRATA_A53_855873		:=	1
 
-# Disable the PSCI platform compatibility layer.
-ENABLE_PLAT_COMPAT		:= 	0
-
 MULTI_CONSOLE_API		:=	1
 
-# Prohibit using deprecated interfaces. We rely on this for this platform.
-ERROR_DEPRECATED		:=	1
-
 # The reset vector can be changed for each CPU.
 PROGRAMMABLE_RESET_ADDRESS	:=	1
 

plat/arm/board/fvp/fvp_common.c

@@ -24,7 +24,6 @@
 /* Defines for GIC Driver build time selection */
 #define FVP_GICV2		1
 #define FVP_GICV3		2
-#define FVP_GICV3_LEGACY	3
 
 /*******************************************************************************
  * arm_config holds the characteristics of the differences between the three FVP
@@ -92,9 +91,9 @@ const mmap_region_t plat_arm_mmap[] = {
 #if TRUSTED_BOARD_BOOT
 	/* To access the Root of Trust Public Key registers. */
 	MAP_DEVICE2,
-#if LOAD_IMAGE_V2 && !BL2_AT_EL3
+#if !BL2_AT_EL3
 	ARM_MAP_BL1_RW,
-#endif /* LOAD_IMAGE_V2 && !BL2_AT_EL3 */
+#endif
 #endif /* TRUSTED_BOARD_BOOT */
 #if ENABLE_SPM
 	ARM_SP_IMAGE_MMAP,
@@ -399,7 +398,7 @@ void fvp_interconnect_disable(void)
 #endif
 }
 
-#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2
+#if TRUSTED_BOARD_BOOT
 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
 {
 	assert(heap_addr != NULL);

plat/arm/board/fvp/include/platform_def.h

@@ -145,12 +145,6 @@
  * terminology. On a GICv2 system or mode, the lists will be merged and treated
  * as Group 0 interrupts.
  */
-#define PLAT_ARM_G1S_IRQS		ARM_G1S_IRQS,			\
-					FVP_IRQ_TZ_WDOG,		\
-					FVP_IRQ_SEC_SYS_TIMER
-
-#define PLAT_ARM_G0_IRQS		ARM_G0_IRQS
-
 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \
 	ARM_G1S_IRQ_PROPS(grp), \
 	INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \

plat/arm/board/fvp/platform.mk

@@ -69,19 +69,6 @@ FVP_GIC_SOURCES		:=	drivers/arm/gic/common/gic_common.c	\
 				plat/arm/common/arm_gicv2.c
 
 FVP_DT_PREFIX		:=	fvp-base-gicv2-psci
-
-else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3_LEGACY)
-  ifeq (${ARCH}, aarch32)
-    $(error "GICV3 Legacy driver not supported for AArch32 build")
-  endif
-FVP_GIC_SOURCES		:=	drivers/arm/gic/arm_gic.c		\
-				drivers/arm/gic/gic_v2.c		\
-				drivers/arm/gic/gic_v3.c		\
-				plat/common/plat_gic.c			\
-				plat/arm/common/arm_gicv3_legacy.c
-
-FVP_DT_PREFIX		:=	fvp-base-gicv2-psci
-
 else
 $(error "Incorrect GIC driver chosen on FVP port")
 endif
@@ -208,9 +195,6 @@ $(eval FVP_HW_CONFIG	:=	${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS
 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config))
 endif
 
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT	:= 	0
-
 # Enable Activity Monitor Unit extensions by default
 ENABLE_AMU			:=	1
 
@@ -247,9 +231,7 @@ include plat/arm/board/common/board_common.mk
 include plat/arm/common/arm_common.mk
 
 # FVP being a development platform, enable capability to disable Authentication
-# dynamically if TRUSTED_BOARD_BOOT and LOAD_IMAGE_V2 is set.
+# dynamically if TRUSTED_BOARD_BOOT is set.
 ifeq (${TRUSTED_BOARD_BOOT}, 1)
-    ifeq (${LOAD_IMAGE_V2}, 1)
         DYN_DISABLE_AUTH	:=	1
-    endif
 endif

plat/arm/board/juno/platform.mk

@@ -115,9 +115,6 @@ ERRATA_A72_859971		:=	0
 # power down sequence
 SKIP_A57_L1_FLUSH_PWR_DWN	:=	 1
 
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT		:= 	0
-
 # Enable memory map related constants optimisation
 ARM_BOARD_OPTIMISE_MEM		:=	1
 

plat/arm/common/arm_bl1_setup.c

@@ -76,16 +76,6 @@ void arm_bl1_early_platform_setup(void)
 	/* Allow BL1 to see the whole Trusted RAM */
 	bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
 	bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
-
-#if !LOAD_IMAGE_V2
-	/* Calculate how much RAM BL1 is using and how much remains free */
-	bl1_tzram_layout.free_base = ARM_BL_RAM_BASE;
-	bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE;
-	reserve_mem(&bl1_tzram_layout.free_base,
-		    &bl1_tzram_layout.free_size,
-		    BL1_RAM_BASE,
-		    BL1_RAM_LIMIT - BL1_RAM_BASE);
-#endif /* LOAD_IMAGE_V2 */
 }
 
 void bl1_early_platform_setup(void)
@@ -155,13 +145,12 @@ void arm_bl1_platform_setup(void)
 {
 	/* Initialise the IO layer and register platform IO devices */
 	plat_arm_io_setup();
-#if LOAD_IMAGE_V2
 	arm_load_tb_fw_config();
 #if TRUSTED_BOARD_BOOT
 	/* Share the Mbed TLS heap info with other images */
 	arm_bl1_set_mbedtls_heap();
 #endif /* TRUSTED_BOARD_BOOT */
-#endif /* LOAD_IMAGE_V2 */
+
 	/*
 	 * Allow access to the System counter timer module and program
 	 * counter frequency for non secure images during FWU

plat/arm/common/arm_bl2_setup.c

@@ -40,138 +40,9 @@ CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
 					bl2_tzram_layout.total_size,	\
 					MT_MEMORY | MT_RW | MT_SECURE)
 
-#if LOAD_IMAGE_V2
 
 #pragma weak arm_bl2_plat_handle_post_image_load
 
-#else /* LOAD_IMAGE_V2 */
-
-/*******************************************************************************
- * This structure represents the superset of information that is passed to
- * BL31, e.g. while passing control to it from BL2, bl31_params
- * and other platform specific params
- ******************************************************************************/
-typedef struct bl2_to_bl31_params_mem {
-	bl31_params_t bl31_params;
-	image_info_t bl31_image_info;
-	image_info_t bl32_image_info;
-	image_info_t bl33_image_info;
-	entry_point_info_t bl33_ep_info;
-	entry_point_info_t bl32_ep_info;
-	entry_point_info_t bl31_ep_info;
-} bl2_to_bl31_params_mem_t;
-
-
-static bl2_to_bl31_params_mem_t bl31_params_mem;
-
-
-/* Weak definitions may be overridden in specific ARM standard platform */
-#pragma weak bl2_plat_get_bl31_params
-#pragma weak bl2_plat_get_bl31_ep_info
-#pragma weak bl2_plat_flush_bl31_params
-#pragma weak bl2_plat_set_bl31_ep_info
-#pragma weak bl2_plat_get_scp_bl2_meminfo
-#pragma weak bl2_plat_get_bl32_meminfo
-#pragma weak bl2_plat_set_bl32_ep_info
-#pragma weak bl2_plat_get_bl33_meminfo
-#pragma weak bl2_plat_set_bl33_ep_info
-
-#if ARM_BL31_IN_DRAM
-meminfo_t *bl2_plat_sec_mem_layout(void)
-{
-	static meminfo_t bl2_dram_layout
-		__aligned(CACHE_WRITEBACK_GRANULE) = {
-		.total_base = BL31_BASE,
-		.total_size = (ARM_AP_TZC_DRAM1_BASE +
-				ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE,
-		.free_base = BL31_BASE,
-		.free_size = (ARM_AP_TZC_DRAM1_BASE +
-				ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE
-	};
-
-	return &bl2_dram_layout;
-}
-#else
-meminfo_t *bl2_plat_sec_mem_layout(void)
-{
-	return &bl2_tzram_layout;
-}
-#endif /* ARM_BL31_IN_DRAM */
-
-/*******************************************************************************
- * This function assigns a pointer to the memory that the platform has kept
- * aside to pass platform specific and trusted firmware related information
- * to BL31. This memory is allocated by allocating memory to
- * bl2_to_bl31_params_mem_t structure which is a superset of all the
- * structure whose information is passed to BL31
- * NOTE: This function should be called only once and should be done
- * before generating params to BL31
- ******************************************************************************/
-bl31_params_t *bl2_plat_get_bl31_params(void)
-{
-	bl31_params_t *bl2_to_bl31_params;
-
-	/*
-	 * Initialise the memory for all the arguments that needs to
-	 * be passed to BL31
-	 */
-	zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
-
-	/* Assign memory for TF related information */
-	bl2_to_bl31_params = &bl31_params_mem.bl31_params;
-	SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
-
-	/* Fill BL31 related information */
-	bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
-		VERSION_1, 0);
-
-	/* Fill BL32 related information if it exists */
-#ifdef BL32_BASE
-	bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
-		VERSION_1, 0);
-	bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
-		VERSION_1, 0);
-#endif /* BL32_BASE */
-
-	/* Fill BL33 related information */
-	bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
-		PARAM_EP, VERSION_1, 0);
-
-	/* BL33 expects to receive the primary CPU MPID (through x0) */
-	bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
-
-	bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
-		VERSION_1, 0);
-
-	return bl2_to_bl31_params;
-}
-
-/* Flush the TF params and the TF plat params */
-void bl2_plat_flush_bl31_params(void)
-{
-	flush_dcache_range((unsigned long)&bl31_params_mem,
-			sizeof(bl2_to_bl31_params_mem_t));
-}
-
-/*******************************************************************************
- * This function returns a pointer to the shared memory that the platform
- * has kept to point to entry point information of BL31 to BL2
- ******************************************************************************/
-struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
-{
-#if DEBUG
-	bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL;
-#endif
-
-	return &bl31_params_mem.bl31_ep_info;
-}
-#endif /* LOAD_IMAGE_V2 */
-
 /*******************************************************************************
  * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
  * in x0. This memory layout is sitting at the base of the free trusted SRAM.
@@ -189,10 +60,8 @@ void arm_bl2_early_platform_setup(uintptr_t tb_fw_config,
 	/* Initialise the IO layer and register platform IO devices */
 	plat_arm_io_setup();
 
-#if LOAD_IMAGE_V2
 	if (tb_fw_config != 0U)
 		arm_bl2_set_tb_cfg_addr((void *)tb_fw_config);
-#endif
 }
 
 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
@@ -208,9 +77,7 @@ void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_
  */
 void bl2_plat_preload_setup(void)
 {
-#if LOAD_IMAGE_V2
 	arm_bl2_dyn_cfg_init();
-#endif
 }
 
 /*
@@ -274,7 +141,6 @@ void bl2_plat_arch_setup(void)
 	arm_bl2_plat_arch_setup();
 }
 
-#if LOAD_IMAGE_V2
 int arm_bl2_handle_post_image_load(unsigned int image_id)
 {
 	int err = 0;
@@ -342,86 +208,3 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
 {
 	return arm_bl2_plat_handle_post_image_load(image_id);
 }
-
-#else /* LOAD_IMAGE_V2 */
-
-/*******************************************************************************
- * Populate the extents of memory available for loading SCP_BL2 (if used),
- * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
- ******************************************************************************/
-void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
-{
-	*scp_bl2_meminfo = bl2_tzram_layout;
-}
-
-/*******************************************************************************
- * Before calling this function BL31 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL31 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
-					entry_point_info_t *bl31_ep_info)
-{
-	SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
-	bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-					DISABLE_ALL_EXCEPTIONS);
-}
-
-
-/*******************************************************************************
- * Before calling this function BL32 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL32 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-#ifdef BL32_BASE
-void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
-					entry_point_info_t *bl32_ep_info)
-{
-	SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
-	bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry();
-}
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL32
- ******************************************************************************/
-void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
-{
-	/*
-	 * Populate the extents of memory available for loading BL32.
-	 */
-	bl32_meminfo->total_base = BL32_BASE;
-	bl32_meminfo->free_base = BL32_BASE;
-	bl32_meminfo->total_size =
-			(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
-	bl32_meminfo->free_size =
-			(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
-}
-#endif /* BL32_BASE */
-
-/*******************************************************************************
- * Before calling this function BL33 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL33 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl33_ep_info(image_info_t *image,
-					entry_point_info_t *bl33_ep_info)
-{
-	SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
-	bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry();
-}
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL33
- ******************************************************************************/
-void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
-{
-	bl33_meminfo->total_base = ARM_NS_DRAM1_BASE;
-	bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE;
-	bl33_meminfo->free_base = ARM_NS_DRAM1_BASE;
-	bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE;
-}
-
-#endif /* LOAD_IMAGE_V2 */

plat/arm/common/arm_bl31_setup.c

@@ -71,13 +71,8 @@ struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
  * while creating page tables. BL2 has flushed this information to memory, so
  * we are guaranteed to pick up good data.
  ******************************************************************************/
-#if LOAD_IMAGE_V2
 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
 				uintptr_t hw_config, void *plat_params_from_bl2)
-#else
-void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_config,
-				uintptr_t hw_config, void *plat_params_from_bl2)
-#endif
 {
 	/* Initialize the console to provide early debug support */
 	arm_console_boot_init();
@@ -135,7 +130,6 @@ void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_con
 	assert(((unsigned long long)plat_params_from_bl2) ==
 		ARM_BL31_PLAT_PARAM_VAL);
 
-# if LOAD_IMAGE_V2
 	/*
 	 * Check params passed from BL2 should not be NULL,
 	 */
@@ -162,29 +156,6 @@ void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_con
 
 	if (bl33_image_ep_info.pc == 0U)
 		panic();
-
-# else /* LOAD_IMAGE_V2 */
-
-	/*
-	 * Check params passed from BL2 should not be NULL,
-	 */
-	assert(from_bl2 != NULL);
-	assert(from_bl2->h.type == PARAM_BL31);
-	assert(from_bl2->h.version >= VERSION_1);
-
-	/* Dynamic Config is not supported for LOAD_IMAGE_V1 */
-	assert(soc_fw_config == 0U);
-	assert(hw_config == 0U);
-
-	/*
-	 * Copy BL32 (if populated by BL2) and BL33 entry point information.
-	 * They are stored in Secure RAM, in BL2's address space.
-	 */
-	if (from_bl2->bl32_ep_info)
-		bl32_image_ep_info = *from_bl2->bl32_ep_info;
-	bl33_image_ep_info = *from_bl2->bl33_ep_info;
-
-# endif /* LOAD_IMAGE_V2 */
 #endif /* RESET_TO_BL31 */
 }
 

plat/arm/common/arm_common.c

@@ -21,9 +21,7 @@
 
 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
  * conflicts with the definition in plat/common. */
-#if ERROR_DEPRECATED
 #pragma weak plat_get_syscnt_freq2
-#endif
 
 
 void arm_setup_romlib(void)

plat/arm/common/arm_common.mk

@@ -122,17 +122,11 @@ ENABLE_PMF			:=	1
 # mapping the former as executable and the latter as execute-never.
 SEPARATE_CODE_AND_RODATA	:=	1
 
-# Enable new version of image loading on ARM platforms
-LOAD_IMAGE_V2			:=	1
-
 # Use the multi console API, which is only available for AArch64 for now
 ifeq (${ARCH}, aarch64)
   MULTI_CONSOLE_API		:=	1
 endif
 
-# Use generic OID definition (tbbr_oid.h)
-USE_TBBR_DEFS			:=	1
-
 # Disable ARM Cryptocell by default
 ARM_CRYPTOCELL_INTEG		:=	0
 $(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
@@ -202,7 +196,6 @@ ifeq (${BL2_AT_EL3},1)
 BL2_SOURCES		+=	plat/arm/common/arm_bl2_el3_setup.c
 endif
 
-ifeq (${LOAD_IMAGE_V2},1)
 # Because BL1/BL2 execute in AArch64 mode but BL32 in AArch32 we need to use
 # the AArch32 descriptors.
 ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
@@ -215,7 +208,6 @@ BL2_SOURCES		+=	plat/arm/common/arm_image_load.c		\
 ifeq (${SPD},opteed)
 BL2_SOURCES		+=	lib/optee/optee_utils.c
 endif
-endif
 
 BL2U_SOURCES		+=	drivers/delay_timer/delay_timer.c		\
 				drivers/delay_timer/generic_delay_timer.c	\

plat/arm/common/arm_dyn_cfg.c

@@ -17,9 +17,8 @@
 #include <string.h>
 #include <tbbr_img_def.h>
 
-#if LOAD_IMAGE_V2
 
-/* Variable to store the address of TB_FW_CONFIG file */
+/* Variable to store the address to TB_FW_CONFIG passed from BL1 */
 static void *tb_fw_cfg_dtb;
 static size_t tb_fw_cfg_dtb_size;
 
@@ -39,9 +38,7 @@ static size_t mbedtls_heap_size;
  *   - To allocate space for the Mbed TLS heap --only if-- Trusted Board Boot
  *     is enabled.
  *   - This implementation requires the DTB to be present so that BL1 has a
- *     mechanism to pass the pointer to BL2. If LOAD_IMAGE_V2=0 then
- *     TB_FW_CONFIG is not present, which means that this implementation
- *     cannot be applied.
+ *     mechanism to pass the pointer to BL2.
  */
 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
 {
@@ -283,5 +280,3 @@ void arm_bl2_dyn_cfg_init(void)
 		dyn_disable_auth();
 #endif
 }
-
-#endif /* LOAD_IMAGE_V2 */

plat/arm/common/arm_gicv3_legacy.c

-/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arm_def.h>
-#include <arm_gic.h>
-#include <plat_arm.h>
-#include <platform.h>
-#include <platform_def.h>
-
-/******************************************************************************
- * The following function is defined as weak to allow a platform to override
- * the way the Legacy GICv3 driver is initialised and used.
- *****************************************************************************/
-#pragma weak plat_arm_gic_driver_init
-#pragma weak plat_arm_gic_init
-#pragma weak plat_arm_gic_cpuif_enable
-#pragma weak plat_arm_gic_cpuif_disable
-#pragma weak plat_arm_gic_pcpu_init
-
-/*
- * In the GICv3 Legacy mode, the Group 1 secure interrupts are treated as Group
- * 0 interrupts.
- */
-static const unsigned int irq_sec_array[] = {
-	PLAT_ARM_G0_IRQS,
-	PLAT_ARM_G1S_IRQS
-};
-
-void plat_arm_gic_driver_init(void)
-{
-	arm_gic_init(PLAT_ARM_GICC_BASE,
-		     PLAT_ARM_GICD_BASE,
-		     PLAT_ARM_GICR_BASE,
-		     irq_sec_array,
-		     ARRAY_SIZE(irq_sec_array));
-}
-
-/******************************************************************************
- * ARM common helper to initialize the GIC.
- *****************************************************************************/
-void plat_arm_gic_init(void)
-{
-	arm_gic_setup();
-}
-
-/******************************************************************************
- * ARM common helper to enable the GIC CPU interface
- *****************************************************************************/
-void plat_arm_gic_cpuif_enable(void)
-{
-	arm_gic_cpuif_setup();
-}
-
-/******************************************************************************
- * ARM common helper to disable the GIC CPU interface
- *****************************************************************************/
-void plat_arm_gic_cpuif_disable(void)
-{
-	arm_gic_cpuif_deactivate();
-}
-
-/******************************************************************************
- * ARM common helper to initialize the per-cpu distributor in GICv2 or
- * redistributor interface in GICv3.
- *****************************************************************************/
-void plat_arm_gic_pcpu_init(void)
-{
-	arm_gic_pcpu_distif_setup();
-}
-
-/******************************************************************************
- * Stubs for Redistributor power management. Although legacy configuration isn't
- * supported, these are provided for the sake of uniform GIC API
- *****************************************************************************/
-void plat_arm_gic_redistif_on(void)
-{
-	return;
-}
-
-void plat_arm_gic_redistif_off(void)
-{
-	return;
-}
-
-/******************************************************************************
- * ARM common helper to save & restore the GICv3 on resume from system suspend.
- *****************************************************************************/
-void plat_arm_gic_save(void)
-{
-	return;
-}
-
-void plat_arm_gic_resume(void)
-{
-	arm_gic_setup();
-}

plat/arm/common/arm_pm.c

@@ -6,7 +6,6 @@
 
 #include <arch_helpers.h>
 #include <arm_def.h>
-#include <arm_gic.h>
 #include <assert.h>
 #include <errno.h>
 #include <plat_arm.h>

plat/arm/css/common/css_bl2_setup.c

@@ -14,21 +14,13 @@
 #include "../drivers/scp/css_scp.h"
 
 /* Weak definition may be overridden in specific CSS based platform */
-#if LOAD_IMAGE_V2
 #pragma weak plat_arm_bl2_handle_scp_bl2
-#else
-#pragma weak bl2_plat_handle_scp_bl2
-#endif
 
 /*******************************************************************************
  * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
  * Return 0 on success, -1 otherwise.
  ******************************************************************************/
-#if LOAD_IMAGE_V2
 int plat_arm_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
-#else
-int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
-#endif
 {
 	int ret;
 

plat/arm/css/sgi/include/platform_def.h

@@ -62,11 +62,6 @@
 
 #define PLAT_MAX_PWR_LVL		U(1)
 
-#define PLAT_ARM_G1S_IRQS		ARM_G1S_IRQS,			\
-					CSS_IRQ_MHU
-
-#define PLAT_ARM_G0_IRQS		ARM_G0_IRQS
-
 #define PLAT_ARM_G1S_IRQ_PROPS(grp)	CSS_G1S_IRQ_PROPS(grp)
 #define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
 

plat/arm/css/sgi/include/sgi_plat_config.h

@@ -7,7 +7,6 @@
 #ifndef __SGI_PLAT_CONFIG_H__
 #define __SGI_PLAT_CONFIG_H__
 
-#include <arm_gic.h>
 #include <ccn.h>
 #include <gicv3.h>
 

plat/arm/css/sgi/sgi-common.mk

@@ -6,8 +6,6 @@
 
 CSS_USE_SCMI_SDS_DRIVER		:=	1
 
-ENABLE_PLAT_COMPAT		:=	0
-
 CSS_ENT_BASE			:=	plat/arm/css/sgi
 
 RAS_EXTENSION			:=	0

plat/arm/css/sgi/sgi_plat.c

@@ -65,7 +65,7 @@ const mmap_region_t plat_arm_mmap[] = {
 #if ENABLE_SPM
 	ARM_SP_IMAGE_MMAP,
 #endif
-#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2 && !BL2_AT_EL3
+#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
 	ARM_MAP_BL1_RW,
 #endif
 	{0}
@@ -148,7 +148,7 @@ const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
 }
 #endif /* ENABLE_SPM && defined(IMAGE_BL31) */
 
-#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2
+#if TRUSTED_BOARD_BOOT
 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
 {
 	assert(heap_addr != NULL);

plat/arm/css/sgm/include/sgm_plat_config.h

@@ -7,7 +7,6 @@
 #ifndef __SGM_PLAT_CONFIG_H__
 #define __SGM_PLAT_CONFIG_H__
 
-#include <arm_gic.h>
 #include <ccn.h>
 #include <gicv3.h>