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Unverified Commit 3ccfcd6e authored by Soby Mathew's avatar Soby Mathew Committed by GitHub
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Merge pull request #1587 from antonio-nino-diaz-arm/an/deprecated 

Remove deprecated interfaces for all platforms
parents 9a983cfe 991f1f4d
Hide whitespace changes
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plat/arm/css/sgm/sgm-common.mk
View file @ 3ccfcd6e
......@@ -48,9 +48,6 @@ BL31_SOURCES += $(SGM_CPU_SOURCES) \
# sgm uses CCI-500 as Cache Coherent Interconnect
ARM_CCI_PRODUCT_ID := 500
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
# System coherency is managed in hardware
HW_ASSISTED_COHERENCY := 1
......
plat/arm/css/sgm/sgm_mmap_config.c
View file @ 3ccfcd6e
......@@ -43,7 +43,7 @@ const mmap_region_t plat_arm_mmap[] = {
#ifdef SPD_opteed
ARM_OPTEE_PAGEABLE_LOAD_MEM,
#endif
#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2 && !BL2_AT_EL3
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
ARM_MAP_BL1_RW,
#endif
{0}
......
plat/arm/css/sgm/sgm_plat_config.c
View file @ 3ccfcd6e
......@@ -68,7 +68,7 @@ css_plat_config_t *get_plat_config(void)
return css_plat_info;
}
#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2
#if TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
{
assert(heap_addr != NULL);
......
plat/common/aarch32/plat_sp_min_common.c
View file @ 3ccfcd6e
......@@ -23,14 +23,3 @@ void sp_min_plat_runtime_setup(void)
*/
console_uninit();
}
#if !ERROR_DEPRECATED
#pragma weak sp_min_early_platform_setup2
void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
sp_min_early_platform_setup((void *)arg0, (void *)arg1);
}
#endif
plat/common/aarch64/plat_common.c
View file @ 3ccfcd6e
......@@ -19,10 +19,6 @@
* platforms but may also be overridden by a platform if required.
*/
#pragma weak bl31_plat_runtime_setup
#if !ERROR_DEPRECATED
#pragma weak plat_get_syscnt_freq2
#pragma weak bl31_early_platform_setup2
#endif /* ERROR_DEPRECATED */
#if SDEI_SUPPORT
#pragma weak plat_sdei_handle_masked_trigger
......@@ -40,7 +36,6 @@ void bl31_plat_runtime_setup(void)
#endif
}
#if !ENABLE_PLAT_COMPAT
/*
* Helper function for platform_get_pos() when platform compatibility is
* disabled. This is to enable SPDs using the older platform API to continue
......@@ -52,33 +47,6 @@ unsigned int platform_core_pos_helper(unsigned long mpidr)
assert(idx >= 0);
return idx;
}
#endif
#if !ERROR_DEPRECATED
unsigned int plat_get_syscnt_freq2(void)
{
WARN("plat_get_syscnt_freq() is deprecated\n");
WARN("Please define plat_get_syscnt_freq2()\n");
/*
* Suppress deprecated declaration warning in compatibility function
*/
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
unsigned long long freq = plat_get_syscnt_freq();
#pragma GCC diagnostic pop
assert(freq >> 32 == 0);
return (unsigned int)freq;
}
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
bl31_early_platform_setup((void *) arg0, (void *)arg1);
}
#endif /* ERROR_DEPRECATED */
#if SDEI_SUPPORT
/*
......
plat/common/aarch64/plat_psci_common.c deleted 100644 → 0
View file @ 9a983cfe
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#if !ERROR_DEPRECATED
#include "../plat_psci_common.c"
#endif
plat/common/aarch64/platform_helpers.S
View file @ 3ccfcd6e
......@@ -24,33 +24,10 @@
.weak plat_handle_double_fault
.weak plat_handle_el3_ea
#if !ENABLE_PLAT_COMPAT
.globl platform_get_core_pos
#define MPIDR_RES_BIT_MASK 0xff000000
/* ------------------------------------------------------------------
* int platform_get_core_pos(int mpidr)
* Returns the CPU index of the CPU specified by mpidr. This is
* defined when platform compatibility is disabled to enable Trusted
* Firmware components like SPD using the old platform API to work.
* This API is deprecated and it assumes that the mpidr specified is
* that of a valid and present CPU. Instead, plat_my_core_pos()
* should be used for CPU index of the current CPU and
* plat_core_pos_by_mpidr() should be used for CPU index of a
* CPU specified by its mpidr.
* ------------------------------------------------------------------
*/
func_deprecated platform_get_core_pos
bic x0, x0, #MPIDR_RES_BIT_MASK
mrs x1, mpidr_el1
bic x1, x1, #MPIDR_RES_BIT_MASK
cmp x0, x1
beq plat_my_core_pos
b platform_core_pos_helper
endfunc_deprecated platform_get_core_pos
#endif
/* -----------------------------------------------------
* Placeholder function which should be redefined by
* each platform.
......
plat/common/aarch64/platform_mp_stack.S
View file @ 3ccfcd6e
......@@ -10,81 +10,11 @@
#include <platform_def.h>
.local platform_normal_stacks
#if ENABLE_PLAT_COMPAT
.globl plat_get_my_stack
.globl plat_set_my_stack
.weak platform_get_stack
.weak platform_set_stack
#else
.weak plat_get_my_stack
.weak plat_set_my_stack
.globl platform_get_stack
.globl platform_set_stack
#endif /* __ENABLE_PLAT_COMPAT__ */
#if ENABLE_PLAT_COMPAT
/* ---------------------------------------------------------------------
* When the compatility layer is enabled, the new platform APIs
* viz plat_get_my_stack() and plat_set_my_stack() need to be
* defined using the previous APIs platform_get_stack() and
* platform_set_stack(). Also we need to provide weak definitions
* of platform_get_stack() and platform_set_stack() for the platforms
* to reuse.
* --------------------------------------------------------------------
*/
/* -----------------------------------------------------
* unsigned long plat_get_my_stack ()
*
* For the current CPU, this function returns the stack
* pointer for a stack allocated in device memory.
* -----------------------------------------------------
*/
func plat_get_my_stack
mrs x0, mpidr_el1
b platform_get_stack
endfunc plat_get_my_stack
/* -----------------------------------------------------
* void plat_set_my_stack ()
*
* For the current CPU, this function sets the stack
* pointer to a stack allocated in normal memory.
* -----------------------------------------------------
*/
func plat_set_my_stack
mrs x0, mpidr_el1
b platform_set_stack
endfunc plat_set_my_stack
/* -----------------------------------------------------
* unsigned long platform_get_stack (unsigned long mpidr)
*
* For a given CPU, this function returns the stack
* pointer for a stack allocated in device memory.
* -----------------------------------------------------
*/
func platform_get_stack
mov x10, x30 // lr
get_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE
ret x10
endfunc platform_get_stack
/* -----------------------------------------------------
* void platform_set_stack (unsigned long mpidr)
*
* For a given CPU, this function sets the stack pointer
* to a stack allocated in normal memory.
* -----------------------------------------------------
*/
func platform_set_stack
mov x9, x30 // lr
bl platform_get_stack
mov sp, x0
ret x9
endfunc platform_set_stack
#else
/* ---------------------------------------------------------------------
* When the compatility layer is disabled, the new platform APIs
* viz plat_get_my_stack() and plat_set_my_stack() are
......@@ -96,44 +26,6 @@ endfunc platform_set_stack
* --------------------------------------------------------------------
*/
/* -------------------------------------------------------
* unsigned long platform_get_stack (unsigned long mpidr)
*
* For the current CPU, this function returns the stack
* pointer for a stack allocated in device memory. The
* 'mpidr' should correspond to that of the current CPU.
* This function is deprecated and plat_get_my_stack()
* should be used instead.
* -------------------------------------------------------
*/
func_deprecated platform_get_stack
#if ENABLE_ASSERTIONS
mrs x1, mpidr_el1
cmp x0, x1
ASM_ASSERT(eq)
#endif
b plat_get_my_stack
endfunc_deprecated platform_get_stack
/* -----------------------------------------------------
* void platform_set_stack (unsigned long mpidr)
*
* For the current CPU, this function sets the stack pointer
* to a stack allocated in normal memory. The
* 'mpidr' should correspond to that of the current CPU.
* This function is deprecated and plat_get_my_stack()
* should be used instead.
* -----------------------------------------------------
*/
func_deprecated platform_set_stack
#if ENABLE_ASSERTIONS
mrs x1, mpidr_el1
cmp x0, x1
ASM_ASSERT(eq)
#endif
b plat_set_my_stack
endfunc_deprecated platform_set_stack
/* -----------------------------------------------------
* uintptr_t plat_get_my_stack ()
*
......@@ -161,8 +53,6 @@ func plat_set_my_stack
ret x9
endfunc plat_set_my_stack
#endif /*__ENABLE_PLAT_COMPAT__*/
/* -----------------------------------------------------
* Per-cpu stacks in normal memory. Each cpu gets a
* stack of PLATFORM_STACK_SIZE bytes.
......
plat/common/aarch64/platform_up_stack.S
View file @ 3ccfcd6e
......@@ -42,32 +42,6 @@ func plat_set_my_stack
ret
endfunc plat_set_my_stack
/* -----------------------------------------------------
* unsigned long platform_get_stack ()
*
* For cold-boot BL images, only the primary CPU needs a
* stack. This function returns the stack pointer for a
* stack allocated in device memory. This function
* is deprecated.
* -----------------------------------------------------
*/
func_deprecated platform_get_stack
b plat_get_my_stack
endfunc_deprecated platform_get_stack
/* -----------------------------------------------------
* void platform_set_stack ()
*
* For cold-boot BL images, only the primary CPU needs a
* stack. This function sets the stack pointer to a stack
* allocated in normal memory.This function is
* deprecated.
* -----------------------------------------------------
*/
func_deprecated platform_set_stack
b plat_set_my_stack
endfunc_deprecated platform_set_stack
/* -----------------------------------------------------
* Single cpu stack in normal memory.
* Used for C code during boot, PLATFORM_STACK_SIZE bytes
......
plat/common/plat_bl1_common.c
View file @ 3ccfcd6e
......@@ -104,18 +104,9 @@ int bl1_plat_handle_post_image_load(unsigned int image_id)
* to BL2. BL2 will read the memory layout before using its
* memory for other purposes.
*/
#if LOAD_IMAGE_V2
bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base;
#else
bl2_tzram_layout = (meminfo_t *) round_up(bl1_tzram_layout->free_base,
sizeof(uint64_t));
#endif /* LOAD_IMAGE_V2 */
#if !ERROR_DEPRECATED
bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
#else
bl1_calc_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
#endif
ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout;
......
plat/common/plat_bl_common.c
View file @ 3ccfcd6e
......@@ -40,7 +40,6 @@ void bl2_plat_preload_setup(void)
{
}
#if LOAD_IMAGE_V2
int bl2_plat_handle_pre_image_load(unsigned int image_id)
{
return 0;
......@@ -50,28 +49,12 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
{
return 0;
}
#endif
int plat_try_next_boot_source(void)
{
return 0;
}
#if !ERROR_DEPRECATED
#pragma weak bl2_early_platform_setup2
/*
* The following platform API implementation that allow compatibility for
* the older platform APIs.
*/
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
bl2_early_platform_setup((void *)arg1);
}
#endif
#if TRUSTED_BOARD_BOOT
/*
* The following default implementation of the function simply returns the
......
plat/common/plat_gic.c deleted 100644 → 0
View file @ 9a983cfe
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arm_gic.h>
/*
* The following platform GIC functions are weakly defined. They
* provide typical implementations that may be re-used by multiple
* platforms but may also be overridden by a platform if required.
*/
#pragma weak plat_ic_get_pending_interrupt_id
#pragma weak plat_ic_get_pending_interrupt_type
#pragma weak plat_ic_acknowledge_interrupt
#pragma weak plat_ic_get_interrupt_type
#pragma weak plat_ic_end_of_interrupt
#pragma weak plat_interrupt_type_to_line
uint32_t plat_ic_get_pending_interrupt_id(void)
{
return arm_gic_get_pending_interrupt_id();
}
uint32_t plat_ic_get_pending_interrupt_type(void)
{
return arm_gic_get_pending_interrupt_type();
}
uint32_t plat_ic_acknowledge_interrupt(void)
{
return arm_gic_acknowledge_interrupt();
}
uint32_t plat_ic_get_interrupt_type(uint32_t id)
{
return arm_gic_get_interrupt_type(id);
}
void plat_ic_end_of_interrupt(uint32_t id)
{
arm_gic_end_of_interrupt(id);
}
uint32_t plat_interrupt_type_to_line(uint32_t type,
uint32_t security_state)
{
return arm_gic_interrupt_type_to_line(type, security_state);
}
plat/compat/aarch64/plat_helpers_compat.S deleted 100644 → 0
View file @ 9a983cfe
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
#include <platform_def.h>
.globl plat_my_core_pos
.globl plat_is_my_cpu_primary
.globl plat_get_my_entrypoint
.weak platform_get_core_pos
/* -----------------------------------------------------
* Compatibility wrappers for new platform APIs.
* -----------------------------------------------------
*/
func plat_my_core_pos
mrs x0, mpidr_el1
b platform_get_core_pos
endfunc plat_my_core_pos
func plat_is_my_cpu_primary
mrs x0, mpidr_el1
b platform_is_primary_cpu
endfunc plat_is_my_cpu_primary
func plat_get_my_entrypoint
mrs x0, mpidr_el1
b platform_get_entrypoint
endfunc plat_get_my_entrypoint
/* -----------------------------------------------------
* int platform_get_core_pos(int mpidr);
* With this function: CorePos = (ClusterId * 4) +
* CoreId
* -----------------------------------------------------
*/
func platform_get_core_pos
and x1, x0, #MPIDR_CPU_MASK
and x0, x0, #MPIDR_CLUSTER_MASK
add x0, x1, x0, LSR #6
ret
endfunc platform_get_core_pos
plat/compat/plat_compat.mk deleted 100644 → 0
View file @ 9a983cfe
#
# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq (${PSCI_EXTENDED_STATE_ID}, 1)
$(error "PSCI Compatibility mode can be enabled only if \
PSCI_EXTENDED_STATE_ID is not set")
endif
ifneq (${ARCH}, aarch64)
$(error "PSCI Compatibility mode is only supported for AArch64 platforms")
endif
PLAT_BL_COMMON_SOURCES += plat/compat/aarch64/plat_helpers_compat.S
BL31_SOURCES += plat/common/plat_psci_common.c \
plat/compat/plat_pm_compat.c \
plat/compat/plat_topology_compat.c
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
plat/compat/plat_pm_compat.c deleted 100644 → 0
View file @ 9a983cfe
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <assert.h>
#include <errno.h>
#include <platform.h>
#include <psci.h>
/*
* The platform hooks exported by the platform using the earlier version of
* platform interface
*/
const plat_pm_ops_t *pm_ops;
/*
* The hooks exported by the compatibility layer
*/
static plat_psci_ops_t compat_psci_ops;
/*
* The secure entry point to be used on warm reset.
*/
static unsigned long secure_entrypoint;
/*
* This array stores the 'power_state' requests of each CPU during
* CPU_SUSPEND and SYSTEM_SUSPEND to support querying of state-ID
* by the platform.
*/
unsigned int psci_power_state_compat[PLATFORM_CORE_COUNT];
/*******************************************************************************
* The PSCI compatibility helper to parse the power state and populate the
* 'pwr_domain_state' for each power level. It is assumed that, when in
* compatibility mode, the PSCI generic layer need to know only whether the
* affinity level will be OFF or in RETENTION and if the platform supports
* multiple power down and retention states, it will be taken care within
* the platform layer.
******************************************************************************/
static int parse_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
int i;
int pstate = psci_get_pstate_type(power_state);
int aff_lvl = psci_get_pstate_pwrlvl(power_state);
if (aff_lvl > PLATFORM_MAX_AFFLVL)
return PSCI_E_INVALID_PARAMS;
/* Sanity check the requested state */
if (pstate == PSTATE_TYPE_STANDBY) {
/*
* Set the CPU local state as retention and ignore the higher
* levels. This allows the generic PSCI layer to invoke
* plat_psci_ops 'cpu_standby' hook and the compatibility
* layer invokes the 'affinst_standby' handler with the
* correct power_state parameter thus preserving the correct
* behavior.
*/
req_state->pwr_domain_state[0] =
PLAT_MAX_RET_STATE;
} else {
for (i = 0; i <= aff_lvl; i++)
req_state->pwr_domain_state[i] =
PLAT_MAX_OFF_STATE;
}
return PSCI_E_SUCCESS;
}
/*******************************************************************************
* The PSCI compatibility helper to set the 'power_state' in
* psci_power_state_compat[] at index corresponding to the current core.
******************************************************************************/
static void set_psci_power_state_compat(unsigned int power_state)
{
unsigned int my_core_pos = plat_my_core_pos();
psci_power_state_compat[my_core_pos] = power_state;
flush_dcache_range((uintptr_t) &psci_power_state_compat[my_core_pos],
sizeof(psci_power_state_compat[my_core_pos]));
}
/*******************************************************************************
* The PSCI compatibility helper for plat_pm_ops_t 'validate_power_state'
* hook.
******************************************************************************/
static int validate_power_state_compat(unsigned int power_state,
psci_power_state_t *req_state)
{
int rc;
assert(req_state);
if (pm_ops->validate_power_state) {
rc = pm_ops->validate_power_state(power_state);
if (rc != PSCI_E_SUCCESS)
return rc;
}
/* Store the 'power_state' parameter for the current CPU. */
set_psci_power_state_compat(power_state);
return parse_power_state(power_state, req_state);
}
/*******************************************************************************
* The PSCI compatibility helper for plat_pm_ops_t
* 'get_sys_suspend_power_state' hook.
******************************************************************************/
void get_sys_suspend_power_state_compat(psci_power_state_t *req_state)
{
unsigned int power_state;
assert(req_state);
power_state = pm_ops->get_sys_suspend_power_state();
/* Store the 'power_state' parameter for the current CPU. */
set_psci_power_state_compat(power_state);
if (parse_power_state(power_state, req_state) != PSCI_E_SUCCESS)
assert(0);
}
/*******************************************************************************
* The PSCI compatibility helper for plat_pm_ops_t 'validate_ns_entrypoint'
* hook.
******************************************************************************/
static int validate_ns_entrypoint_compat(uintptr_t ns_entrypoint)
{
return pm_ops->validate_ns_entrypoint(ns_entrypoint);
}
/*******************************************************************************
* The PSCI compatibility helper for plat_pm_ops_t 'affinst_standby' hook.
******************************************************************************/
static void cpu_standby_compat(plat_local_state_t cpu_state)
{
unsigned int powerstate = psci_get_suspend_powerstate();
assert(powerstate != PSCI_INVALID_DATA);
pm_ops->affinst_standby(powerstate);
}
/*******************************************************************************
* The PSCI compatibility helper for plat_pm_ops_t 'affinst_on' hook.
******************************************************************************/
static int pwr_domain_on_compat(u_register_t mpidr)
{
int level, rc;
/*
* The new PSCI framework does not hold the locks for higher level
* power domain nodes when this hook is invoked. Hence figuring out the
* target state of the parent power domains does not make much sense.
* Hence we hard-code the state as PSCI_STATE_OFF for all the levels.
* We expect the platform to perform the necessary CPU_ON operations
* when the 'affinst_on' is invoked only for level 0.
*/
for (level = PLATFORM_MAX_AFFLVL; level >= 0; level--) {
rc = pm_ops->affinst_on((unsigned long)mpidr, secure_entrypoint,
level, PSCI_STATE_OFF);
if (rc != PSCI_E_SUCCESS)
break;
}
return rc;
}
/*******************************************************************************
* The PSCI compatibility helper for plat_pm_ops_t 'affinst_off' hook.
******************************************************************************/
static void pwr_domain_off_compat(const psci_power_state_t *target_state)
{
int level;
unsigned int plat_state;
for (level = 0; level <= PLATFORM_MAX_AFFLVL; level++) {
plat_state = (is_local_state_run(
target_state->pwr_domain_state[level]) ?
PSCI_STATE_ON : PSCI_STATE_OFF);
pm_ops->affinst_off(level, plat_state);
}
}
/*******************************************************************************
* The PSCI compatibility helper for plat_pm_ops_t 'affinst_suspend' hook.
******************************************************************************/
static void pwr_domain_suspend_compat(const psci_power_state_t *target_state)
{
int level;
unsigned int plat_state;
for (level = 0; level <= psci_get_suspend_afflvl(); level++) {
plat_state = (is_local_state_run(
target_state->pwr_domain_state[level]) ?
PSCI_STATE_ON : PSCI_STATE_OFF);
pm_ops->affinst_suspend(secure_entrypoint, level, plat_state);
}
}
/*******************************************************************************
* The PSCI compatibility helper for plat_pm_ops_t 'affinst_on_finish'
* hook.
******************************************************************************/
static void pwr_domain_on_finish_compat(const psci_power_state_t *target_state)
{
int level;
unsigned int plat_state;
for (level = PLATFORM_MAX_AFFLVL; level >= 0; level--) {
plat_state = (is_local_state_run(
target_state->pwr_domain_state[level]) ?
PSCI_STATE_ON : PSCI_STATE_OFF);
pm_ops->affinst_on_finish(level, plat_state);
}
}
/*******************************************************************************
* The PSCI compatibility helper for plat_pm_ops_t
* 'affinst_suspend_finish' hook.
******************************************************************************/
static void pwr_domain_suspend_finish_compat(
const psci_power_state_t *target_state)
{
int level;
unsigned int plat_state;
for (level = psci_get_suspend_afflvl(); level >= 0; level--) {
plat_state = (is_local_state_run(
target_state->pwr_domain_state[level]) ?
PSCI_STATE_ON : PSCI_STATE_OFF);
pm_ops->affinst_suspend_finish(level, plat_state);
}
}
/*******************************************************************************
* The PSCI compatibility helper for plat_pm_ops_t 'system_off' hook.
******************************************************************************/
static void __dead2 system_off_compat(void)
{
pm_ops->system_off();
}
/*******************************************************************************
* The PSCI compatibility helper for plat_pm_ops_t 'system_reset' hook.
******************************************************************************/
static void __dead2 system_reset_compat(void)
{
pm_ops->system_reset();
}
/*******************************************************************************
* Export the compatibility compat_psci_ops. The assumption made is that the
* power domains correspond to affinity instances on the platform.
******************************************************************************/
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const plat_psci_ops_t **psci_ops)
{
platform_setup_pm(&pm_ops);
secure_entrypoint = (unsigned long) sec_entrypoint;
/*
* It is compulsory for the platform ports using the new porting
* interface to export a hook to validate the power state parameter
*/
compat_psci_ops.validate_power_state = validate_power_state_compat;
/*
* Populate the compatibility plat_psci_ops_t hooks if available
*/
if (pm_ops->validate_ns_entrypoint)
compat_psci_ops.validate_ns_entrypoint =
validate_ns_entrypoint_compat;
if (pm_ops->affinst_standby)
compat_psci_ops.cpu_standby = cpu_standby_compat;
if (pm_ops->affinst_on)
compat_psci_ops.pwr_domain_on = pwr_domain_on_compat;
if (pm_ops->affinst_off)
compat_psci_ops.pwr_domain_off = pwr_domain_off_compat;
if (pm_ops->affinst_suspend)
compat_psci_ops.pwr_domain_suspend = pwr_domain_suspend_compat;
if (pm_ops->affinst_on_finish)
compat_psci_ops.pwr_domain_on_finish =
pwr_domain_on_finish_compat;
if (pm_ops->affinst_suspend_finish)
compat_psci_ops.pwr_domain_suspend_finish =
pwr_domain_suspend_finish_compat;
if (pm_ops->system_off)
compat_psci_ops.system_off = system_off_compat;
if (pm_ops->system_reset)
compat_psci_ops.system_reset = system_reset_compat;
if (pm_ops->get_sys_suspend_power_state)
compat_psci_ops.get_sys_suspend_power_state =
get_sys_suspend_power_state_compat;
*psci_ops = &compat_psci_ops;
return 0;
}
plat/compat/plat_topology_compat.c deleted 100644 → 0
View file @ 9a983cfe
/*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <assert.h>
#include <platform.h>
#include <platform_def.h>
#include <psci.h>
/* The power domain tree descriptor */
static unsigned char power_domain_tree_desc
[PLATFORM_NUM_AFFS - PLATFORM_CORE_COUNT + 1];
/*******************************************************************************
* Simple routine to set the id of an affinity instance at a given level
* in the mpidr. The assumption is that the affinity level and the power
* domain level are the same.
******************************************************************************/
unsigned long mpidr_set_aff_inst(unsigned long mpidr,
unsigned char aff_inst,
int aff_lvl)
{
unsigned long aff_shift;
assert(aff_lvl <= MPIDR_AFFLVL3);
/*
* Decide the number of bits to shift by depending upon
* the power level
*/
aff_shift = get_afflvl_shift(aff_lvl);
/* Clear the existing power instance & set the new one*/
mpidr &= ~((unsigned long)MPIDR_AFFLVL_MASK << aff_shift);
mpidr |= (unsigned long)aff_inst << aff_shift;
return mpidr;
}
/******************************************************************************
* This function uses insertion sort to sort a given list of mpidr's in the
* ascending order of the index returned by platform_get_core_pos.
*****************************************************************************/
void sort_mpidr_by_cpu_idx(unsigned int aff_count, unsigned long mpidr_list[])
{
int i, j;
unsigned long temp_mpidr;
for (i = 1; i < aff_count; i++) {
temp_mpidr = mpidr_list[i];
for (j = i;
j > 0 &&
platform_get_core_pos(mpidr_list[j-1]) >
platform_get_core_pos(temp_mpidr);
j--)
mpidr_list[j] = mpidr_list[j-1];
mpidr_list[j] = temp_mpidr;
}
}
/*******************************************************************************
* The compatibility routine to construct the power domain tree description.
* The assumption made is that the power domains correspond to affinity
* instances on the platform. This routine's aim is to traverse to the target
* affinity level and populate the number of siblings at that level in
* 'power_domain_tree_desc' array. It uses the current affinity level to keep
* track of how many levels from the root of the tree have been traversed.
* If the current affinity level != target affinity level, then the platform
* is asked to return the number of children that each affinity instance has
* at the current affinity level. Traversal is then done for each child at the
* next lower level i.e. current affinity level - 1.
*
* The power domain description needs to be constructed in such a way that
* affinity instances containing CPUs with lower cpu indices need to be
* described first. Hence when traversing the power domain levels, the list
* of mpidrs at that power domain level is sorted in the ascending order of CPU
* indices before the lower levels are recursively described.
*
* CAUTION: This routine assumes that affinity instance ids are allocated in a
* monotonically increasing manner at each affinity level in a mpidr starting
* from 0. If the platform breaks this assumption then this code will have to
* be reworked accordingly.
******************************************************************************/
static unsigned int init_pwr_domain_tree_desc(unsigned long mpidr,
unsigned int affmap_idx,
unsigned int cur_afflvl,
unsigned int tgt_afflvl)
{
unsigned int ctr, aff_count;
/*
* Temporary list to hold the MPIDR list at a particular power domain
* level so as to sort them.
*/
unsigned long mpidr_list[PLATFORM_CORE_COUNT];
assert(cur_afflvl >= tgt_afflvl);
/*
* Find the number of siblings at the current power level &
* assert if there are none 'cause then we have been invoked with
* an invalid mpidr.
*/
aff_count = plat_get_aff_count(cur_afflvl, mpidr);
assert(aff_count);
if (tgt_afflvl < cur_afflvl) {
for (ctr = 0; ctr < aff_count; ctr++) {
mpidr_list[ctr] = mpidr_set_aff_inst(mpidr, ctr,
cur_afflvl);
}
/* Need to sort mpidr list according to CPU index */
sort_mpidr_by_cpu_idx(aff_count, mpidr_list);
for (ctr = 0; ctr < aff_count; ctr++) {
affmap_idx = init_pwr_domain_tree_desc(mpidr_list[ctr],
affmap_idx,
cur_afflvl - 1,
tgt_afflvl);
}
} else {
power_domain_tree_desc[affmap_idx++] = aff_count;
}
return affmap_idx;
}
/*******************************************************************************
* This function constructs the topology tree description at runtime
* and returns it. The assumption made is that the power domains correspond
* to affinity instances on the platform.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
int afflvl;
unsigned int affmap_idx;
/*
* We assume that the platform allocates affinity instance ids from
* 0 onwards at each affinity level in the mpidr. FIRST_MPIDR = 0.0.0.0
*/
affmap_idx = 0;
for (afflvl = (int) PLATFORM_MAX_AFFLVL;
afflvl >= (int) MPIDR_AFFLVL0; afflvl--) {
affmap_idx = init_pwr_domain_tree_desc(FIRST_MPIDR,
affmap_idx,
PLATFORM_MAX_AFFLVL,
(unsigned int) afflvl);
}
assert(affmap_idx == (PLATFORM_NUM_AFFS - PLATFORM_CORE_COUNT + 1));
return power_domain_tree_desc;
}
/******************************************************************************
* The compatibility helper function for plat_core_pos_by_mpidr(). It
* validates the 'mpidr' by making sure that it is within acceptable bounds
* for the platform and queries the platform layer whether the CPU specified
* by the mpidr is present or not. If present, it returns the index of the
* core corresponding to the 'mpidr'. Else it returns -1.
*****************************************************************************/
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
unsigned long shift, aff_inst;
int i;
/* Ignore the Reserved bits and U bit in MPIDR */
mpidr &= MPIDR_AFFINITY_MASK;
/*
* Check if any affinity field higher than
* the PLATFORM_MAX_AFFLVL is set.
*/
shift = get_afflvl_shift(PLATFORM_MAX_AFFLVL + 1);
if (mpidr >> shift)
return -1;
for (i = PLATFORM_MAX_AFFLVL; i >= 0; i--) {
shift = get_afflvl_shift(i);
aff_inst = ((mpidr &
((unsigned long)MPIDR_AFFLVL_MASK << shift)) >> shift);
if (aff_inst >= plat_get_aff_count(i, mpidr))
return -1;
}
if (plat_get_aff_state(0, mpidr) == PSCI_AFF_ABSENT)
return -1;
return platform_get_core_pos(mpidr);
}
plat/hisilicon/hikey/aarch64/hikey_common.c
View file @ 3ccfcd6e
......@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
......
plat/hisilicon/hikey/hikey_bl1_setup.c
View file @ 3ccfcd6e
......@@ -37,28 +37,6 @@ meminfo_t *bl1_plat_sec_mem_layout(void)
return &bl1_tzram_layout;
}
/*******************************************************************************
* Function that takes a memory layout into which BL2 has been loaded and
* populates a new memory layout for BL2 that ensures that BL1's data sections
* resident in secure RAM are not visible to BL2.
******************************************************************************/
void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
meminfo_t *bl2_mem_layout)
{
assert(bl1_mem_layout != NULL);
assert(bl2_mem_layout != NULL);
/*
* Cannot remove BL1 RW data from the scope of memory visible to BL2
* like arm platforms because they overlap in hikey
*/
bl2_mem_layout->total_base = BL2_BASE;
bl2_mem_layout->total_size = BL32_SRAM_LIMIT - BL2_BASE;
flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
}
/*
* Perform any BL1 specific platform actions.
*/
......
plat/hisilicon/hikey/hikey_bl31_setup.c
View file @ 3ccfcd6e
......@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <cci.h>
......@@ -17,6 +16,7 @@
#include <hikey_def.h>
#include <hisi_ipc.h>
#include <hisi_pwrc.h>
#include <interrupt_props.h>
#include <mmio.h>
#include <platform_def.h>
......@@ -48,9 +48,11 @@ static entry_point_info_t bl33_ep_info;
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
*****************************************************************************/
const unsigned int g0_interrupt_array[] = {
IRQ_SEC_PHY_TIMER,
IRQ_SEC_SGI_0
static const interrupt_prop_t g0_interrupt_props[] = {
INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
/*
......@@ -61,8 +63,8 @@ const unsigned int g0_interrupt_array[] = {
gicv2_driver_data_t hikey_gic_data = {
.gicd_base = PLAT_ARM_GICD_BASE,
.gicc_base = PLAT_ARM_GICC_BASE,
.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
.g0_interrupt_array = g0_interrupt_array,
.interrupt_props = g0_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
};
static const int cci_map[] = {
......@@ -82,9 +84,13 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
return NULL;
}
void bl31_early_platform_setup(void *from_bl2,
void *plat_params_from_bl2)
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
void *from_bl2;
from_bl2 = (void *) arg0;
/* Initialize the console to provide early debug support */
console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
......
plat/hisilicon/hikey/include/plat_macros.S
View file @ 3ccfcd6e
......@@ -8,7 +8,7 @@
#define __PLAT_MACROS_S__
#include <cci.h>
#include <gic_v2.h>
#include <gicv2.h>
#include <hi6220.h>
#include <platform_def.h>
......
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