Merge pull request #1587 from antonio-nino-diaz-arm/an/deprecated

Remove deprecated interfaces for all platforms

plat/imx/imx8qx/imx8qx_bl31_setup.c

@@ -250,8 +250,8 @@ void imx8_partition_resources(void)
 		NOTICE("Non-secure Partitioning Succeeded\n");
 }
 
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
-				void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
 {
 #if DEBUG_CONSOLE
 	static console_lpuart_t console;

plat/imx/imx8qx/platform.mk

@@ -30,8 +30,6 @@ BL31_SOURCES		+=	plat/imx/common/lpuart_console.S	\
 
 include plat/imx/common/sci/sci_api.mk
 
-ENABLE_PLAT_COMPAT	:=	0
 USE_COHERENT_MEM	:=	1
 RESET_TO_BL31		:=	1
-ARM_GIC_ARCH		:=	3
 MULTI_CONSOLE_API	:=	1

plat/layerscape/board/ls1043/platform.mk

@@ -63,7 +63,6 @@ BL31_SOURCES			+=	plat/layerscape/board/ls1043/ls1043_bl31_setup.c		\
 					${LS1043_SECURITY_SOURCES}
 
 # Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT		:= 	0
 MULTI_CONSOLE_API		:=	1
 
 # Enable workarounds for selected Cortex-A53 erratas.

plat/layerscape/common/ls_bl31_setup.c

@@ -7,8 +7,10 @@
 #include <assert.h>
 #include <bl_common.h>
 #include <console.h>
-#include <mmio.h>
 #include <gicv2.h>
+#include <interrupt_props.h>
+#include <mmio.h>
+
 #include "ls_16550.h"
 #include "plat_ls.h"
 #include "soc.h"
@@ -20,15 +22,16 @@
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
 
-const unsigned int g0_interrupt_array1[] = {
-	9
+static const interrupt_prop_t g0_interrupt_props[] = {
+	INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
 };
 
 gicv2_driver_data_t ls_gic_data = {
 	.gicd_base = GICD_BASE,
 	.gicc_base = GICC_BASE,
-	.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array1),
-	.g0_interrupt_array = g0_interrupt_array1,
+	.interrupt_props = g0_interrupt_props,
+	.interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
 };
 
 

plat/layerscape/common/ls_common.mk

@@ -13,13 +13,6 @@ LS1043_DISABLE_TRUSTED_WDOG	:=	1
 # mapping the former as executable and the latter as execute-never.
 SEPARATE_CODE_AND_RODATA	:=	1
 
-# Enable new version of image loading on Layerscape platforms
-LOAD_IMAGE_V2			:=	1
-
-# Use generic OID definition (tbbr_oid.h)
-USE_TBBR_DEFS			:=	1
-
-
 COLD_BOOT_SINGLE_CPU		:=	1
 
 PLAT_INCLUDES		+=	-Iinclude/common/tbbr
@@ -54,9 +47,3 @@ BL31_SOURCES		+=	plat/layerscape/common/ls_bl31_setup.c		\
 				plat/layerscape/common/ls_topology.c			\
 				plat/layerscape/common/ns_access.c		\
 				plat/common/plat_psci_common.c
-# Verify build config
-# -------------------
-
-ifneq (${LOAD_IMAGE_V2}, 1)
-  $(error Error: Layerscape needs LOAD_IMAGE_V2=1)
-endif

plat/layerscape/common/tsp/ls_tsp_setup.c

@@ -4,23 +4,26 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <gicv2.h>
 #include <debug.h>
+#include <gicv2.h>
+#include <interrupt_props.h>
+
 #include "ls_16550.h"
 #include "plat_ls.h"
 #include "soc.h"
 
 #define BL32_END (unsigned long)(&__BL32_END__)
 
-const unsigned int g0_interrupt_array1[] = {
-	9
+static const interrupt_prop_t g0_interrupt_props[] = {
+	INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
 };
 
 gicv2_driver_data_t ls_gic_data = {
 	.gicd_base = GICD_BASE,
 	.gicc_base = GICC_BASE,
-	.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array1),
-	.g0_interrupt_array = g0_interrupt_array1,
+	.interrupt_props = g0_interrupt_props,
+	.interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
 };
 
 /*******************************************************************************

plat/marvell/a8k/common/a8k_common.mk

@@ -97,11 +97,6 @@ BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a72.S		       \
 # Add trace functionality for PM
 BL31_SOURCES		+=	$(PLAT_COMMON_BASE)/plat_pm_trace.c
 
-# Disable the PSCI platform compatibility layer (allows porting
-# from Old Platform APIs to the new APIs).
-# It is not needed since Marvell platform already used the new platform APIs.
-ENABLE_PLAT_COMPAT	:= 	0
-
 # Force builds with BL2 image on a80x0 platforms
 ifndef SCP_BL2
  $(error "Error: SCP_BL2 image is mandatory for a8k family")

plat/marvell/common/marvell_bl2_setup.c

@@ -24,7 +24,7 @@ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
  *****************************************************************************
  */
 typedef struct bl2_to_bl31_params_mem {
-	bl31_params_t bl31_params;
+	struct marvell_bl31_params bl31_params;
 	image_info_t bl31_image_info;
 	image_info_t bl32_image_info;
 	image_info_t bl33_image_info;
@@ -68,9 +68,9 @@ meminfo_t *bl2_plat_sec_mem_layout(void)
  * before generating params to BL31
  *****************************************************************************
  */
-bl31_params_t *bl2_plat_get_bl31_params(void)
+void *bl2_plat_get_bl31_params(void)
 {
-	bl31_params_t *bl2_to_bl31_params;
+	struct marvell_bl31_params *bl2_to_bl31_params;
 
 	/*
 	 * Initialise the memory for all the arguments that needs to
@@ -109,7 +109,7 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
 	SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
 		VERSION_1, 0);
 
-	return bl2_to_bl31_params;
+	return (void *)bl2_to_bl31_params;
 }
 
 /* Flush the TF params and the TF plat params */
@@ -153,8 +153,12 @@ void marvell_bl2_early_platform_setup(meminfo_t *mem_layout)
 	plat_marvell_io_setup();
 }
 
-void bl2_early_platform_setup(meminfo_t *mem_layout)
+
+void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+			       u_register_t arg2, u_register_t arg3)
 {
+	struct meminfo *mem_layout = (struct meminfo *)arg1;
+
 	marvell_bl2_early_platform_setup(mem_layout);
 }
 

plat/marvell/common/marvell_bl31_setup.c

@@ -68,11 +68,14 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  * we are guaranteed to pick up good data.
  *****************************************************************************
  */
-void marvell_bl31_early_platform_setup(bl31_params_t *from_bl2,
+void marvell_bl31_early_platform_setup(void *from_bl2,
 				       uintptr_t soc_fw_config,
 				       uintptr_t hw_config,
 				       void *plat_params_from_bl2)
 {
+	struct marvell_bl31_params *params_from_bl2 =
+					(struct marvell_bl31_params *)from_bl2;
+
 	/* Initialize the console to provide early debug support */
 	console_init(PLAT_MARVELL_BOOT_UART_BASE,
 		     PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
@@ -126,9 +129,9 @@ void marvell_bl31_early_platform_setup(bl31_params_t *from_bl2,
 	 * Copy BL32 (if populated by BL2) and BL33 entry point information.
 	 * They are stored in Secure RAM, in BL2's address space.
 	 */
-	if (from_bl2->bl32_ep_info)
-		bl32_image_ep_info = *from_bl2->bl32_ep_info;
-	bl33_image_ep_info = *from_bl2->bl33_ep_info;
+	if (params_from_bl2->bl32_ep_info)
+		bl32_image_ep_info = *params_from_bl2->bl32_ep_info;
+	bl33_image_ep_info = *params_from_bl2->bl33_ep_info;
 #endif
 }
 

plat/marvell/common/mrvl_sip_svc.c

@@ -11,7 +11,7 @@
 #include <marvell_plat_priv.h>
 #include <plat_marvell.h>
 #include <runtime_svc.h>
-#include <smcc.h>
+#include <smccc.h>
 #include "comphy/phy-comphy-cp110.h"
 
 /* #define DEBUG_COMPHY */

plat/mediatek/common/mtk_plat_common.c

@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <bl_common.h>
 #include <cci.h>
 #include <console.h>

plat/mediatek/common/mtk_plat_common.h

 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef __MTK_PLAT_COMMON_H__
 #define __MTK_PLAT_COMMON_H__
+
+#include <bl_common.h>
+#include <param_header.h>
 #include <stdint.h>
+
 /*******************************************************************************
  * Function and variable prototypes
  ******************************************************************************/
@@ -45,6 +49,15 @@ struct mtk_bl_param_t {
 	uint64_t tee_info_addr;
 };
 
+struct mtk_bl31_params {
+       param_header_t h;
+       image_info_t *bl31_image_info;
+       entry_point_info_t *bl32_ep_info;
+       image_info_t *bl32_image_info;
+       entry_point_info_t *bl33_ep_info;
+       image_info_t *bl33_image_info;
+};
+
 /* Declarations for mtk_plat_common.c */
 uint32_t plat_get_spsr_for_bl32_entry(void);
 uint32_t plat_get_spsr_for_bl33_entry(void);

plat/mediatek/mt6795/bl31_plat_setup.c

@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <assert.h>
 #include <bl_common.h>
 #include <cci.h>
@@ -172,16 +171,15 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  * BL2 has flushed this information to memory, so we are guaranteed to pick up
  * good data.
  ******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
-						 void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
 {
-	struct mtk_bl_param_t *pmtk_bl_param =
-	(struct mtk_bl_param_t *)from_bl2;
+	struct mtk_bl_param_t *pmtk_bl_param = (struct mtk_bl_param_t *)arg0;
 	struct atf_arg_t *teearg;
 	unsigned long long normal_base;
 	unsigned long long atf_base;
 
-	assert(from_bl2 != NULL);
+	assert(pmtk_bl_param != NULL);
 	/*
 	 * Mediatek preloader(i.e, BL2) is in 32 bit state, high 32bits
 	 * of 64 bit GP registers are UNKNOWN if CPU warm reset from 32 bit
@@ -190,8 +188,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	 */
 	pmtk_bl_param =
 	(struct mtk_bl_param_t *)((uint64_t)pmtk_bl_param & 0x00000000ffffffff);
-	plat_params_from_bl2 =
-	(void *)((uint64_t)plat_params_from_bl2 & 0x00000000ffffffff);
 
 	teearg  = (struct atf_arg_t *)pmtk_bl_param->tee_info_addr;
 
@@ -445,6 +441,6 @@ void bl31_prepare_kernel_entry(uint64_t k32_64)
 	INFO("BL3-1: Next image address = 0x%llx\n",
 		(unsigned long long) next_image_info->pc);
 	INFO("BL3-1: Next image spsr = 0x%x\n", next_image_info->spsr);
-	cm_init_context(read_mpidr_el1(), next_image_info);
+	cm_init_my_context(next_image_info);
 	cm_prepare_el3_exit(image_type);
 }

plat/mediatek/mt6795/include/plat_macros.S

@@ -5,7 +5,6 @@
  */
 
 #include <cci.h>
-#include <gic_v2.h>
 #include <platform_def.h>
 
 .section .rodata.gic_reg_name, "aS"

plat/mediatek/mt6795/include/platform_def.h

@@ -117,10 +117,6 @@
 
 #define FIQ_SMP_CALL_SGI  MT_IRQ_SEC_SGI_5
 
-#define PLAT_ARM_G0_IRQS	FIQ_SMP_CALL_SGI
-
-#define DEBUG_XLAT_TABLE 0
-
 /*******************************************************************************
  * Platform binary types for linking
  ******************************************************************************/
@@ -132,9 +128,7 @@
  ******************************************************************************/
 
 /* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif defined(IMAGE_BL1)
+#if defined(IMAGE_BL1)
 #define PLATFORM_STACK_SIZE 0x440
 #elif defined(IMAGE_BL2)
 #define PLATFORM_STACK_SIZE 0x400
@@ -145,11 +139,10 @@
 #endif
 
 #define FIRMWARE_WELCOME_STR    "Booting Trusted Firmware\n"
-#if ENABLE_PLAT_COMPAT
-#define PLATFORM_MAX_AFFLVL     MPIDR_AFFLVL2
-#else
 #define PLAT_MAX_PWR_LVL        U(2) /* MPIDR_AFFLVL2 */
-#endif
+
+#define PLAT_MAX_RET_STATE	U(1)
+#define PLAT_MAX_OFF_STATE	U(2)
 
 #define PLATFORM_CACHE_LINE_SIZE      64
 #define PLATFORM_SYSTEM_COUNT         1
@@ -198,7 +191,8 @@
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
  ******************************************************************************/
-#define ADDR_SPACE_SIZE   (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE   (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE    (1ULL << 32)
 #define MAX_XLAT_TABLES   7
 #define MAX_MMAP_REGIONS  16
 

plat/mediatek/mt6795/plat_mt_gic.c

 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <gicv2.h>
-#include <plat_arm.h>
+#include <interrupt_props.h>
 #include <platform.h>
 #include <platform_def.h>
 
-const unsigned int g0_interrupt_array[] = {
-	PLAT_ARM_G0_IRQS
+static const interrupt_prop_t g0_interrupt_props[] = {
+	INTR_PROP_DESC(FIQ_SMP_CALL_SGI, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
 };
 
 gicv2_driver_data_t arm_gic_data = {
 	.gicd_base = BASE_GICD_BASE,
 	.gicc_base = BASE_GICC_BASE,
-	.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
-	.g0_interrupt_array = g0_interrupt_array,
+	.interrupt_props = g0_interrupt_props,
+	.interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
 };
 
 void plat_mt_gic_driver_init(void)

plat/mediatek/mt6795/plat_pm.c

@@ -5,7 +5,6 @@
  */
 
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <assert.h>
 #include <bakery_lock.h>
 #include <cci.h>

plat/mediatek/mt6795/platform.mk

@@ -26,7 +26,8 @@ PLAT_INCLUDES		:=	-I${MTK_PLAT}/common/				\
 				-Iinclude/common/tbbr/					\
 				${OEMS_INCLUDES}
 
-PLAT_BL_COMMON_SOURCES	:=	lib/aarch64/xlat_tables.c			\
+PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/aarch64/xlat_tables.c			\
+				lib/xlat_tables/xlat_tables_common.c			\
 				plat/common/plat_gic.c
 
 BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
@@ -35,7 +36,7 @@ BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				drivers/arm/gic/v2/gicv2_main.c			\
 				drivers/arm/gic/v2/gicv2_helpers.c		\
 				plat/common/plat_gicv2.c			\
-				drivers/console/console.S			\
+				drivers/console/aarch64/console.S		\
 				drivers/delay_timer/delay_timer.c		\
 				lib/cpus/aarch64/cortex_a53.S			\
 				${MTK_PLAT_SOC}/bl31_plat_setup.c		\
@@ -52,11 +53,6 @@ BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				${MTK_PLAT_SOC}/scu.c		\
 				${OEMS_SOURCES}
 
-# Flag used by the MTK_platform port to determine the version of ARM GIC
-# architecture to use for interrupt management in EL3.
-ARM_GIC_ARCH		:=	2
-$(eval $(call add_define,ARM_GIC_ARCH))
-
 # Enable workarounds for selected Cortex-A53 erratas.
 ERRATA_A53_826319	:=	1
 ERRATA_A53_836870	:=	1

plat/mediatek/mt8173/aarch64/plat_helpers.S

@@ -36,7 +36,6 @@ func platform_is_primary_cpu
 	ret
 endfunc platform_is_primary_cpu
 
-#if !ENABLE_PLAT_COMPAT
 	/* -----------------------------------------------------
 	 * unsigned int plat_my_core_pos(void);
 	 *
@@ -50,7 +49,6 @@ func plat_my_core_pos
 	add     x0, x1, x0, LSR #6
 	ret
 endfunc plat_my_core_pos
-#endif
 
 	/* ---------------------------------------------
 	 * int plat_crash_console_init(void)

plat/mediatek/mt8173/aarch64/platform_common.c

@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <bl_common.h>
 #include <cci.h>
 #include <debug.h>