Merge pull request #1587 from antonio-nino-diaz-arm/an/deprecated

Remove deprecated interfaces for all platforms

plat/mediatek/mt8173/bl31_plat_setup.c

@@ -12,6 +12,7 @@
 #include <mcucfg.h>
 #include <mmio.h>
 #include <mtcmos.h>
+#include <mtk_plat_common.h>
 #include <plat_arm.h>
 #include <plat_private.h>
 #include <platform.h>
@@ -91,19 +92,21 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  * BL2 has flushed this information to memory, so we are guaranteed to pick up
  * good data.
  ******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
-			       void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
 {
+	struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0;
+
 	console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE);
 
 	VERBOSE("bl31_setup\n");
 
-	assert(from_bl2 != NULL);
-	assert(from_bl2->h.type == PARAM_BL31);
-	assert(from_bl2->h.version >= VERSION_1);
+	assert(arg_from_bl2 != NULL);
+	assert(arg_from_bl2->h.type == PARAM_BL31);
+	assert(arg_from_bl2->h.version >= VERSION_1);
 
-	bl32_ep_info = *from_bl2->bl32_ep_info;
-	bl33_ep_info = *from_bl2->bl33_ep_info;
+	bl32_ep_info = *arg_from_bl2->bl32_ep_info;
+	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
 }
 
 /*******************************************************************************
@@ -120,11 +123,6 @@ void bl31_platform_setup(void)
 	plat_arm_gic_driver_init();
 	plat_arm_gic_init();
 
-#if ENABLE_PLAT_COMPAT
-	/* Topologies are best known to the platform. */
-	mt_setup_topology();
-#endif
-
 	/* Initialize spm at boot time */
 	spm_boot_init();
 }

plat/mediatek/mt8173/include/platform_def.h

@@ -36,11 +36,9 @@
 #define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
 
 #define PLATFORM_MAX_AFFLVL		MPIDR_AFFLVL2
-#if !ENABLE_PLAT_COMPAT
 #define PLAT_MAX_PWR_LVL		U(2)
 #define PLAT_MAX_RET_STATE		U(1)
 #define PLAT_MAX_OFF_STATE		U(2)
-#endif
 #define PLATFORM_SYSTEM_COUNT		1
 #define PLATFORM_CLUSTER_COUNT		2
 #define PLATFORM_CLUSTER0_CORE_COUNT	4

plat/mediatek/mt8173/plat_mt_gic.c

@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#include <arm_gic.h>
+
 #include <bl_common.h>
 #include <mt8173_def.h>
 #include <utils.h>

plat/mediatek/mt8173/plat_pm.c

@@ -26,7 +26,6 @@
 #include <spm_mcdi.h>
 #include <spm_suspend.h>
 
-#if !ENABLE_PLAT_COMPAT
 #define MTK_PWR_LVL0	0
 #define MTK_PWR_LVL1	1
 #define MTK_PWR_LVL2	2
@@ -36,7 +35,6 @@
 #define MTK_CLUSTER_PWR_STATE(state)	(state)->pwr_domain_state[MTK_PWR_LVL1]
 #define MTK_SYSTEM_PWR_STATE(state)	((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ?\
 			(state)->pwr_domain_state[MTK_PWR_LVL2] : 0)
-#endif
 
 #if PSCI_EXTENDED_STATE_ID
 /*
@@ -234,59 +232,6 @@ static void mt_platform_restore_context(unsigned long mpidr)
 	mt_cpu_restore(mpidr);
 }
 
-#if ENABLE_PLAT_COMPAT
-/*******************************************************************************
-* Private function which is used to determine if any platform actions
-* should be performed for the specified affinity instance given its
-* state. Nothing needs to be done if the 'state' is not off or if this is not
-* the highest affinity level which will enter the 'state'.
-*******************************************************************************/
-static int32_t plat_do_plat_actions(unsigned int afflvl, unsigned int state)
-{
-	unsigned int max_phys_off_afflvl;
-
-	assert(afflvl <= MPIDR_AFFLVL2);
-
-	if (state != PSCI_STATE_OFF)
-		return -EAGAIN;
-
-	/*
-	 * Find the highest affinity level which will be suspended and postpone
-	 * all the platform specific actions until that level is hit.
-	 */
-	max_phys_off_afflvl = psci_get_max_phys_off_afflvl();
-	assert(max_phys_off_afflvl != PSCI_INVALID_DATA);
-	if (afflvl != max_phys_off_afflvl)
-		return -EAGAIN;
-
-	return 0;
-}
-
-/*******************************************************************************
- * MTK_platform handler called when an affinity instance is about to enter
- * standby.
- ******************************************************************************/
-static void plat_affinst_standby(unsigned int power_state)
-{
-	unsigned int target_afflvl;
-
-	/* Sanity check the requested state */
-	target_afflvl = psci_get_pstate_afflvl(power_state);
-
-	/*
-	 * It's possible to enter standby only on affinity level 0 i.e. a cpu
-	 * on the MTK_platform. Ignore any other affinity level.
-	 */
-	if (target_afflvl == MPIDR_AFFLVL0) {
-		/*
-		 * Enter standby state. dsb is good practice before using wfi
-		 * to enter low power states.
-		 */
-		dsb();
-		wfi();
-	}
-}
-#else
 static void plat_cpu_standby(plat_local_state_t cpu_state)
 {
 	unsigned int scr;
@@ -298,47 +243,11 @@ static void plat_cpu_standby(plat_local_state_t cpu_state)
 	wfi();
 	write_scr_el3(scr);
 }
-#endif
 
 /*******************************************************************************
  * MTK_platform handler called when an affinity instance is about to be turned
  * on. The level and mpidr determine the affinity instance.
  ******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static int plat_affinst_on(unsigned long mpidr,
-		    unsigned long sec_entrypoint,
-		    unsigned int afflvl,
-		    unsigned int state)
-{
-	int rc = PSCI_E_SUCCESS;
-	unsigned long cpu_id;
-	unsigned long cluster_id;
-	uintptr_t rv;
-
-	/*
-	 * It's possible to turn on only affinity level 0 i.e. a cpu
-	 * on the MTK_platform. Ignore any other affinity level.
-	 */
-	if (afflvl != MPIDR_AFFLVL0)
-		return rc;
-
-	cpu_id = mpidr & MPIDR_CPU_MASK;
-	cluster_id = mpidr & MPIDR_CLUSTER_MASK;
-
-	if (cluster_id)
-		rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
-	else
-		rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
-
-	mmio_write_32(rv, sec_entrypoint);
-	INFO("mt_on[%ld:%ld], entry %x\n",
-		cluster_id, cpu_id, mmio_read_32(rv));
-
-	spm_hotplug_on(mpidr);
-
-	return rc;
-}
-#else
 static uintptr_t secure_entrypoint;
 
 static int plat_power_domain_on(unsigned long mpidr)
@@ -363,7 +272,6 @@ static int plat_power_domain_on(unsigned long mpidr)
 	spm_hotplug_on(mpidr);
 	return rc;
 }
-#endif
 
 /*******************************************************************************
  * MTK_platform handler called when an affinity instance is about to be turned
@@ -377,30 +285,6 @@ static int plat_power_domain_on(unsigned long mpidr)
  * dealt with. So do not write & read global variables across calls. It will be
  * wise to do flush a write to the global to prevent unpredictable results.
  ******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_off(unsigned int afflvl, unsigned int state)
-{
-	unsigned long mpidr = read_mpidr_el1();
-
-	/* Determine if any platform actions need to be executed. */
-	if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
-		return;
-
-	/* Prevent interrupts from spuriously waking up this cpu */
-	gicv2_cpuif_disable();
-
-	spm_hotplug_off(mpidr);
-
-	trace_power_flow(mpidr, CPU_DOWN);
-
-	if (afflvl != MPIDR_AFFLVL0) {
-		/* Disable coherency if this cluster is to be turned off */
-		plat_cci_disable();
-
-		trace_power_flow(mpidr, CLUSTER_DOWN);
-	}
-}
-#else
 static void plat_power_domain_off(const psci_power_state_t *state)
 {
 	unsigned long mpidr = read_mpidr_el1();
@@ -419,7 +303,6 @@ static void plat_power_domain_off(const psci_power_state_t *state)
 		trace_power_flow(mpidr, CLUSTER_DOWN);
 	}
 }
-#endif
 
 /*******************************************************************************
  * MTK_platform handler called when an affinity instance is about to be
@@ -433,51 +316,6 @@ static void plat_power_domain_off(const psci_power_state_t *state)
  * dealt with. So do not write & read global variables across calls. It will be
  * wise to do flush a write to the global to prevent unpredictable results.
  ******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_suspend(unsigned long sec_entrypoint,
-			  unsigned int afflvl,
-			  unsigned int state)
-{
-	unsigned long mpidr = read_mpidr_el1();
-	unsigned long cluster_id;
-	unsigned long cpu_id;
-	uintptr_t rv;
-
-	/* Determine if any platform actions need to be executed. */
-	if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
-		return;
-
-	cpu_id = mpidr & MPIDR_CPU_MASK;
-	cluster_id = mpidr & MPIDR_CLUSTER_MASK;
-
-	if (cluster_id)
-		rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
-	else
-		rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
-
-	mmio_write_32(rv, sec_entrypoint);
-
-	if (afflvl < MPIDR_AFFLVL2)
-		spm_mcdi_prepare_for_off_state(mpidr, afflvl);
-
-	if (afflvl >= MPIDR_AFFLVL0)
-		mt_platform_save_context(mpidr);
-
-	/* Perform the common cluster specific operations */
-	if (afflvl >= MPIDR_AFFLVL1) {
-		/* Disable coherency if this cluster is to be turned off */
-		plat_cci_disable();
-	}
-
-	if (afflvl >= MPIDR_AFFLVL2) {
-		disable_scu(mpidr);
-		generic_timer_backup();
-		spm_system_suspend();
-		/* Prevent interrupts from spuriously waking up this cpu */
-		gicv2_cpuif_disable();
-	}
-}
-#else
 static void plat_power_domain_suspend(const psci_power_state_t *state)
 {
 	unsigned long mpidr = read_mpidr_el1();
@@ -517,7 +355,6 @@ static void plat_power_domain_suspend(const psci_power_state_t *state)
 		gicv2_cpuif_disable();
 	}
 }
-#endif
 
 /*******************************************************************************
  * MTK_platform handler called when an affinity instance has just been powered
@@ -526,28 +363,6 @@ static void plat_power_domain_suspend(const psci_power_state_t *state)
  * was turned off prior to wakeup and do what's necessary to setup it up
  * correctly.
  ******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_on_finish(unsigned int afflvl, unsigned int state)
-{
-	unsigned long mpidr = read_mpidr_el1();
-
-	/* Determine if any platform actions need to be executed. */
-	if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
-		return;
-
-	/* Perform the common cluster specific operations */
-	if (afflvl >= MPIDR_AFFLVL1) {
-		/* Enable coherency if this cluster was off */
-		plat_cci_enable();
-		trace_power_flow(mpidr, CLUSTER_UP);
-	}
-
-	/* Enable the gic cpu interface */
-	gicv2_cpuif_enable();
-	gicv2_pcpu_distif_init();
-	trace_power_flow(mpidr, CPU_UP);
-}
-#else
 void mtk_system_pwr_domain_resume(void);
 
 static void plat_power_domain_on_finish(const psci_power_state_t *state)
@@ -574,44 +389,12 @@ static void plat_power_domain_on_finish(const psci_power_state_t *state)
 	gicv2_pcpu_distif_init();
 	trace_power_flow(mpidr, CPU_UP);
 }
-#endif
 
 /*******************************************************************************
  * MTK_platform handler called when an affinity instance has just been powered
  * on after having been suspended earlier. The level and mpidr determine the
  * affinity instance.
  ******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state)
-{
-	unsigned long mpidr = read_mpidr_el1();
-
-	/* Determine if any platform actions need to be executed. */
-	if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
-		return;
-
-	if (afflvl >= MPIDR_AFFLVL2) {
-		/* Enable the gic cpu interface */
-		plat_arm_gic_init();
-		spm_system_suspend_finish();
-		enable_scu(mpidr);
-	}
-
-	/* Perform the common cluster specific operations */
-	if (afflvl >= MPIDR_AFFLVL1) {
-		/* Enable coherency if this cluster was off */
-		plat_cci_enable();
-	}
-
-	if (afflvl >= MPIDR_AFFLVL0)
-		mt_platform_restore_context(mpidr);
-
-	if (afflvl < MPIDR_AFFLVL2)
-		spm_mcdi_finish_for_on_state(mpidr, afflvl);
-
-	gicv2_pcpu_distif_init();
-}
-#else
 static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
 {
 	unsigned long mpidr = read_mpidr_el1();
@@ -642,15 +425,7 @@ static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
 
 	gicv2_pcpu_distif_init();
 }
-#endif
 
-#if ENABLE_PLAT_COMPAT
-static unsigned int plat_get_sys_suspend_power_state(void)
-{
-	/* StateID: 0, StateType: 1(power down), PowerLevel: 2(system) */
-	return psci_make_powerstate(0, 1, 2);
-}
-#else
 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
 {
 	assert(PLAT_MAX_PWR_LVL >= 2);
@@ -658,7 +433,6 @@ static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
 	for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
 		req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF;
 }
-#endif
 
 /*******************************************************************************
  * MTK handlers to shutdown/reboot the system
@@ -690,7 +464,6 @@ static void __dead2 plat_system_reset(void)
 	panic();
 }
 
-#if !ENABLE_PLAT_COMPAT
 #if !PSCI_EXTENDED_STATE_ID
 static int plat_validate_power_state(unsigned int power_state,
 					psci_power_state_t *req_state)
@@ -775,34 +548,7 @@ void mtk_system_pwr_domain_resume(void)
 
 	plat_arm_gic_init();
 }
-#endif
-
-#if ENABLE_PLAT_COMPAT
-/*******************************************************************************
- * Export the platform handlers to enable psci to invoke them
- ******************************************************************************/
-static const plat_pm_ops_t plat_plat_pm_ops = {
-	.affinst_standby		= plat_affinst_standby,
-	.affinst_on			= plat_affinst_on,
-	.affinst_off			= plat_affinst_off,
-	.affinst_suspend		= plat_affinst_suspend,
-	.affinst_on_finish		= plat_affinst_on_finish,
-	.affinst_suspend_finish		= plat_affinst_suspend_finish,
-	.system_off			= plat_system_off,
-	.system_reset			= plat_system_reset,
-	.get_sys_suspend_power_state	= plat_get_sys_suspend_power_state,
-};
 
-/*******************************************************************************
- * Export the platform specific power ops & initialize the mtk_platform power
- * controller
- ******************************************************************************/
-int platform_setup_pm(const plat_pm_ops_t **plat_ops)
-{
-	*plat_ops = &plat_plat_pm_ops;
-	return 0;
-}
-#else
 static const plat_psci_ops_t plat_plat_pm_ops = {
 	.cpu_standby			= plat_cpu_standby,
 	.pwr_domain_on			= plat_power_domain_on,
@@ -852,4 +598,3 @@ plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
 
 	return target;
 }
-#endif

plat/mediatek/mt8173/plat_topology.c

@@ -7,31 +7,6 @@
 #include <platform_def.h>
 #include <psci.h>
 
-#if ENABLE_PLAT_COMPAT
-unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr)
-{
-	/* Report 1 (absent) instance at levels higher that the cluster level */
-	if (aff_lvl > MPIDR_AFFLVL1)
-		return PLATFORM_SYSTEM_COUNT;
-
-	if (aff_lvl == MPIDR_AFFLVL1)
-		return PLATFORM_CLUSTER_COUNT;
-
-	return mpidr & 0x100 ? PLATFORM_CLUSTER1_CORE_COUNT :
-			       PLATFORM_CLUSTER0_CORE_COUNT;
-}
-
-unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr)
-{
-	return aff_lvl <= MPIDR_AFFLVL2 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT;
-}
-
-int mt_setup_topology(void)
-{
-	/* [TODO] Make topology configurable via SCC */
-	return 0;
-}
-#else
 
 const unsigned char mtk_power_domain_tree_desc[] = {
 	/* No of root nodes */
@@ -82,4 +57,3 @@ int plat_core_pos_by_mpidr(u_register_t mpidr)
 
 	return (cpu_id + (cluster_id * 4));
 }
-#endif

plat/mediatek/mt8173/platform.mk

@@ -56,11 +56,6 @@ BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				${MTK_PLAT_SOC}/power_tracer.c			\
 				${MTK_PLAT_SOC}/scu.c
 
-# Flag used by the MTK_platform port to determine the version of ARM GIC
-# architecture to use for interrupt management in EL3.
-ARM_GIC_ARCH		:=	2
-$(eval $(call add_define,ARM_GIC_ARCH))
-
 # Enable workarounds for selected Cortex-A53 erratas.
 ERRATA_A53_826319	:=	1
 ERRATA_A53_836870	:=	1

plat/nvidia/tegra/common/tegra_bl31_setup.c

@@ -23,13 +23,13 @@
 #include <string.h>
 #include <tegra_def.h>
 #include <tegra_private.h>
+#include <utils.h>
 #include <utils_def.h>
 
 /* length of Trusty's input parameters (in bytes) */
 #define TRUSTY_PARAMS_LEN_BYTES	(4096*2)
 
 extern void memcpy16(void *dest, const void *src, unsigned int length);
-extern void zeromem16(void *mem, unsigned int length);
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
@@ -72,7 +72,7 @@ void plat_early_platform_setup(void)
 	; /* do nothing */
 }
 
-bl31_params_t *plat_get_bl31_params(void)
+struct tegra_bl31_params *plat_get_bl31_params(void)
 {
 	return NULL;
 }
@@ -112,11 +112,11 @@ plat_params_from_bl2_t *bl31_get_plat_params(void)
  * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
  * info.
  ******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
-				void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
 {
-	plat_params_from_bl2_t *plat_params =
-		(plat_params_from_bl2_t *)plat_params_from_bl2;
+	struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
+	plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
 	image_info_t bl32_img_info = { {0} };
 	uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
 
@@ -126,8 +126,8 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	 * might use custom ways to get arguments, so provide handlers which
 	 * they can override.
 	 */
-	if (from_bl2 == NULL)
-		from_bl2 = plat_get_bl31_params();
+	if (arg_from_bl2 == NULL)
+		arg_from_bl2 = plat_get_bl31_params();
 	if (plat_params == NULL)
 		plat_params = plat_get_bl31_plat_params();
 
@@ -135,14 +135,14 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	 * Copy BL3-3, BL3-2 entry point information.
 	 * They are stored in Secure RAM, in BL2's address space.
 	 */
-	assert(from_bl2);
-	assert(from_bl2->bl33_ep_info);
-	bl33_image_ep_info = *from_bl2->bl33_ep_info;
-
-	if (from_bl2->bl32_ep_info) {
-		bl32_image_ep_info = *from_bl2->bl32_ep_info;
-		bl32_mem_size = from_bl2->bl32_ep_info->args.arg0;
-		bl32_boot_params = from_bl2->bl32_ep_info->args.arg2;
+	assert(arg_from_bl2);
+	assert(arg_from_bl2->bl33_ep_info);
+	bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
+
+	if (arg_from_bl2->bl32_ep_info) {
+		bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
+		bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0;
+		bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2;
 	}
 
 	/*
@@ -191,9 +191,9 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	 * inside the TZDRAM. We check the BL32 image info to find out
 	 * the base/PC values and relocate the image if necessary.
 	 */
-	if (from_bl2->bl32_image_info) {
+	if (arg_from_bl2->bl32_image_info) {
 
-		bl32_img_info = *from_bl2->bl32_image_info;
+		bl32_img_info = *arg_from_bl2->bl32_image_info;
 
 		/* Relocate BL32 if it resides outside of the TZDRAM */
 		tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
@@ -217,7 +217,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 				 bl32_img_info.image_size);
 
 			/* clean up non-secure intermediate buffer */
-			zeromem16((void *)(uintptr_t)bl32_start,
+			zeromem((void *)(uintptr_t)bl32_start,
 				bl32_img_info.image_size);
 		}
 	}

plat/nvidia/tegra/common/tegra_common.mk

 #
-# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -13,8 +13,7 @@ PLAT_BL_COMMON_SOURCES	+=	${XLAT_TABLES_LIB_SRCS}
 
 COMMON_DIR		:=	plat/nvidia/tegra/common
 
-BL31_SOURCES		+=	drivers/arm/gic/gic_v2.c			\
-				drivers/console/aarch64/console.S		\
+BL31_SOURCES		+= 	drivers/console/aarch64/console.S		\
 				drivers/delay_timer/delay_timer.c		\
 				drivers/ti/uart/aarch64/16550_console.S		\
 				${COMMON_DIR}/aarch64/tegra_helpers.S		\

plat/nvidia/tegra/common/tegra_fiq_glue.c

@@ -12,7 +12,6 @@
 #include <context_mgmt.h>
 #include <debug.h>
 #include <denver.h>
-#include <gic_v2.h>
 #include <interrupt_mgmt.h>
 #include <platform.h>
 #include <tegra_def.h>

plat/nvidia/tegra/common/tegra_gic.c

@@ -5,11 +5,9 @@
  */
 
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <assert.h>
 #include <bl_common.h>
 #include <debug.h>
-#include <gic_v2.h>
 #include <interrupt_mgmt.h>
 #include <platform.h>
 #include <stdint.h>
@@ -188,14 +186,9 @@ static uint32_t tegra_gic_interrupt_type_to_line(uint32_t type,
 	 * both normal and secure worlds are using ARM GICv2. This parameter
 	 * will be used when the secure world starts using GICv3.
 	 */
-#if ARM_GIC_ARCH == 2
 	return gicv2_interrupt_type_to_line(TEGRA_GICC_BASE, type);
-#else
-#error "Invalid ARM GIC architecture version specified for platform port"
-#endif /* ARM_GIC_ARCH */
 }
 
-#if ARM_GIC_ARCH == 2
 /*******************************************************************************
  * This function returns the type of the highest priority pending interrupt at
  * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
@@ -296,10 +289,6 @@ static uint32_t tegra_gic_get_interrupt_type(uint32_t id)
 	return ret;
 }
 
-#else
-#error "Invalid ARM GIC architecture version specified for platform port"
-#endif /* ARM_GIC_ARCH */
-
 uint32_t plat_ic_get_pending_interrupt_id(void)
 {
 	return tegra_gic_get_pending_interrupt_id();

plat/nvidia/tegra/include/plat_macros.S

@@ -7,7 +7,6 @@
 #ifndef __PLAT_MACROS_S__
 #define __PLAT_MACROS_S__
 
-#include <gic_v2.h>
 #include <tegra_def.h>
 
 .section .rodata.gic_reg_name, "aS"

plat/nvidia/tegra/include/tegra_private.h

@@ -50,6 +50,18 @@ typedef struct irq_sec_cfg {
 	uint32_t type;
 } irq_sec_cfg_t;
 
+/*******************************************************************************
+ * Struct describing parameters passed to bl31
+ ******************************************************************************/
+struct tegra_bl31_params {
+       param_header_t h;
+       image_info_t *bl31_image_info;
+       entry_point_info_t *bl32_ep_info;
+       image_info_t *bl32_image_info;
+       entry_point_info_t *bl33_ep_info;
+       image_info_t *bl33_image_info;
+};
+
 /* Declarations for plat_psci_handlers.c */
 int32_t tegra_soc_validate_power_state(unsigned int power_state,
 		psci_power_state_t *req_state);
@@ -58,7 +70,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
 const mmap_region_t *plat_get_mmio_map(void);
 uint32_t plat_get_console_from_id(int id);
 void plat_gic_setup(void);
-bl31_params_t *plat_get_bl31_params(void);
+struct tegra_bl31_params *plat_get_bl31_params(void);
 plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
 
 /* Declarations for plat_secondary.c */

plat/nvidia/tegra/platform.mk

@@ -13,9 +13,6 @@ $(eval $(call add_define,CRASH_REPORTING))
 # enable assert() for release/debug builds
 ENABLE_ASSERTIONS	:=	1
 
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT	:=	0
-
 # enable dynamic memory mapping
 PLAT_XLAT_TABLES_DYNAMIC :=	1
 $(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))

plat/nvidia/tegra/soc/t186/plat_setup.c

@@ -217,13 +217,13 @@ void plat_gic_setup(void)
 /*******************************************************************************
  * Return pointer to the BL31 params from previous bootloader
  ******************************************************************************/
-bl31_params_t *plat_get_bl31_params(void)
+struct tegra_bl31_params *plat_get_bl31_params(void)
 {
 	uint32_t val;
 
 	val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
 
-	return (bl31_params_t *)(uintptr_t)val;
+	return (struct tegra_bl31_params *)(uintptr_t)val;
 }
 
 /*******************************************************************************

plat/qemu/platform.mk

@@ -25,12 +25,6 @@ endif
 
 include lib/libfdt/libfdt.mk
 
-# Enable new version of image loading on QEMU platforms
-LOAD_IMAGE_V2		:=	1
-ifneq ($(LOAD_IMAGE_V2),1)
-$(error Error: qemu needs LOAD_IMAGE_V2=1)
-endif
-
 ifeq ($(NEED_BL32),yes)
 $(eval $(call add_define,QEMU_LOAD_BL32))
 endif
@@ -68,8 +62,6 @@ ifneq (${TRUSTED_BOARD_BOOT},0)
     include drivers/auth/mbedtls/mbedtls_crypto.mk
     include drivers/auth/mbedtls/mbedtls_x509.mk
 
-    USE_TBBR_DEFS	:=	1
-
     AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
 				drivers/auth/crypto_mod.c		\
 				drivers/auth/img_parser_mod.c		\
@@ -181,9 +173,6 @@ ifeq ($(ARCH),aarch64)
 MULTI_CONSOLE_API	:= 1
 endif
 
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT	:= 	0
-
 BL32_RAM_LOCATION	:=	tdram
 ifeq (${BL32_RAM_LOCATION}, tsram)
   BL32_RAM_LOCATION_ID = SEC_SRAM_ID

plat/qemu/qemu_bl1_setup.c

@@ -39,7 +39,7 @@ void bl1_early_platform_setup(void)
  * does not do anything platform specific.
  *****************************************************************************/
 #ifdef AARCH32
-#define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_secure(__VA_ARGS__)
+#define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
 #else
 #define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_el3(__VA_ARGS__)
 #endif

plat/qemu/qemu_bl2_setup.c

@@ -20,103 +20,6 @@
 /* Data structure which holds the extents of the trusted SRAM for BL2 */
 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
 
-#if !LOAD_IMAGE_V2
-/*******************************************************************************
- * This structure represents the superset of information that is passed to
- * BL3-1, e.g. while passing control to it from BL2, bl31_params
- * and other platform specific params
- ******************************************************************************/
-typedef struct bl2_to_bl31_params_mem {
-	bl31_params_t bl31_params;
-	image_info_t bl31_image_info;
-	image_info_t bl32_image_info;
-	image_info_t bl33_image_info;
-	entry_point_info_t bl33_ep_info;
-	entry_point_info_t bl32_ep_info;
-	entry_point_info_t bl31_ep_info;
-} bl2_to_bl31_params_mem_t;
-
-
-static bl2_to_bl31_params_mem_t bl31_params_mem;
-
-
-meminfo_t *bl2_plat_sec_mem_layout(void)
-{
-	return &bl2_tzram_layout;
-}
-
-/*******************************************************************************
- * This function assigns a pointer to the memory that the platform has kept
- * aside to pass platform specific and trusted firmware related information
- * to BL31. This memory is allocated by allocating memory to
- * bl2_to_bl31_params_mem_t structure which is a superset of all the
- * structure whose information is passed to BL31
- * NOTE: This function should be called only once and should be done
- * before generating params to BL31
- ******************************************************************************/
-bl31_params_t *bl2_plat_get_bl31_params(void)
-{
-	bl31_params_t *bl2_to_bl31_params;
-
-	/*
-	 * Initialise the memory for all the arguments that needs to
-	 * be passed to BL3-1
-	 */
-	zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
-
-	/* Assign memory for TF related information */
-	bl2_to_bl31_params = &bl31_params_mem.bl31_params;
-	SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
-
-	/* Fill BL3-1 related information */
-	bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
-		VERSION_1, 0);
-
-	/* Fill BL3-2 related information */
-	bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
-		VERSION_1, 0);
-	bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
-		VERSION_1, 0);
-
-	/* Fill BL3-3 related information */
-	bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
-		PARAM_EP, VERSION_1, 0);
-
-	/* BL3-3 expects to receive the primary CPU MPID (through x0) */
-	bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
-
-	bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
-	SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
-		VERSION_1, 0);
-
-	return bl2_to_bl31_params;
-}
-
-/* Flush the TF params and the TF plat params */
-void bl2_plat_flush_bl31_params(void)
-{
-	flush_dcache_range((unsigned long)&bl31_params_mem,
-			sizeof(bl2_to_bl31_params_mem_t));
-}
-
-/*******************************************************************************
- * This function returns a pointer to the shared memory that the platform
- * has kept to point to entry point information of BL31 to BL2
- ******************************************************************************/
-struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
-{
-#if DEBUG
-	bl31_params_mem.bl31_ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL;
-#endif
-
-	return &bl31_params_mem.bl31_ep_info;
-}
-#endif /* !LOAD_IMAGE_V2 */
-
 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 			       u_register_t arg2, u_register_t arg3)
 {
@@ -174,7 +77,7 @@ void bl2_platform_setup(void)
 }
 
 #ifdef AARCH32
-#define QEMU_CONFIGURE_BL2_MMU(...)	qemu_configure_mmu_secure(__VA_ARGS__)
+#define QEMU_CONFIGURE_BL2_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
 #else
 #define QEMU_CONFIGURE_BL2_MMU(...)	qemu_configure_mmu_el1(__VA_ARGS__)
 #endif
@@ -231,7 +134,6 @@ static uint32_t qemu_get_spsr_for_bl33_entry(void)
 	return spsr;
 }
 
-#if LOAD_IMAGE_V2
 static int qemu_bl2_handle_post_image_load(unsigned int image_id)
 {
 	int err = 0;
@@ -305,75 +207,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
 	return qemu_bl2_handle_post_image_load(image_id);
 }
 
-#else /* LOAD_IMAGE_V2 */
-
-/*******************************************************************************
- * Before calling this function BL3-1 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL3-1 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
-					entry_point_info_t *bl31_ep_info)
-{
-	SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
-	bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-					DISABLE_ALL_EXCEPTIONS);
-}
-
-/*******************************************************************************
- * Before calling this function BL3-2 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL3-2 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
-					entry_point_info_t *bl32_ep_info)
-{
-	SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
-	bl32_ep_info->spsr = qemu_get_spsr_for_bl32_entry();
-}
-
-/*******************************************************************************
- * Before calling this function BL3-3 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL3-3 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl33_ep_info(image_info_t *image,
-					entry_point_info_t *bl33_ep_info)
-{
-
-	SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
-	bl33_ep_info->spsr = qemu_get_spsr_for_bl33_entry();
-}
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL32
- ******************************************************************************/
-void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
-{
-	/*
-	 * Populate the extents of memory available for loading BL32.
-	 */
-	bl32_meminfo->total_base = BL32_BASE;
-	bl32_meminfo->free_base = BL32_BASE;
-	bl32_meminfo->total_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
-	bl32_meminfo->free_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
-}
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL33
- ******************************************************************************/
-void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
-{
-	bl33_meminfo->total_base = NS_DRAM0_BASE;
-	bl33_meminfo->total_size = NS_DRAM0_SIZE;
-	bl33_meminfo->free_base = NS_DRAM0_BASE;
-	bl33_meminfo->free_size = NS_DRAM0_SIZE;
-}
-#endif /* !LOAD_IMAGE_V2 */
-
 uintptr_t plat_get_ns_image_entrypoint(void)
 {
 	return NS_IMAGE_OFFSET;

plat/qemu/qemu_common.c

@@ -131,7 +131,7 @@ static const mmap_region_t plat_qemu_mmap[] = {
 
 /* Define EL1 and EL3 variants of the function initialising the MMU */
 #ifdef AARCH32
-DEFINE_CONFIGURE_MMU_EL(secure)
+DEFINE_CONFIGURE_MMU_EL(svc_mon)
 #else
 DEFINE_CONFIGURE_MMU_EL(el1)
 DEFINE_CONFIGURE_MMU_EL(el3)

plat/qemu/qemu_private.h

@@ -11,7 +11,7 @@
 
 #include "../../bl1/bl1_private.h"
 
-void qemu_configure_mmu_secure(unsigned long total_base,
+void qemu_configure_mmu_svc_mon(unsigned long total_base,
 			unsigned long total_size,
 			unsigned long code_start, unsigned long code_limit,
 			unsigned long ro_start, unsigned long ro_limit,

plat/qemu/sp_min/sp_min_setup.c

@@ -5,7 +5,6 @@
  */
 
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <assert.h>
 #include <bl_common.h>
 #include <console.h>
@@ -108,9 +107,10 @@ entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
 		return NULL;
 }
 
-void sp_min_early_platform_setup(void *from_bl2, void *plat_params_from_bl2)
+void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+		u_register_t arg2, u_register_t arg3)
 {
-	bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+	bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
 
 	/* Initialize the console to provide early debug support */
 	console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
@@ -142,7 +142,7 @@ void sp_min_early_platform_setup(void *from_bl2, void *plat_params_from_bl2)
 
 void sp_min_plat_arch_setup(void)
 {
-	qemu_configure_mmu_secure(BL32_RO_BASE, BL32_END - BL32_RO_BASE,
+	qemu_configure_mmu_svc_mon(BL32_RO_BASE, BL32_END - BL32_RO_BASE,
 				  BL32_RO_BASE, BL32_RO_LIMIT,
 				  BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);