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Commit 3dd9835f authored by danh-arm's avatar danh-arm Committed by GitHub
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Merge pull request #667 from soby-mathew/sm/PSCI_lib 

Introduce PSCI library
parents bc469a84 738b1fd7
Show whitespace changes
Inline Side-by-side
include/bl31/runtime_svc.h → include/common/runtime_svc.h
View file @ 3dd9835f
/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -66,14 +66,14 @@ typedef int32_t (*rt_svc_init_t)(void);
* can be accessed using the handle pointer. The cookie parameter is reserved
* for future use
*/
typedef uint64_t (*rt_svc_handle_t)(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
typedef uintptr_t (*rt_svc_handle_t)(uint32_t smc_fid,
u_register_t x1,
u_register_t x2,
u_register_t x3,
u_register_t x4,
void *cookie,
void *handle,
uint64_t flags);
u_register_t flags);
typedef struct rt_svc_desc {
uint8_t start_oen;
uint8_t end_oen;
......@@ -127,8 +127,8 @@ CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \
* Function & variable prototypes
******************************************************************************/
void runtime_svc_init(void);
extern uint64_t __RT_SVC_DESCS_START__;
extern uint64_t __RT_SVC_DESCS_END__;
extern uintptr_t __RT_SVC_DESCS_START__;
extern uintptr_t __RT_SVC_DESCS_END__;
void init_crash_reporting(void);
#endif /*__ASSEMBLY__*/
......
include/drivers/arm/gic_v3.h
View file @ 3dd9835f
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -41,6 +41,7 @@
#include <mmio.h>
#include <stdint.h>
#include <types.h>
/* GICv3 Re-distributor interface registers & shifts */
......@@ -74,7 +75,7 @@
/*******************************************************************************
* Function prototypes
******************************************************************************/
uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr);
uintptr_t gicv3_get_rdist(uintptr_t gicr_base, u_register_t mpidr);
/*******************************************************************************
* GIC Redistributor interface accessors
......
include/drivers/arm/gicv3.h
View file @ 3dd9835f
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -170,6 +170,7 @@
#ifndef __ASSEMBLY__
#include <stdint.h>
#include <types.h>
#define gicv3_is_intr_id_special_identifier(id) \
(((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT))
......@@ -234,7 +235,7 @@
* a hash function. Otherwise, the "Processor Number" field will be used to
* access the array elements.
******************************************************************************/
typedef unsigned int (*mpidr_hash_fn)(unsigned long mpidr);
typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
typedef struct gicv3_driver_data {
uintptr_t gicd_base;
......
include/lib/aarch64/smcc_helpers.h 0 → 100644
View file @ 3dd9835f
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SMCC_HELPERS_H__
#define __SMCC_HELPERS_H__
#include <smcc.h>
#ifndef __ASSEMBLY__
#include <context.h>
/* Convenience macros to return from SMC handler */
#define SMC_RET0(_h) { \
return (uint64_t) (_h); \
}
#define SMC_RET1(_h, _x0) { \
write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X0, (_x0)); \
SMC_RET0(_h); \
}
#define SMC_RET2(_h, _x0, _x1) { \
write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X1, (_x1)); \
SMC_RET1(_h, (_x0)); \
}
#define SMC_RET3(_h, _x0, _x1, _x2) { \
write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X2, (_x2)); \
SMC_RET2(_h, (_x0), (_x1)); \
}
#define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \
write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X3, (_x3)); \
SMC_RET3(_h, (_x0), (_x1), (_x2)); \
}
/*
* Convenience macros to access general purpose registers using handle provided
* to SMC handler. These take the offset values defined in context.h
*/
#define SMC_GET_GP(_h, _g) \
read_ctx_reg(get_gpregs_ctx(_h), (_g))
#define SMC_SET_GP(_h, _g, _v) \
write_ctx_reg(get_gpregs_ctx(_h), (_g), (_v))
/*
* Convenience macros to access EL3 context registers using handle provided to
* SMC handler. These take the offset values defined in context.h
*/
#define SMC_GET_EL3(_h, _e) \
read_ctx_reg(get_el3state_ctx(_h), (_e))
#define SMC_SET_EL3(_h, _e, _v) \
write_ctx_reg(get_el3state_ctx(_h), (_e), (_v))
/* Return a UUID in the SMC return registers */
#define SMC_UUID_RET(_h, _uuid) \
SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \
((const uint32_t *) &(_uuid))[1], \
((const uint32_t *) &(_uuid))[2], \
((const uint32_t *) &(_uuid))[3])
#endif /*__ASSEMBLY__*/
#endif /* __SMCC_HELPERS_H__ */
include/common/context.h → include/lib/el3_runtime/aarch64/context.h
View file @ 3dd9835f
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -298,35 +298,35 @@ CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx),
*/
#define set_aapcs_args0(ctx, x0) do { \
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \
} while (0);
} while (0)
#define set_aapcs_args1(ctx, x0, x1) do { \
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \
set_aapcs_args0(ctx, x0); \
} while (0);
} while (0)
#define set_aapcs_args2(ctx, x0, x1, x2) do { \
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \
set_aapcs_args1(ctx, x0, x1); \
} while (0);
} while (0)
#define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \
set_aapcs_args2(ctx, x0, x1, x2); \
} while (0);
} while (0)
#define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \
set_aapcs_args3(ctx, x0, x1, x2, x3); \
} while (0);
} while (0)
#define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \
set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \
} while (0);
} while (0)
#define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \
set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
} while (0);
} while (0)
#define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \
set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \
} while (0);
} while (0)
/*******************************************************************************
* Function prototypes
......
include/common/context_mgmt.h → include/lib/el3_runtime/context_mgmt.h
View file @ 3dd9835f
/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -32,7 +32,6 @@
#define __CM_H__
#include <arch.h>
#include <bl_common.h>
/*******************************************************************************
* Forward declarations
......@@ -63,9 +62,9 @@ void cm_init_context_by_index(unsigned int cpu_idx,
void cm_prepare_el3_exit(uint32_t security_state);
void cm_el1_sysregs_context_save(uint32_t security_state);
void cm_el1_sysregs_context_restore(uint32_t security_state);
void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint);
void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint);
void cm_set_elr_spsr_el3(uint32_t security_state,
uint64_t entrypoint, uint32_t spsr);
uintptr_t entrypoint, uint32_t spsr);
void cm_write_scr_el3_bit(uint32_t security_state,
uint32_t bit_pos,
uint32_t value);
......
include/bl31/cpu_data.h → include/lib/el3_runtime/cpu_data.h
View file @ 3dd9835f
/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -78,9 +78,9 @@
******************************************************************************/
typedef struct cpu_data {
void *cpu_context[2];
uint64_t cpu_ops_ptr;
uintptr_t cpu_ops_ptr;
#if CRASH_REPORTING
uint64_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3];
u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3];
#endif
struct psci_cpu_data psci_svc_cpu_data;
#if PLAT_PCPU_DATA_SIZE
......@@ -123,14 +123,14 @@ void init_cpu_ops(void);
#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m
#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v
#define flush_cpu_data(_m) flush_dcache_range((uint64_t) \
#define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \
&(_cpu_data()->_m), \
sizeof(_cpu_data()->_m))
#define inv_cpu_data(_m) inv_dcache_range((uint64_t) \
#define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \
&(_cpu_data()->_m), \
sizeof(_cpu_data()->_m))
#define flush_cpu_data_by_index(_ix, _m) \
flush_dcache_range((uint64_t) \
flush_dcache_range((uintptr_t) \
&(_cpu_data_by_index(_ix)->_m), \
sizeof(_cpu_data_by_index(_ix)->_m))
......
include/bl31/services/psci.h → include/lib/psci/psci.h
View file @ 3dd9835f
/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -97,6 +97,12 @@
#define PSCI_NUM_CALLS 18
#endif
/* The macros below are used to identify PSCI calls from the SMC function ID */
#define PSCI_FID_MASK 0xffe0u
#define PSCI_FID_VALUE 0u
#define is_psci_fid(_fid) \
(((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE)
/*******************************************************************************
* PSCI Migrate and friends
******************************************************************************/
......@@ -296,13 +302,13 @@ typedef struct plat_psci_ops {
* migrate capability etc.
******************************************************************************/
typedef struct spd_pm_ops {
void (*svc_on)(uint64_t target_cpu);
int32_t (*svc_off)(uint64_t __unused);
void (*svc_suspend)(uint64_t max_off_pwrlvl);
void (*svc_on_finish)(uint64_t __unused);
void (*svc_suspend_finish)(uint64_t max_off_pwrlvl);
int32_t (*svc_migrate)(uint64_t from_cpu, uint64_t to_cpu);
int32_t (*svc_migrate_info)(uint64_t *resident_cpu);
void (*svc_on)(u_register_t target_cpu);
int32_t (*svc_off)(u_register_t __unused);
void (*svc_suspend)(u_register_t max_off_pwrlvl);
void (*svc_on_finish)(u_register_t __unused);
void (*svc_suspend_finish)(u_register_t max_off_pwrlvl);
int32_t (*svc_migrate)(u_register_t from_cpu, u_register_t to_cpu);
int32_t (*svc_migrate_info)(u_register_t *resident_cpu);
void (*svc_system_off)(void);
void (*svc_system_reset)(void);
} spd_pm_ops_t;
......@@ -326,19 +332,33 @@ int psci_migrate_info_type(void);
long psci_migrate_info_up_cpu(void);
int psci_features(unsigned int psci_fid);
void __dead2 psci_power_down_wfi(void);
void psci_entrypoint(void);
void psci_register_spd_pm_hook(const spd_pm_ops_t *);
uint64_t psci_smc_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
void psci_arch_setup(void);
/*
* The below API is deprecated. This is now replaced by bl31_warmboot_entry in
* AArch64.
*/
void psci_entrypoint(void) __deprecated;
/*******************************************************************************
* Forward declarations
******************************************************************************/
struct entry_point_info;
/******************************************************************************
* PSCI Library Interfaces
*****************************************************************************/
u_register_t psci_smc_handler(uint32_t smc_fid,
u_register_t x1,
u_register_t x2,
u_register_t x3,
u_register_t x4,
void *cookie,
void *handle,
uint64_t flags);
/* PSCI setup function */
int psci_setup(void);
u_register_t flags);
int psci_setup(uintptr_t mailbox_ep);
void psci_warmboot_entrypoint(void);
void psci_register_spd_pm_hook(const spd_pm_ops_t *pm);
#endif /*__ASSEMBLY__*/
......
include/bl31/services/psci_compat.h → include/lib/psci/psci_compat.h
View file @ 3dd9835f
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......
include/common/smcc_helpers.h → include/lib/smcc.h
View file @ 3dd9835f
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -28,8 +28,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SMCC_HELPERS_H__
#define __SMCC_HELPERS_H__
#ifndef __SMCC_H__
#define __SMCC_H__
/*******************************************************************************
* Bit definitions inside the function id as per the SMC calling convention
......@@ -83,7 +83,6 @@
#ifndef __ASSEMBLY__
#include <cassert.h>
#include <context.h>
#include <stdint.h>
/* Various flags passed to SMC handlers */
......@@ -93,45 +92,6 @@
#define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE))
#define is_caller_secure(_f) (!(is_caller_non_secure(_f)))
/* Convenience macros to return from SMC handler */
#define SMC_RET0(_h) { \
return (uint64_t) (_h); \
}
#define SMC_RET1(_h, _x0) { \
write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X0, (_x0)); \
SMC_RET0(_h); \
}
#define SMC_RET2(_h, _x0, _x1) { \
write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X1, (_x1)); \
SMC_RET1(_h, (_x0)); \
}
#define SMC_RET3(_h, _x0, _x1, _x2) { \
write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X2, (_x2)); \
SMC_RET2(_h, (_x0), (_x1)); \
}
#define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \
write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X3, (_x3)); \
SMC_RET3(_h, (_x0), (_x1), (_x2)); \
}
/*
* Convenience macros to access general purpose registers using handle provided
* to SMC handler. These takes the offset values defined in context.h
*/
#define SMC_GET_GP(_h, _g) \
read_ctx_reg(get_gpregs_ctx(_h), (_g));
#define SMC_SET_GP(_h, _g, _v) \
write_ctx_reg(get_gpregs_ctx(_h), (_g), (_v));
/*
* Convenience macros to access EL3 context registers using handle provided to
* SMC handler. These takes the offset values defined in context.h
*/
#define SMC_GET_EL3(_h, _e) \
read_ctx_reg(get_el3state_ctx(_h), (_e));
#define SMC_SET_EL3(_h, _e, _v) \
write_ctx_reg(get_el3state_ctx(_h), (_e), (_v));
/* The macro below is used to identify a Standard Service SMC call */
#define is_std_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \
FUNCID_OEN_MASK) == OEN_STD_START)
......@@ -154,12 +114,5 @@
{ _n0, _n1, _n2, _n3, _n4, _n5 } \
}
/* Return a UUID in the SMC return registers */
#define SMC_UUID_RET(_h, _uuid) \
SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \
((const uint32_t *) &(_uuid))[1], \
((const uint32_t *) &(_uuid))[2], \
((const uint32_t *) &(_uuid))[3])
#endif /*__ASSEMBLY__*/
#endif /* __SMCC_HELPERS_H__ */
#endif /* __SMCC_H__ */
include/lib/stdlib/machine/_stdint.h
View file @ 3dd9835f
......@@ -30,6 +30,11 @@
* $FreeBSD$
*/
/*
* Portions copyright (c) 2016, ARM Limited and Contributors.
* All rights reserved.
*/
#ifndef _MACHINE__STDINT_H_
#define _MACHINE__STDINT_H_
......@@ -38,12 +43,12 @@
#define INT8_C(c) (c)
#define INT16_C(c) (c)
#define INT32_C(c) (c)
#define INT64_C(c) (c ## L)
#define INT64_C(c) (c ## LL)
#define UINT8_C(c) (c)
#define UINT16_C(c) (c)
#define UINT32_C(c) (c ## U)
#define UINT64_C(c) (c ## UL)
#define UINT64_C(c) (c ## ULL)
#define INTMAX_C(c) INT64_C(c)
#define UINTMAX_C(c) UINT64_C(c)
......@@ -60,19 +65,19 @@
#define INT8_MIN (-0x7f-1)
#define INT16_MIN (-0x7fff-1)
#define INT32_MIN (-0x7fffffff-1)
#define INT64_MIN (-0x7fffffffffffffffL-1)
#define INT64_MIN (-0x7fffffffffffffffLL-1)
/* Maximum values of exact-width signed integer types. */
#define INT8_MAX 0x7f
#define INT16_MAX 0x7fff
#define INT32_MAX 0x7fffffff
#define INT64_MAX 0x7fffffffffffffffL
#define INT64_MAX 0x7fffffffffffffffLL
/* Maximum values of exact-width unsigned integer types. */
#define UINT8_MAX 0xff
#define UINT16_MAX 0xffff
#define UINT32_MAX 0xffffffffU
#define UINT64_MAX 0xffffffffffffffffUL
#define UINT64_MAX 0xffffffffffffffffULL
/*
* ISO/IEC 9899:1999
......
include/plat/arm/common/plat_arm.h
View file @ 3dd9835f
......@@ -45,15 +45,15 @@
/*
* Utility functions common to ARM standard platforms
*/
void arm_setup_page_tables(unsigned long total_base,
unsigned long total_size,
unsigned long code_start,
unsigned long code_limit,
unsigned long rodata_start,
unsigned long rodata_limit
void arm_setup_page_tables(uintptr_t total_base,
size_t total_size,
uintptr_t code_start,
uintptr_t code_limit,
uintptr_t rodata_start,
uintptr_t rodata_limit
#if USE_COHERENT_MEM
, unsigned long coh_start,
unsigned long coh_limit
, uintptr_t coh_start,
uintptr_t coh_limit
#endif
);
......
include/plat/common/platform.h
View file @ 3dd9835f
......@@ -83,7 +83,7 @@ uint32_t plat_interrupt_type_to_line(uint32_t type,
/*******************************************************************************
* Optional common functions (may be overridden)
******************************************************************************/
unsigned long plat_get_my_stack(void);
uintptr_t plat_get_my_stack(void);
void plat_report_exception(unsigned long);
int plat_crash_console_init(void);
int plat_crash_console_putc(int c);
......
include/bl31/services/std_svc.h → include/services/std_svc.h
View file @ 3dd9835f
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -42,10 +42,4 @@
#define STD_SVC_VERSION_MAJOR 0x0
#define STD_SVC_VERSION_MINOR 0x1
/* The macros below are used to identify PSCI calls from the SMC function ID */
#define PSCI_FID_MASK 0xffe0u
#define PSCI_FID_VALUE 0u
#define is_psci_fid(_fid) \
(((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE)
#endif /* __STD_SVC_H__ */
common/aarch64/context.S → lib/el3_runtime/aarch64/context.S
View file @ 3dd9835f
/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......
common/context_mgmt.c → lib/el3_runtime/aarch64/context_mgmt.c
View file @ 3dd9835f
/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -285,7 +285,7 @@ void cm_el1_sysregs_context_restore(uint32_t security_state)
* This function populates ELR_EL3 member of 'cpu_context' pertaining to the
* given security state with the given entrypoint
******************************************************************************/
void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint)
void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
{
cpu_context_t *ctx;
el3_state_t *state;
......@@ -303,7 +303,7 @@ void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint)
* pertaining to the given security state
******************************************************************************/
void cm_set_elr_spsr_el3(uint32_t security_state,
uint64_t entrypoint, uint32_t spsr)
uintptr_t entrypoint, uint32_t spsr)
{
cpu_context_t *ctx;
el3_state_t *state;
......
bl31/aarch64/cpu_data.S → lib/el3_runtime/aarch64/cpu_data.S
View file @ 3dd9835f
/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......
bl31/cpu_data_array.c → lib/el3_runtime/cpu_data_array.c
View file @ 3dd9835f
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......
lib/locks/bakery/bakery_lock_normal.c
View file @ 3dd9835f
......@@ -82,13 +82,13 @@ extern void *__PERCPU_BAKERY_LOCK_SIZE__;
#define write_cache_op(addr, cached) \
do { \
(cached ? dccvac((uint64_t)addr) :\
dcivac((uint64_t)addr));\
(cached ? dccvac((uintptr_t)addr) :\
dcivac((uintptr_t)addr));\
dsbish();\
} while (0)
#define read_cache_op(addr, cached) if (cached) \
dccivac((uint64_t)addr)
dccivac((uintptr_t)addr)
static unsigned int bakery_get_ticket(bakery_lock_t *lock,
unsigned int me, int is_cached)
......
services/std_svc/psci/psci_helpers.S → lib/psci/aarch64/psci_helpers.S
View file @ 3dd9835f
/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -35,6 +35,10 @@
.globl psci_do_pwrdown_cache_maintenance
.globl psci_do_pwrup_cache_maintenance
.globl psci_power_down_wfi
#if !ERROR_DEPRECATED
.globl psci_entrypoint
#endif
/* -----------------------------------------------------------------------
* void psci_do_pwrdown_cache_maintenance(unsigned int power level);
......@@ -152,3 +156,25 @@ func psci_do_pwrup_cache_maintenance
ldp x29, x30, [sp], #16
ret
endfunc psci_do_pwrup_cache_maintenance
/* -----------------------------------------------------------------------
* void psci_power_down_wfi(void);
* This function is called to indicate to the power controller that it
* is safe to power down this cpu. It should not exit the wfi and will
* be released from reset upon power up.
* -----------------------------------------------------------------------
*/
func psci_power_down_wfi
dsb sy // ensure write buffer empty
wfi
bl plat_panic_handler
endfunc psci_power_down_wfi
/* -----------------------------------------------------------------------
* void psci_entrypoint(void);
* The deprecated entry point for PSCI on warm boot for AArch64.
* -----------------------------------------------------------------------
*/
func_deprecated psci_entrypoint
b bl31_warm_entrypoint
endfunc_deprecated psci_entrypoint
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