diff --git a/include/lib/cpus/aarch32/aem_generic.h b/include/lib/cpus/aarch32/aem_generic.h index 5fbdf533897c4d315f27c428d93b9ef5e7ee07e0..1d40cec2eb7b117f39881d077742821ba9325a5d 100644 --- a/include/lib/cpus/aarch32/aem_generic.h +++ b/include/lib/cpus/aarch32/aem_generic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,9 @@ #ifndef AEM_GENERIC_H #define AEM_GENERIC_H +#include <lib/utils_def.h> + /* BASE AEM midr for revision 0 */ -#define BASE_AEM_MIDR 0x410FD0F0 +#define BASE_AEM_MIDR U(0x410FD0F0) #endif /* AEM_GENERIC_H */ diff --git a/include/lib/cpus/aarch32/cortex_a12.h b/include/lib/cpus/aarch32/cortex_a12.h index 3aa7278a6f7136560260b5ca0cc0ff5386cf74fe..8f6e7b8b0f4db1b7a98ea250646b8f95f0542280 100644 --- a/include/lib/cpus/aarch32/cortex_a12.h +++ b/include/lib/cpus/aarch32/cortex_a12.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,14 +7,16 @@ #ifndef CORTEX_A12_H #define CORTEX_A12_H +#include <lib/utils_def.h> + /******************************************************************************* * Cortex-A12 midr with version/revision set to 0 ******************************************************************************/ -#define CORTEX_A12_MIDR 0x410FC0C0 +#define CORTEX_A12_MIDR U(0x410FC0C0) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A12_ACTLR_SMP_BIT (1 << 6) +#define CORTEX_A12_ACTLR_SMP_BIT (U(1) << 6) #endif /* CORTEX_A12_H */ diff --git a/include/lib/cpus/aarch32/cortex_a15.h b/include/lib/cpus/aarch32/cortex_a15.h index ca842f6f240f23c7087b5bbf8ac601af52f59dc6..957afbdb471130fc43ec88be751dd6108eb55e24 100644 --- a/include/lib/cpus/aarch32/cortex_a15.h +++ b/include/lib/cpus/aarch32/cortex_a15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,15 +7,17 @@ #ifndef CORTEX_A15_H #define CORTEX_A15_H +#include <lib/utils_def.h> + /******************************************************************************* * Cortex-A15 midr with version/revision set to 0 ******************************************************************************/ -#define CORTEX_A15_MIDR 0x410FC0F0 +#define CORTEX_A15_MIDR U(0x410FC0F0) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A15_ACTLR_INV_BTB_BIT (1 << 0) -#define CORTEX_A15_ACTLR_SMP_BIT (1 << 6) +#define CORTEX_A15_ACTLR_INV_BTB_BIT (U(1) << 0) +#define CORTEX_A15_ACTLR_SMP_BIT (U(1) << 6) #endif /* CORTEX_A15_H */ diff --git a/include/lib/cpus/aarch32/cortex_a17.h b/include/lib/cpus/aarch32/cortex_a17.h index b5a4a90abd88c86567eea28eddf4a439ea703f23..4b05216508ef56b9a159bc2d5501e031f72447e6 100644 --- a/include/lib/cpus/aarch32/cortex_a17.h +++ b/include/lib/cpus/aarch32/cortex_a17.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,14 +7,16 @@ #ifndef CORTEX_A17_H #define CORTEX_A17_H +#include <lib/utils_def.h> + /******************************************************************************* * Cortex-A17 midr with version/revision set to 0 ******************************************************************************/ -#define CORTEX_A17_MIDR 0x410FC0E0 +#define CORTEX_A17_MIDR U(0x410FC0E0) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A17_ACTLR_SMP_BIT (1 << 6) +#define CORTEX_A17_ACTLR_SMP_BIT (U(1) << 6) #endif /* CORTEX_A17_H */ diff --git a/include/lib/cpus/aarch32/cortex_a32.h b/include/lib/cpus/aarch32/cortex_a32.h index 36322d2c0ef2f3381924c8bb63fab47fdda54907..6ddd53380ee6417eddf46fe553621548276fa61a 100644 --- a/include/lib/cpus/aarch32/cortex_a32.h +++ b/include/lib/cpus/aarch32/cortex_a32.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,14 +7,16 @@ #ifndef CORTEX_A32_H #define CORTEX_A32_H +#include <lib/utils_def.h> + /* Cortex-A32 Main ID register for revision 0 */ -#define CORTEX_A32_MIDR 0x410FD010 +#define CORTEX_A32_MIDR U(0x410FD010) /******************************************************************************* * CPU Extended Control register specific definitions. * CPUECTLR_EL1 is an implementation-specific register. ******************************************************************************/ #define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15 -#define CORTEX_A32_CPUECTLR_SMPEN_BIT (1 << 6) +#define CORTEX_A32_CPUECTLR_SMPEN_BIT (ULL(1) << 6) #endif /* CORTEX_A32_H */ diff --git a/include/lib/cpus/aarch32/cortex_a5.h b/include/lib/cpus/aarch32/cortex_a5.h index 3e58f250001794b206dd7ea86ffa186fb9664772..76703b72ac2637d64e28aa9514458e0281725d78 100644 --- a/include/lib/cpus/aarch32/cortex_a5.h +++ b/include/lib/cpus/aarch32/cortex_a5.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,14 +7,16 @@ #ifndef CORTEX_A5_H #define CORTEX_A5_H +#include <lib/utils_def.h> + /******************************************************************************* * Cortex-A8 midr with version/revision set to 0 ******************************************************************************/ -#define CORTEX_A5_MIDR 0x410FC050 +#define CORTEX_A5_MIDR U(0x410FC050) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A5_ACTLR_SMP_BIT (1 << 6) +#define CORTEX_A5_ACTLR_SMP_BIT (U(1) << 6) #endif /* CORTEX_A5_H */ diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h index a2d7ec093e12b89c6a626ddb6705b40297333654..8dd0192e68c5c49bb251367139442d6067918e3f 100644 --- a/include/lib/cpus/aarch32/cortex_a53.h +++ b/include/lib/cpus/aarch32/cortex_a53.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,30 +7,32 @@ #ifndef CORTEX_A53_H #define CORTEX_A53_H +#include <lib/utils_def.h> + /* Cortex-A53 midr for revision 0 */ -#define CORTEX_A53_MIDR 0x410FD030 +#define CORTEX_A53_MIDR U(0x410FD030) /* Retention timer tick definitions */ -#define RETENTION_ENTRY_TICKS_2 0x1 -#define RETENTION_ENTRY_TICKS_8 0x2 -#define RETENTION_ENTRY_TICKS_32 0x3 -#define RETENTION_ENTRY_TICKS_64 0x4 -#define RETENTION_ENTRY_TICKS_128 0x5 -#define RETENTION_ENTRY_TICKS_256 0x6 -#define RETENTION_ENTRY_TICKS_512 0x7 +#define RETENTION_ENTRY_TICKS_2 U(0x1) +#define RETENTION_ENTRY_TICKS_8 U(0x2) +#define RETENTION_ENTRY_TICKS_32 U(0x3) +#define RETENTION_ENTRY_TICKS_64 U(0x4) +#define RETENTION_ENTRY_TICKS_128 U(0x5) +#define RETENTION_ENTRY_TICKS_256 U(0x6) +#define RETENTION_ENTRY_TICKS_512 U(0x7) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A53_ECTLR p15, 1, c15 -#define CORTEX_A53_ECTLR_SMP_BIT (1 << 6) +#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6) -#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT 0 -#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) -#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT 3 -#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. @@ -42,25 +44,26 @@ ******************************************************************************/ #define CORTEX_A53_CPUACTLR p15, 0, c15 -#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT 44 -#define CORTEX_A53_CPUACTLR_ENDCCASCI (1 << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT) -#define CORTEX_A53_CPUACTLR_DTAH (1 << 24) +#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT U(44) +#define CORTEX_A53_CPUACTLR_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT) +#define CORTEX_A53_CPUACTLR_DTAH_SHIFT U(24) +#define CORTEX_A53_CPUACTLR_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_DTAH_SHIFT) /******************************************************************************* * L2 Auxiliary Control register specific definitions. ******************************************************************************/ #define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0 -#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) -#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) +#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14) +#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3) /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3 -#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT 0 -#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0) +#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index 2ac1e17d8d12c8bf0df82eff26dd40cc3603bc2a..f7005da3eda3f66e40bde0885fe51e24b622ad59 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,16 +10,16 @@ #include <lib/utils_def.h> /* Cortex-A57 midr for revision 0 */ -#define CORTEX_A57_MIDR 0x410FD070 +#define CORTEX_A57_MIDR U(0x410FD070) /* Retention timer tick definitions */ -#define RETENTION_ENTRY_TICKS_2 0x1 -#define RETENTION_ENTRY_TICKS_8 0x2 -#define RETENTION_ENTRY_TICKS_32 0x3 -#define RETENTION_ENTRY_TICKS_64 0x4 -#define RETENTION_ENTRY_TICKS_128 0x5 -#define RETENTION_ENTRY_TICKS_256 0x6 -#define RETENTION_ENTRY_TICKS_512 0x7 +#define RETENTION_ENTRY_TICKS_2 U(0x1) +#define RETENTION_ENTRY_TICKS_8 U(0x2) +#define RETENTION_ENTRY_TICKS_32 U(0x3) +#define RETENTION_ENTRY_TICKS_64 U(0x4) +#define RETENTION_ENTRY_TICKS_128 U(0x5) +#define RETENTION_ENTRY_TICKS_256 U(0x6) +#define RETENTION_ENTRY_TICKS_512 U(0x7) /******************************************************************************* * CPU Extended Control register specific definitions. @@ -31,7 +31,7 @@ #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) -#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0 +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) /******************************************************************************* @@ -61,19 +61,19 @@ ******************************************************************************/ #define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2 -#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) +#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) -#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3 -#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0 -#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) +#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. diff --git a/include/lib/cpus/aarch32/cortex_a7.h b/include/lib/cpus/aarch32/cortex_a7.h index 03fc118446682703f41945bdb9b1b8ab1e3dce00..730fdb5cff11f12edd5ecbd0e9c417ed70770e80 100644 --- a/include/lib/cpus/aarch32/cortex_a7.h +++ b/include/lib/cpus/aarch32/cortex_a7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,14 +7,16 @@ #ifndef CORTEX_A7_H #define CORTEX_A7_H +#include <lib/utils_def.h> + /******************************************************************************* * Cortex-A7 midr with version/revision set to 0 ******************************************************************************/ -#define CORTEX_A7_MIDR 0x410FC070 +#define CORTEX_A7_MIDR U(0x410FC070) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A7_ACTLR_SMP_BIT (1 << 6) +#define CORTEX_A7_ACTLR_SMP_BIT (U(1) << 6) #endif /* CORTEX_A7_H */ diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index 95402d0a727d3bd41cd4eda4fef2ed15deb632ed..4b1af61ca3f243275b338f79b6afe24b584acca5 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,7 @@ #include <lib/utils_def.h> /* Cortex-A72 midr for revision 0 */ -#define CORTEX_A72_MIDR 0x410FD080 +#define CORTEX_A72_MIDR U(0x410FD080) /******************************************************************************* * CPU Extended Control register specific definitions. @@ -43,12 +43,12 @@ ******************************************************************************/ #define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 -#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) +#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) -#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) +#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. diff --git a/include/lib/cpus/aarch32/cortex_a9.h b/include/lib/cpus/aarch32/cortex_a9.h index a9e86ef64a9a271590e4abb407d26a82e1d9977c..1fb0a923c1c6662ebe4fd142d172c89b986557b8 100644 --- a/include/lib/cpus/aarch32/cortex_a9.h +++ b/include/lib/cpus/aarch32/cortex_a9.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,16 +7,18 @@ #ifndef CORTEX_A9_H #define CORTEX_A9_H +#include <lib/utils_def.h> + /******************************************************************************* * Cortex-A9 midr with version/revision set to 0 ******************************************************************************/ -#define CORTEX_A9_MIDR 0x410FC090 +#define CORTEX_A9_MIDR U(0x410FC090) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A9_ACTLR_SMP_BIT (1 << 6) -#define CORTEX_A9_ACTLR_FLZW_BIT (1 << 3) +#define CORTEX_A9_ACTLR_SMP_BIT (U(1) << 6) +#define CORTEX_A9_ACTLR_FLZW_BIT (U(1) << 3) /******************************************************************************* * CPU Power Control Register diff --git a/include/lib/cpus/aarch64/aem_generic.h b/include/lib/cpus/aarch64/aem_generic.h index 1edef84da360d9b85e6b91bd33b6e9eb48405a27..6bb30a275bbe89434f05cc61472758817025e8d6 100644 --- a/include/lib/cpus/aarch64/aem_generic.h +++ b/include/lib/cpus/aarch64/aem_generic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +7,12 @@ #ifndef AEM_GENERIC_H #define AEM_GENERIC_H +#include <lib/utils_def.h> + /* BASE AEM midr for revision 0 */ -#define BASE_AEM_MIDR 0x410FD0F0 +#define BASE_AEM_MIDR U(0x410FD0F0) /* Foundation AEM midr for revision 0 */ -#define FOUNDATION_AEM_MIDR 0x410FD000 +#define FOUNDATION_AEM_MIDR U(0x410FD000) #endif /* AEM_GENERIC_H */ diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h index 2363198f6d83757494c11e8cbaba506295075c13..06788049168815bc6c43e0720601106752ba6835 100644 --- a/include/lib/cpus/aarch64/cortex_a35.h +++ b/include/lib/cpus/aarch64/cortex_a35.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,14 +7,16 @@ #ifndef CORTEX_A35_H #define CORTEX_A35_H +#include <lib/utils_def.h> + /* Cortex-A35 Main ID register for revision 0 */ -#define CORTEX_A35_MIDR 0x410FD040 +#define CORTEX_A35_MIDR U(0x410FD040) /******************************************************************************* * CPU Extended Control register specific definitions. * CPUECTLR_EL1 is an implementation-specific register. ******************************************************************************/ #define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1 -#define CORTEX_A35_CPUECTLR_SMPEN_BIT (1 << 6) +#define CORTEX_A35_CPUECTLR_SMPEN_BIT (ULL(1) << 6) #endif /* CORTEX_A35_H */ diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 4b7d238c9bb72e28dc8914c6f6f02601b7ef95b2..09db12b6eb147bd5b1875f6d5206c9daa50d5f84 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #ifndef CORTEX_A53_H #define CORTEX_A53_H +#include <lib/utils_def.h> + /* Cortex-A53 midr for revision 0 */ #define CORTEX_A53_MIDR U(0x410FD030) @@ -24,13 +26,13 @@ ******************************************************************************/ #define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1 -#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6) +#define CORTEX_A53_ECTLR_SMP_BIT (ULL(1) << 6) #define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) -#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) #define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) -#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. @@ -43,13 +45,13 @@ #define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0 #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44) -#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT) #define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27) -#define CORTEX_A53_CPUACTLR_EL1_RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT) #define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25) -#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT) #define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24) -#define CORTEX_A53_CPUACTLR_EL1_DTAH (U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT) /******************************************************************************* * L2 Auxiliary Control register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h index 763b7cbb07ab5794b5c5dc9f8bc7a1dad3825cb1..8b21e16a1deed863ca28e34aebaee0817119befd 100644 --- a/include/lib/cpus/aarch64/cortex_a55.h +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,16 +7,18 @@ #ifndef CORTEX_A55_H #define CORTEX_A55_H +#include <lib/utils_def.h> + /* Cortex-A55 MIDR for revision 0 */ -#define CORTEX_A55_MIDR 0x410fd050 +#define CORTEX_A55_MIDR U(0x410fd050) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ -#define CORTEX_A55_CORE_PWRDN_EN_MASK 0x1 +#define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) #endif /* CORTEX_A55_H */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 5b6c9dd292a69d480dd52a8f9528e58760145aa6..1e68f21a4cc732187d6240f48757888e1d28827b 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,13 +26,13 @@ ******************************************************************************/ #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 -#define CORTEX_A57_ECTLR_SMP_BIT (U(1) << 6) -#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (U(1) << 38) -#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (U(0x3) << 35) -#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (U(0x3) << 32) +#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) +#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) +#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) +#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) -#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 60b6c619011eb31287d489e4f3834272394ac33e..4a444c67aa4eb5b90c96759e875fc5f67785ac61 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,7 @@ #include <lib/utils_def.h> /* Cortex-A72 midr for revision 0 */ -#define CORTEX_A72_MIDR 0x410FD080 +#define CORTEX_A72_MIDR U(0x410FD080) /******************************************************************************* * CPU Extended Control register specific definitions. @@ -50,12 +50,12 @@ ******************************************************************************/ #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 -#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) +#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) -#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 -#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) +#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index 77ea205c24613431d60e391e1ea0af293b21fb64..3b401805a8228640ef4b308064f2720b98f8c9e7 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,15 +7,17 @@ #ifndef CORTEX_A73_H #define CORTEX_A73_H +#include <lib/utils_def.h> + /* Cortex-A73 midr for revision 0 */ -#define CORTEX_A73_MIDR 0x410FD090 +#define CORTEX_A73_MIDR U(0x410FD090) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ -#define CORTEX_A73_CPUECTLR_SMP_BIT (1 << 6) +#define CORTEX_A73_CPUECTLR_SMP_BIT (ULL(1) << 6) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. @@ -27,6 +29,6 @@ ******************************************************************************/ #define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0 -#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (1 << 3) +#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3) #endif /* CORTEX_A73_H */ diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h index fabc1afdc4a716025afb87e934038c09953763ad..204bfdd469196403bce1da1fe578f4e738dd59c9 100644 --- a/include/lib/cpus/aarch64/cortex_a75.h +++ b/include/lib/cpus/aarch64/cortex_a75.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,12 +23,12 @@ ******************************************************************************/ #define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0 -#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (1 << 35) +#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 35) /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ #define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1) -#define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4) +#define CORTEX_A75_ACTLR_AMEN_BIT (ULL(1) << 4) /* * The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index 4dea64b7aabef17c9d9b8be3784b4e034b0958bc..5779d7babe9470d4ef4dcaa1fb130f8ace499076 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,23 +7,25 @@ #ifndef CORTEX_A76_H #define CORTEX_A76_H +#include <lib/utils_def.h> + /* Cortex-A76 MIDR for revision 0 */ -#define CORTEX_A76_MIDR 0x410fd0b0 +#define CORTEX_A76_MIDR U(0x410fd0b0) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 -#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (1 << 16) +#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ -#define CORTEX_A76_CORE_PWRDN_EN_MASK 0x1 +#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) #endif /* CORTEX_A76_H */ diff --git a/include/lib/cpus/aarch64/cortex_deimos.h b/include/lib/cpus/aarch64/cortex_deimos.h index 694fb1527f7a9df91a35d851e1557d24752e8be9..9d024b6744a340c6b72dcc9f1f1f1c53f237e4fd 100644 --- a/include/lib/cpus/aarch64/cortex_deimos.h +++ b/include/lib/cpus/aarch64/cortex_deimos.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #ifndef CORTEX_DEIMOS_H #define CORTEX_DEIMOS_H +#include <lib/utils_def.h> + #define CORTEX_DEIMOS_MIDR U(0x410FD0D0) /******************************************************************************* diff --git a/include/lib/cpus/aarch64/cortex_helios.h b/include/lib/cpus/aarch64/cortex_helios.h index 571ea9df534747365e1d45aa1dead2d06cdf3860..0c11a9a4ca9f7a47da69e5a3ab783d9467a38a9b 100644 --- a/include/lib/cpus/aarch64/cortex_helios.h +++ b/include/lib/cpus/aarch64/cortex_helios.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #ifndef CORTEX_HELIOS_H #define CORTEX_HELIOS_H +#include <lib/utils_def.h> + #define CORTEX_HELIOS_MIDR U(0x410FD060) /******************************************************************************* diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h index aa8b1b1ab5c7f5a432e2374aaab00a8c2b8ee42b..b7ba28a4ac9a1ce6770578f074c63699a8b41d01 100644 --- a/include/lib/cpus/aarch64/dsu_def.h +++ b/include/lib/cpus/aarch64/dsu_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,6 +28,6 @@ /******************************************************************** * Masks applied for DSU errata workarounds * ********************************************************************/ -#define DSU_ERRATA_936184_MASK (ULL(0x3) << 15) +#define DSU_ERRATA_936184_MASK (U(0x3) << 15) #endif /* DSU_DEF_H */