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Commit 3e942205 authored by Manish Pandey's avatar Manish Pandey Committed by TrustedFirmware Code Review
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Merge "Plat FVP: Fix Generic Timer interrupt types" into integration

parents a262546f dfa6c540
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fdts/fvp-base-gicv2-psci-aarch32.dts
View file @ 3e942205
/* /*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#define REG_32 #define REG_32
#include "fvp-defs.dtsi" #include "fvp-defs.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/memreserve/ 0x80000000 0x00010000; /memreserve/ 0x80000000 0x00010000;
...@@ -100,10 +101,14 @@ ...@@ -100,10 +101,14 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>, interrupts = <GIC_PPI 13
<1 14 0xff01>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 0xff01>, <GIC_PPI 14
<1 10 0xff01>; (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>; clock-frequency = <100000000>;
}; };
......
fdts/fvp-base-gicv2-psci.dts
View file @ 3e942205
/* /*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -11,6 +11,7 @@ ...@@ -11,6 +11,7 @@
#define AFF #define AFF
#include "fvp-defs.dtsi" #include "fvp-defs.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/memreserve/ 0x80000000 0x00010000; /memreserve/ 0x80000000 0x00010000;
...@@ -99,10 +100,14 @@ ...@@ -99,10 +100,14 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>, interrupts = <GIC_PPI 13
<1 14 0xff01>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 0xff01>, <GIC_PPI 14
<1 10 0xff01>; (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>; clock-frequency = <100000000>;
}; };
......
fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
View file @ 3e942205
/* /*
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <dt-bindings/interrupt-controller/arm-gic.h>
/memreserve/ 0x80000000 0x00010000; /memreserve/ 0x80000000 0x00010000;
/ { / {
...@@ -100,10 +102,14 @@ ...@@ -100,10 +102,14 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>, interrupts = <GIC_PPI 13
<1 14 0xff01>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 0xff01>, <GIC_PPI 14
<1 10 0xff01>; (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>; clock-frequency = <100000000>;
}; };
......
fdts/fvp-base-gicv3-psci-common.dtsi
View file @ 3e942205
/* /*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <services/sdei_flags.h> #include <services/sdei_flags.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#define LEVEL 0 #define LEVEL 0
#define EDGE 2 #define EDGE 2
...@@ -161,10 +162,14 @@ ...@@ -161,10 +162,14 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>, interrupts = <GIC_PPI 13
<1 14 0xff01>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 0xff01>, <GIC_PPI 14
<1 10 0xff01>; (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>; clock-frequency = <100000000>;
}; };
......
fdts/fvp-foundation-gicv2-psci.dts
View file @ 3e942205
/* /*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#define CLUSTER_COUNT 1 #define CLUSTER_COUNT 1
#include "fvp-defs.dtsi" #include "fvp-defs.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/memreserve/ 0x80000000 0x00010000; /memreserve/ 0x80000000 0x00010000;
...@@ -100,10 +101,14 @@ ...@@ -100,10 +101,14 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>, interrupts = <GIC_PPI 13
<1 14 0xff01>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 0xff01>, <GIC_PPI 14
<1 10 0xff01>; (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>; clock-frequency = <100000000>;
}; };
......
fdts/fvp-foundation-gicv3-psci.dts
View file @ 3e942205
/* /*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#define CLUSTER_COUNT 1 #define CLUSTER_COUNT 1
#include "fvp-defs.dtsi" #include "fvp-defs.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/memreserve/ 0x80000000 0x00010000; /memreserve/ 0x80000000 0x00010000;
...@@ -109,10 +110,14 @@ ...@@ -109,10 +110,14 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>, interrupts = <GIC_PPI 13
<1 14 0xff01>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 0xff01>, <GIC_PPI 14
<1 10 0xff01>; (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>; clock-frequency = <100000000>;
}; };
......
include/dt-bindings/interrupt-controller/arm-gic.h
View file @ 3e942205
...@@ -18,4 +18,9 @@ ...@@ -18,4 +18,9 @@
#define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_HIGH 4
#define IRQ_TYPE_LEVEL_LOW 8 #define IRQ_TYPE_LEVEL_LOW 8
/*
* Interrupt specifier cell 2.
*/
#define GIC_CPU_MASK_RAW(x) ((x) << 8)
#endif #endif
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